VLSI LAB Workbook

8/10/2019 VLSI LAB Workbook

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EX.NO:01 STUDY OF SIMULATION USING XILINX ISE-9.1.i

DATE:

PROBLEM STATEMENT:

To learn about the procedure in simulation of digital designs using

XILINX ISE tool.

AIM:

To study the simulation of a digital circuit using Xilinx ISE 9.1.i

INTRODUCTION:

uring !L simulation" the simulator soft#are $eri%ed the

functionality" the timing of the design or portion of the design. The simulator

interprets &!L or &erilog code into circuit functionality and displays the

logical result of the desired !L to determine correct circuit operation.

Simulation allo#s creating and $erifying complex functions in a relati$ely

small amount of time.

Simulation ta'es place at se$eral points in the design (o#. It is one of

the %rst steps after design entry and one of the last steps after

implementation" as part of $erifying the end functionality and performance of

the design.

Simulation is an iterati$e process" #hich may re)uire repeating until

both design functionality and performance timing is met. *or a typical

design" simulation libraries

1. +ompilation of the simulation libraries,. +reation of the designs test bench-. *unctional simulation. Implementation of the design and creation of the timing simulation

netlist

/. Timing simulation

SIMULATION LIBRARIES

0ost designs are built #ith gentle code" so de$ice speci%c components

are not necessary. !o#e$er in certain cases if may be re)uired or bene%cial

to use de$ice speci%cation components in the code to achie$e the desired

circuit implementation and results #hen the component is instantiated in the

1


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design" the simulator must reference a library that describes the functionality

of the component to ensure proper simulation" XILINX pro$ides simulation

libraries for simulation primiti$es.

UNISIM library for functional simulation of XILINX primiti$es

XILINX core library for functional simulation of Xilinx primiti$es

SIMPRIM lib for timing simulation of XILINX primiti$es

TEST BENCH

To simulate your design you need both the design under test 2T3 or

unit under test 22T3 and the stimulus pro$ided by the test bench. 4 test

bench is !L code that allo#s to pro$ide a documental" repeatable set of

stimuli that is portable across di5erent simulator. 4 test bench can be as

simple as a %le #ith cloc' and input data or a more complicated %le thatincludes error chec'ing" %le input and output and conditional testing. The

test bench can be created using either of the follo#ing methods.

(i) TEXT EDITORThis is the recommended method for $erifying complex designs. It

allo#s to use all the features a$ailable in the !L language and gi$es you

(exibility in $erifying design. 4lthough this method may be more challenging

in that one must create this code" the ad$antage is that it may produce moreprecise and accurate results than using the bench #a$eform editor.

(ii) XILINX TEST BENCH WAEFORM EDITOR

This is the recommended method for $erifying less complicated

simulation tas's" and is recommended if the designer is ne# to !L

simulation. It allo#s to graphically enter the test bench to dri$e the stimulus

to the design. The same test bench can be used for both functions and

timing simulation

FUNCTIONAL SIMULATION

4fter the simulation libraries and create the test bench and design

code are compiled" one can perform functional simulation on the design.

*unctional simulation is an iterati$e process" #hich may re)uire multiple

simulations to achie$e the desired end functionality of the design.

,


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R!"#$%:

The Simulation of digital circuit using XILINX ISE69.1.i #as studied.

EX.NO:0& STUDY OF SYNTHESIS USING XILINX ISE 9.1i

DATE:

PROBLEM STATEMENT:

To learn about the procedure in digital designs synthesis using XILINX

ISE tool.

AIM:

To study the synthesis of a digital circuit using XILINX ISE 9.1i.

INTRODUCTION:

4fter design entry and optional simulation is done" the synthesis of the

design is run. The ISE soft#are include XILINX synthesis technology XST3"

#hich synthesis &!L or $erilog or mixed language designs to create X6lin'

speci%c netlist %les 'no#n as N7+ %les. XST places the N7+ %les in the

pro8ector and %le is accepted as input to translate step of the implement

design process.

XST INPUT AND OUTPUT FILES:

XST supports extensi$e &!L and $erilog subsets from the follo#ing

standards &!L IEEE 1:;ation.

In addition to N7+ %les" XST also generates the follo#ing

%les or outputs.

-


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SYNTHESIS REPORT:

This report contains the result from the synthesis run" including area

and timing estimation.

1) RTC SCHEMATIC:

This is the schematic representation of the pre6optimi>ed design sho#n

at the ?TL. This representation is in terms of generic symbols such as

address" multiples" counters" 4N and @? gates.

&) TECHNOLOGY SCHEMATIC:

This is a schematic representation of an N7+ %le sho#n in terms of

logic elements. @ptimi>ed to the target architecture or technology. It is

generated after the optimi>ation and technology.

') HDL PASSING:

uring !L passing" XST chec's #hether the !L code is corrected

and reports any syntax errors.

) HDL SYNTHESIS:

uring !L synthesis" XST analysis the !L code and attempts to infer

speci%c design building bloc's or macros for #hich it can create eAcient

technology implementations. To reduce the amount of inferred macros XST

performs a resource sho#ing chec'. This actually leads to a reduction of the

area as #ell as an increase in the cloc' fre)uency.

) LOW LEEL OPTIMI*ATION:

uring lo# le$el optimi>ation XST transforms inferred macros and

general glue logic into a technology speci%c implementation.


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RESULT:

The synthesis of digital circuit #as studied using XILINX ISE 9.1i.

EX.NO: ' STUDY OF PLACE+ ROUTE AND BAC, ANNOTATION IN

FIELD

DATE: PROGRAMMABLE GATE ARRAY (FPGA)

PROBLEM STATEMENT:

To learn about the place" route and bac' annotation in *ield

Brogrammable 7ate 4rray *B743 using XILINX ISE tool.

AIM:

To study the place" route and bac' annotation in *B74.

PLACE AND ROUTE:

Blace and route is a stage in the design of *B74 during #hich logic

elements are placed and interconnected on the grid of the *B74. 4s implied

by the name" it is composed of t#o steps" placement and routing. The %rst

step" placement in$ol$es deciding #here to place all electronic component

circuitry and logic element in a generally limited amount of space. This is

follo#ed by routing" #hich decides the exact design of all the #ires needed

to connect the placed components.

These processes are similar at a high le$el but the actual details are

$ery di5erent. Cith large si>es of the modern designs" this operation is

usually proportional by E4 tools.

MANUAL PLACING AND ROUTING:

The *B74 editor can be used to %ne tune the design and impure theperformance of the place and route process" once can be manually s#apped

components and pins as #ell as route and in route nets" Chen the design is

manually changed in *B74 editor.

Chen a group of components re)uires speci%c placements" relationally

placed macros are used to de%ne the relati$e placements.

/


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DIRECTED ROUTING:

irected routing allo#s the design to retain and timing for a small

number of loads intended sources. 4lthough it is necessary to loc' placement

so that the appropriate routing can be reproduced. The directed routing

cannot be used as placement tool.

BAC, ANNOTATION:

It is the translation of a router on %tted design to a timing simulation

netlist.

Defore timing simulation can occur the physical design information

must be translated and distributed bac' to the logical design.

NETGEN:

It is a command line program that distributes information about delays"

set up and hold timer" cloc' to out and pulse #idths found in the physical

N+ design %le bac' to the logical N7 %le.

Netgen reads an N+ as input. The N+ %le can ha$e only design as apartially or fully placed and normal routed design. 4n N70 %le created 04

is optional source is input. Netgen merges mapping information from the

optional %le #ith placement routing and timing information from N+ %le.

RESULT:


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The place" route and bac' annotation in *ield Brogrammable 7ate

4rray *B743 is studied.

EX.NO: STUDY OF DEELOPMENT TOOL FOR FPGA FOR

SCHEMATIC ENTRY

DATE:

PROBLEM STATEMENT:

To learn about the de$elopment tool for *ield Brogrammable 7ate

4rray*B743 for schematic entry using $erilog!L.

AIM:

To obtain o$er$ie# of schematic entry of the design problem through

synthesis.

REUIREMENTS:

1.Xilinx6ISE 9.1i

,.Xilinx6XST

-. B+

PROCEDURE:

1. Start the Xilinx ISE by using ST4?TB?@7?40 *ILESXilinx ISE 9.1i

Bro8ect Na$igator.

,. *ileNe# Bro8ect.

-. Enter pro8ect name and location" then clic' next.

. Select the de$ice and other category and clic' next t#ice and %nish.

/. +lic' on the symbol of *B74 de$ice and then right clic' clic' on ne#

source .

;


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RESULT

The de$elopment tool for *ield Brogrammable 7ate 4rray*B743 for

schematic entry using $erilog!L is studied.

EXPT.NO: A DESIGN AND SIMULATION OF HALF ADDER

USING ERILOGHDL

DATE:

PROBLEM STATEMENT:

Crite a program to add t#o bits using $erilog!L and $erify the

output.

AIM:

To #rite &E?IL@7 code to simulate and implement the half adder usingbeha$ioral le$el modeling.

TOOLS REUIRED:

1. B+

9


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,. Xilinx and modelsim.

THEORY:

The

!alf adder operation needs t#o binary inputs" augends and addend bits and

t#o binary outputs are sum and carry.

SumF in1Gin,3H

+arryFin1andin,H

In multi6digit addition" #e ha$e to add t#o bytes along #ith the carry of

the pre$ious digit addition. E5ecti$ely such addition re)uires addition of

three bits. This is not possible #ith the half adder.

PROGRAM:

module half adderin1"in,"sum"carry3H

66666666666Input Borts666666666666666

input in1"in,H

66666666666@utput Borts666666666666666

output sum" carryH

6666666666666+ode Starts !ere666666666

1:


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assign sumFin1Gin,3H

assign carryFin1in,3H

end module

TRUTH TABLE

IN1 IN& SUM CARRY

: 0 : :

: 1 1 :

1 : 1 :

1 1 : 1

SIMULATION OUTPUT:

11


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RESULT:

The half adder programme #as #ritten and the &E?IL@7 code is

simulated successfully.

EXPT. NO:B DESIGN AND SIMULATION OF FULL ADDER

USING ERILOGHDL

DATE:

PROBLEM STATEMENT:

Crite a program to add three bits using $erilog!L and $erify theoutput.

AIM:

To #rite &E?IL@7 code to simulate and implement the full adder using

beha$ioral le$el modeling.

TOOLS REUIRED:

1. B+,. Xilinx and model sim.

THEORY:

The

*ull adder operation needs three binary inputs" augends and addend bits and

t#o binary outputs are sum and carry.1,


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sumFin1Gin,3Gin-H

carryFin1andin,3Jin1andin-3Jin,andin-33H

*ull adder is a combinational circuit that forms the arithmetic sum of

three inputs bit. It consists of three inputs and t#o outputs. T#o of the input$ariables" denoted by 4 and D" represent the t#o signi%cant bit" to be added.

The third input +in represents the carry from the pre$ious lo#er signi%cant

position.

PROGRAM:

module full adderin1"in,"in-"sum"carry3H

66666666666Input Borts666666666666666

input in1"in,"in-H

66666666666@utput Borts666666666666666

output sum" carryH

6666666666666+ode Starts !ere666666666

assign sumFin1Gin,3Gin-H

assign carryFin1in,3Jin1in-3Jin,in-33H

end module

1-


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TRUTH TABLE

IN1 IN& IN' SUM CARRY

: : 0 : :

: : 1 1 :

: 1 : 1 :

: 1 1 : 1

1 : 0 1 :

1 : 1 : 1

1 1 : : 1

1 1 1 1 1

SIMULATION OUTPUT:

1


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RESULT:

The full adder programme #as #ritten and the &E?IL@7 code is


EXPT. NO:A DESIGN AND SIMULATION OF HALFSUBTRACTOR USING ERILOGHDL

DATE:

PROBLEM STATEMENT:

Crite a program to subtract t#o bits using $erilog!L and $erify the

output.

AIM:

To #rite &E?IL@7 code to simulate and implement the half subtractor

using beha$ioral le$el modeling.

TOOLS REUIRED:

1. B+

,. Xilinx and model sim.THEORY:

The

*ull adder operation needs three binary inputs" minuend and subtrahend bits

and t#o binary outputs are di5erence and borro#.

1/


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sumFin1Gin,3H

carryFKin1andin,3H

!alf subtractor is a combinational circuit #hich is used to perform

subtraction of t#o bits it has t#o inputs x minuend3andsubtrahend3and t#o

outputs di5erence and D borro#.

PROGRAM:

module half adderin1"in,"di5erence"borro#3H

66666666666Input Borts666666666666666

input in1"in,H

66666666666@utput Borts666666666666666

output di5erence"borro#H

6666666666666+ode Starts !ere666666666

assign di5erenceFin1Gin,3H

assign borro#FKin1in,3H

end module

1


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TRUTH TABLE:

IN1 IN& DIFFERENC

E

BORROW

: 0 : :

: 1 1 1

1 : 1 :

1 1 : :

SIMULATION OUTPUT:

1;


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RESULT:

The half subtractor program #as #ritten and the &E?IL@7 code is


EXPT. NO: B DESIGN AND SIMULATION OF FULLSUBTRACTOR USING ERILOGHDL

DATE:

PROBLEM STATEMENT:

Crite a program to subtract three bits using $erilog!L and $erify the

output.

AIM:

To #rite &E?IL@7 code to simulate and implement the full subtractor

using beha$ioral le$el modeling.

TOOLS REUIRED:


THEORY:

The

1=


19/39

*ull adder operation needs three binary inputs" minuend" subtrahend and

subtract bits and t#o binary outputs are di5erence and borro#.

i5erenceFin1Gin,3H

borro#Fin-andKin1Gin,3JKin1in,33H

!alf subtractor is a combinational circuit #hich is used to perform

subtraction of t#o bits it has t#o inputs Xminuend3"subtrahend3and

Msubtract3 t#o outputs di5erence and D borro#.

PROGRAM:

module full subtractor in1"in,"in-"di5erence"borro#3H

66666666666Input Borts666666666666666

input in1"in,"in-H

66666666666@utput Borts666666666666666

output di5erence" borro#H

6666666666666+ode Starts !ere666666666

assign di5erenceFin1Gin,Gin-3H

assign borro#Fin-Kin1Gin,3JKin1in,33H

end module

19


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TRUTH TABLE:

IN1 IN& IN' DIFFERENC

E

BORROW

: : 0 : :

: : 1 1 1

: 1 : 1 1

: 1 1 : 1

1 : 0 1 :

1 : 1 : :

1 1 : : :

1 1 1 1 1

SIMULATION OUTPUT:

,:


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RESULT:

The full subtractor program #as #ritten and the &E?IL@7 code is


EXP.NO: / DESIGN 2 SIMULATION OF ENCODER AND

DECODER USING

DATE: ERILOGHDL

PROBLEM STATEMENT: Crite a program to encode input bits using $erilog!L and $erify the

output. 4lso Crite a program to decode input bits using $erilog!L and

$erify the output.

AIM:

To design the program for encoder and decoder using $erilog

TOOLS REUIRED:

1. B+,. Xilinx and modelsim.

THEORY

In computers" encoding is the process of putting a se)uence of charactersletters" numbers" punctuation" and certain symbols3 into a speciali>ed format for

eAcient transmission or storage. ecoding is the opposite process 66 the con$ersion

of an encoded format bac' into the original se)uence of characters. Encoding and

decoding are used in data communications" net#or'ing" and storage. The term is

especially applicable to radio #ireless3 communications systems.

,1
http://searchcio-midmarket.techtarget.com/definition/characterhttp://searchmobilecomputing.techtarget.com/definition/wirelesshttp://searchcio-midmarket.techtarget.com/definition/characterhttp://searchmobilecomputing.techtarget.com/definition/wireless


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The terms encoding and decoding are often used in reference to the

processes of analog6to6digital con$ersionand digital6to6analog con$ersion. In this

sense" these terms can apply to any form of data" including text" images" audio"

$ideo" multimedia" computer programs" or signals in sensors" telemetry" and control

systems.

ENCODER: (L34i5 Di467) DECODER: (L34i5

Di467)

PROGRAM (E532!6)

GATE LEEL MODELLING:

module encoder=x"y3Hinput ;:OxH

output ,:OyH

or g1y:O"x1O"x-O"x/O"x;O3H

or g,y1O"x,O"x-O"x


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al#ays P x3

begin

case x3

=Qb:::::::1 yF :H

=Qb::::::1: yF 1H

=Qb:::::1:: yF ,H

=Qb::::1::: yF -H

=Qb:::1:::: yF H

=Qb::1::::: yF /H

=Qb:1:::::: yF


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PROGRAMME (DECODER):


module decodera"b"en"y3H

input a"bH

input enH

output -:OyH

#ire c"dH

not g1c"a3H

not g,d"b3H

and g-y:O"c"d"en3H

and gy1O"c"b"en3H

and g/y,O"a"d"en3H

and g


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al#ays Psel"out13

case sel3

-Rb:: out1 F =Rb:::::::1H

-Rb:1 out1 F =Rb::::::1:H

-Rb1: out1 F =Rb:::::1::H

-Rb11 out1 F =Rb::::1:::H

default out1 F =Rb1:::::::H

endcase

endmodule

TRUTH TABLE (DECODER):

E 4 D : 1 , -

: : : : : : :

1 : : 1 : : :

1 : 1 : 1 : :

1 1 : : : 1 :

1 1 1 : : : 1

SIMULATION OUTPUT (D!532!6):

,/


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RESULT:

The encoder and decoder programme #as #ritten and the

&E?IL@7 code is simulated successfully.

EXP.NO:8 DESIGN OF MULTIPLEXER AND DEMULTIPLEXER

USING ERILOGHDL

DATE:

PROBLEM STATEMENT:

Crite a program for multiplexing input bits using $erilog!L and $erify

the output. 4lso Crite a program to demultiplex the input bits using

$erilog!L and $erify the output.

AIM:

To design the program for multiplexer and demultiplexer using $erilog.

TOOLS REUIRED:


MULTIPLEXER

,


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TRUTH TABLE:

S1 S: @2TB2T

: : :

: 1 1

1 : ,

1 1 -

PROGRAM (M#$%i$!!6)


module muxs"d"y3H

66666666666Input Borts666666666666666

input 1:OsH input -:OdH

66666666666@utput Borts666666666666666

output yH

666666666666Internal &ariables66666666

#ire a"b"c"e"f"gH

6666666666666+ode Starts !ere666666666

not g1a"s1O3Hnot g,b"s:O3H

and g-c"a"b"d:O3H

and ge"a"s:O"d1O3H

and g/f"s1O"b"d,O3H

and g


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reg muxoutH

6666666666666+ode Starts !ere666666666

al#ays P sel or din: or din13

begin 02X

if sel FF 1Qb:3 beginmuxout F din:H

end else begin

muxout F din1 H

end

end

endmodule

SIMULATION OUTPUT (M#$%i$!!6)

DEMULTIPLEXER:

TRUTH TABLE:

S:

IB :

1

,

-

,=


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S1: : : : : : :: : 1 1 : : :: 1 : : : : :

: 1 1 : 1 : :1 : : : : : :1 : 1 : : 1 :1 1 : : : : :1 1 1 : : : 1

PROGRAM (D!M#$%i$!!6)

GATELEEL MODELLING:

module dmuxs"d"y3H66666666666Input Borts666666666666666input 1:OsHinput dH66666666666@utput Borts666666666666666output -:OyH666666666666Internal &ariables66666666#ire a"bH6666666666666+ode Starts !ere666666666not g1a"s1O3Hnot g,b"s:O3H

and g-y:O"a"b"d3Hand gy1O"a"s:O"d3Hand g/y,O"s1O"b"d3Hand g


30/39

SIMULATION OUTPUT (D!M#$%i$!!6)

-:


31/39

RESULT:

The program for 0ultiplexer and emultiplexer #as #ritten by

using &erilog and $eri%ed.

EXP.NO: 9 DESIGN OF FLIP-FLOPS USING ;!6i$34HDL

DATE:

PROBLEM STATEMENT:

Crite a program to design (ip6(ops (ip6(op and T (ip6(op3 using

$erilog!L and $erify the output.

AIM:

To design (ip6(ops using $erilog!L.

TOOLS REUIRED:

1. B+

,. Xilinx and model sim.

i) D FLIPFLOPS %=$!

*lip *lop has t#o inputs" the cloc' and the input" and one output"

. In the picture is connected to the node 4" and is connected to the

node D" so these are essentially names of the same thing. 4s can be seen in

-1


32/39

the truth table" the output is e)ual to the input on the rising edge of the

cloc'. If there is no rising cloc' edge" the output #ill remain in its current

state.

PROGRAM (D FF)

module d5asyncreset

data " ata Input

cl' " +loc' Input

reset " ?eset input

) output

3H

66666666666Input Borts666666666666666

input data" cl'" reset H

66666666666@utput Borts666666666666666

output )H


reg )H6666666666666+ode Starts !ere666666666

al#ays P posedge cl' or negedge reset3

if Kreset3 begin

) UF 1Qb:H

end else begin

) UF dataH

end

endmodule

-,


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SIMULATION OUTPUT (D FF):

ii) T FLIPFLOP

S %=$!

If the T input is high" the T (ip6(op changes state VtogglesV3 #hene$er

the cloc' input is strobed. If the T input is lo#" the (ip6(op holds the pre$ious

$alue. This beha$ior is described by the characteristic e)uation

expanding the X@?operator.

Chen T is held high" the toggle (ip6(op di$ides the cloc' fre)uency by

t#oH that is" if cloc' fre)uency is 0!>" the output fre)uency obtained from

--
http://en.wikipedia.org/wiki/Equationhttp://en.wikipedia.org/wiki/XOR_gatehttp://en.wikipedia.org/wiki/Equationhttp://en.wikipedia.org/wiki/XOR_gate


34/39

the (ip6(op #ill be , 0!>. This Vdi$ide byV feature has application in $arious

types of digital counters. 4 T (ip6(op can also be built using a W (ip6(op

PROGRAM (T FF)

module t5asyncreset

data " ata Input

cl' " +loc' Input

reset " ?eset input

) output

3H

66666666666Input Borts666666666666666

input data" cl'" reset H

66666666666@utput Borts666666666666666

output )H


reg )H

6666666666666+ode Starts !ere666666666

al#ays P posedge cl' or negedge reset3if Kreset3 begin

) UF 1Qb:H

end else if data3 begin

) UF Y )H

end

endmodule

-
http://en.wikipedia.org/wiki/Counterhttp://en.wikipedia.org/wiki/Counter


35/39

SIMULATION OUTPUT (T FF):

RESULT:

The program for (ip6(ops and T3 #as #ritten by using &erilog

and $eri%ed successfully.

EXP.NO: 10 DESIGN OF COUNTER USING ERILOGHDLDATE:

-/


36/39

PROBLEM STATEMENT:

Crite a program to design 6bit synchronous counter using $erilog!Land $erify the output.

AIM:

To design 6bit synchronous counter using $erilog!L.

TOOLS REUIRED:

1. B+

,. Xilinx and model sim.

SYMBOL 2 TRUTH TABLE

SYMBOL

PROGRAM:

module upcounter

-


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out " @utput of the counter

enable " enable for counter

cl' " cloc' Input

reset reset Input

3H

6666666666@utput Borts66666666666666

output -:O outH

666666666666Input Borts66666666666666

input enable" cl'" resetH


reg -:O outH

6666666666666+ode Starts !ere6666666

al#ays Pposedge cl'3

if reset3 begin

out UF Qb: H

end else if enable3 begin

out UF out Z 1H

end

endmodule

-;


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SCHEMATIC:

TRUTH TABLE:

The follo#ing table sho#s the contents of such a 6bit up6counter forsixteen consecuti$e cloc' cycles" assuming that the counter is initially :.

-=


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SIMULATION OUTPUT:

RESULT:

The program for 6bit synchronous counter #as #ritten by using

&erilog!L and $eri%ed successfully.

Documents

VLSI LAB Workbook