Vlsi Lab Manual2

Ex No: 1

Date

IMPLEMENTATION OF 8 BIT ALU IN FPGA

Aim:

To design 8 bit ALU with operations listed in the table and to implement the

design using Spartan 3E FPGA.

Hardware Required:

1. FPGA main board (Spartan 3E)

2. Add on card

Software required:

1. Xilinx ISE 7.1.

Procedure:

1. Start the Xilinx tool

2. Create project using the project wizard

3. Select VHDL module for writing the code in VHDL

4. Initialize the entity declaration by input and output ports entry

5. Write the architecture part o f the coding in VHDL for sliced processor

6. Synthesize and rectify the errors

7. Create a test bench waveform for the corresponding VHDL for sliced processor in

Modelsim

8. Implement it in FPGA kit by pin assignments

9. Create a bit file for the design and download the same in FPGA

10. Verify the operation of sliced processor in FPGA.

Program:

VHDL code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

1

entity aluvhdl is

Port (s : in std_logic_vector(3 downto 0);

y : out std_logic_vector(7 downto 0));

end aluvhdl;

architecture Behavioral of aluvhdl is

signal a:std_logic_vector(7 downto 0 ):="00000100";

signal b:std_logic_vector(7 downto 0 ):="00000010";

begin

process(a,b,s)

begin

case s is

when "0000" => y<=a;

when "0001" => y<=a+1;

when "0010" => y<=a-1;

when "0011" => y<=b;

when "0100" => y<=b+1;

when "0101" => y<=b-1;

when "0110" => y<=a+b;

when "0111" => y<=a-b;

when "1000" => y<= not a;

when "1001" => y<=not b;

when "1010" => y<=a and b;

when "1011" => y<=a or b;

when "1100" => y<=a nand b;

when "1101" => y<=a nor b;

when "1110" => y<=a xor b;

when "1111" => y<=a xnor b;

when others => null;

end case;

end process;

2

end Behavioral;

Verilog code:

module alv( s, y);

input [3:0] s;

output [7:0] y;

reg [7:0]y;

wire [7:0]a,b;

assign a=8'b00000001,b=8'b00000011;

always@(a,b,s)

begin

case(s)

4'b0000:y=a;

4'b0001:y=a+1;

4'b0010:y=a-1;

4'b0011:y=b;

4'b0100:y=b+1;

4'b0101:y=b-1;

4'b0110:y=a+b;

4'b0111:y=a-b;

4'b1000:y=~a;

4'b1001:y=~b;

4'b1010:y=a & b;

4'b1011:y=a | b;

4'b1100:y=~(a&b);

4'b1101:y=~(a|b);

4'b1110:y=a^b;

4'b1111:y=~(a^b);

endcase

end

endmodule

Result :

The ALU was implement using SPARTAN 3 FPGA. The output was verified.

3

Ex.No: 2

Date:

IMPLEMENTATION OF 4 BIT SLICED PROCESSOR IN FPGA

Aim:

To design and implement four bit slice ALU using XILINX FPGA Spartan 3

Hardware requirement:

Spartan 3 FPGA Main board

Add on card

Software required :

XILINX ISE 7.1

Procedure:

1. Start the Xilinx tool

2. Create project using the project wizard

3. Select VHDL module for writing the code in VHDL

4. Initialize the entity declaration by input and output ports entry

5. Write the architecture part o f the coding in VHDL for sliced processor

6. Synthesize and rectify the errors

7. Create a test bench waveform for the corresponding VHDL for sliced processor in

Modelsim

8. Implement it in FPGA kit by pin assignments

9. Create a bit file for the design and download the same in FPGA

10. Verify the operation of sliced processor in FPGA.

Program:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity alu_411bit is

port (

a,b:in std_logic_vector(3 downto 0);

4

ctrl:in std_logic_vector (3 downto 0);

ca:out std_logic;

sel:in std_logic_vector(1 downto 0);

start:in std_logic;

z:out std_logic_vector(3 downto 0));

end alu_411bit;

architecture structure1 of alu_411bit is

signal c,a1,b1:std_logic_vector(3 downto 0) ;

signal p,g:std_logic_vector(3 downto 0);

signal m:std_logic_vector(7 downto 0);

signal cin :std_logic:='0';

begin

process(ctrl,a,b,sel,c,m,a1,b1,p,g,cin)

begin

case sel is

when "00"=>

a1<="000"&a(0);

b1<="000"&b(0);

when "01"=>

a1<="00"&a( 1 downto 0);

b1<="00"&b( 1 downto 0);

when "10"=>

a1<="0"&a( 2 downto 0);

b1<="0"&b( 2 downto 0);

when "11"=>

a1<=a( 3 downto 0);

b1<=b( 3 downto 0);

when others=> null;

end case;

case ctrl is

when "0000"=> z<= a1 and b1;

5

when "0001"=> z<= a1 or b1;

when "0010"=> z<= a1 nand b1;

when "0011"=> z<= a1 nor b1;

when "0100"=> z<= a1 xor b1;

when "0101"=> z<= not(a1 xor b1);

when "0110"=> z<= a1 + b1;

p(0)<=a(0) xor b(0);

p(1)<=a(1) xor b(1);

p(2)<=a(2) xor b(2);

p(3)<=a(3) xor b(3);

g(0)<=a(0) and b(0);

g(1)<=a(1) and b(1);

g(2)<=a(2) xor b(2);

g(3)<=a(3) xor b(3);

c(0)<=g(0) or( p(0) and cin);

c(1)<=g(1) or( p(1) and c(0));

c(2)<=g(2) or( p(2) and c(1));

c(0)<=g(3) or( p(3) and c(2));

ca<=c(3);

when "0111"=>

if (a1>b1)then

z<=a1-b1;

ca<='0';

elsif (a1<b1)then

z<=b1-a1;

ca<='1';

else

ca<='0';

z<="0000";

end if;

when "1000"=>

m<=a1*b1;

6

z<=m(3 downto 0);

when "1111"=>

m<=a1*b1;

z<=m(7 downto 4);

when "1001"=>z<=a(0) & a(3 downto 1);

when "1010"=>z<= a(2 downto 0)&a(3) ;

when "1011"=>z<='0' & a(3 downto 1);

when "1100"=>z<= a(2 downto 0)&'0';

when "1101"=>z<='1' & a(3 downto 1);

when "1110"=>z<= a(2 downto 0)&'1';

when others=>null;

end case;

end process;

end structure1;

Result:

Thus the BIT SLICE ALU was simulated using Modelsim, implemented in

Spartan 3 FPGA and the output was verified.

7

Ex No:3

Date:

IMPLEMENTATION OF ALARM CONTROLLER

USING EMBEDDED CONTROLLER

Aim:

To design a 24 hour digital clock with a single alarm using PIC microcontroller.

Tools required:

PIC-Microcontroller kit

MPLAB-IDE 7.41

PIC-ISP

Data cable

Power cord

Procedure:

Step 1: Start MPLAB IDE by double clicking that icon.

Step 2: Select PIC 16F877A as target device in MPLAB device selection.

Step 3: Select MPLAB CCS C compiler as the language tool.

C:\ Program files PICC CCS C (Code Composer Studio)

Step 4: Create a project using the project wizard

Project Project Wizard Next Next Finish.

Step 5: Create a new C file and write the coding for RTC and add it to the project.

Step 6: Save the program or file with extension .c eg: ka.c

Step 7: Add Library file and linker file for the corresponding PIC in the project.

Right click in Source file Add file Open ka.c

Step 8: Project Select Language Tool Suite Ok

Project Select Language Tool Location Ok

8

Project Build options Click file name ka.c

Step 9: Enable Alternate settings + pe Ok

Project Compile Build all Ok

Step 10: Verify the output in MPLAB IDE through its registers and ports options.

Step 11: Connect the target device with PIC 16F877A to the COM port in the system.

Step 12: Program the Hex file in the target device.

Step 13: Double click the icon PIC ISP COM Port COM 1 Communication Port

Browse Select file (ka) Download Up Direction Reset Download

Succeeded

Program:

#include <16F877.H>

#use delay(clock=20000000)

#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)

#use I2C(MASTER,sda=PIN_C4,scl=PIN_C3)

unsigned int time[]={0x05,0x57}; //(seconds,minute)

unsigned int readtime[0x02];

unsigned long int second,second1,minute,minute1;

unsigned int a,b,a1,b1,c1,d1,dat;

int i,j;

unsigned char array[10]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x67};

void set_rtc_time()

{

for (i=2;i<=3;i++)

{

i2c_start();

i2c_write(0xa0 | 0x00);

i2c_write(i);

i2c_write(time[(i-2)]);

9

i2c_stop();

}

}

void get_rtc_time()

{

for (i=2;i<=3;i++)

{

delay_ms(5);

i2c_start();

i2c_write(0xa0);

i2c_write(i);

i2c_start();

i2c_write(0xa0 | 0x01);

readtime[(i-2)]= i2c_read(0);

i2c_stop();

}

}

void display_sec0()

{

delay_ms(5);

i2c_start();

i2c_write(0x44);

i2c_write(0x00);

i2c_write(array[a1]); //Display Higher Byte of seconds

i2c_write(0xf7);

i2c_stop();

}

void display_sec1()

{

delay_ms(5);

i2c_start();

10

i2c_write(0x44);

i2c_write(0x00);

i2c_write(array[b1]); //Display Lower Byte of seconds

i2c_write(0xfb);

i2c_stop();

}

void display_min0()

{

delay_ms(5);

i2c_start();

i2c_write(0x44);

i2c_write(0x00);

i2c_write(array[c1]); //Display Higher Byte of minute

i2c_write(0xfd);

i2c_stop();

}

void display_min1()

{

delay_ms(5);

i2c_start();

i2c_write(0x44);

i2c_write(0x00);

i2c_write(array[d1]); //Display Higher Byte of minute

i2c_write(0xfe);

i2c_stop();

}

void IC_Config()

{

delay_us(1000);

i2c_start();

11

i2c_write(0x44);

i2c_write(0x04); //GPIO Register

i2c_write(0x00);

i2c_write(0x00);

i2c_stop();

delay_us(1000);

i2c_start();

i2c_write(0x44);

i2c_write(0x06); //GPIO Register

i2c_write(0x00);

i2c_write(0x00);

i2c_stop();

delay_us(1000);

i2c_start();

i2c_write(0x44);

i2c_write(0x0a); //GPIO Register

i2c_write(0x01);

i2c_write(0x01);

i2c_stop();

delay_us(1000);

}

void alarm_set()

{

output_b(0xff);

if(minute==0x57)

{

if((second>=0x10)&&(second<=0x14))

{

output_high(PIN_B0);

delay_ms(10);

output_low(PIN_B0);

delay_ms(10);

12

}

}

}

void main()

{

IC_Config();

set_rtc_time();

while(1)

{

get_rtc_time();

second = readtime[0];

minute = readtime[1];

printf(" Time : %x : %x \n\r",readtime[1],readtime[0]);

a1 = (second & 0x0f);

b1 = (second & 0xf0);

b1 = b1>>0x04;

c1 = (minute & 0x0f);

d1 = (minute & 0xf0);

d1 = d1>>0x04;

display_sec0();

display_sec1();

delay_us(50);

display_min0();

display_min1();

alarm_set();

delay_us(500);

}

}

Result:

The digital clock was designed using PIC microcontroller and the design was verified

using PIC embedded trainer kit.

13

Ex.No:4

Date:

IMPLEMENTATION OF MODEL TRAIN CONTROLLER USING

EMBEDDED MICROCONTROLLER

Aim :

To design and implement the model train controller using an embedded

microcontroller.

TOOLS REQUIRED:

PIC-Microcontroller kit

MPLAB-IDE 7.41

PIC-ISP

Data cable

Power cord

PROCEDURE:

Step 1: Start MPLAB IDE by double clicking that icon.

Step 2: Select PIC 16F877A as target device in MPLAB device selection.

Step 3: Select MPLAB CCS C compiler as the language tool.

C:\ Program files PICC CCS C (Code Composer Studio)

Step 4: Create a project using the project wizard

Project Project Wizard Next Next Finish.

Step 5: Create a new C file and write the coding for RTC and add it to the project.

Step 6: Save the program or file with extension .c eg: ka.c

Step 7: Add Library file and linker file for the corresponding PIC in the project.

Right click in Source file Add file Open ka.c

Step 8: Project Select Language Tool Suite Ok

Project Select Language Tool Location Ok

14

Project Build options Click file name ka.c

Step 9: Enable Alternate settings + pe Ok

Project Compile Build all Ok

Step 10: Verify the output in MPLAB IDE through its registers and ports options.

Step 11: Connect the target device with PIC 16F877A to the COM port in the system.

Step 12: Program the Hex file in the target device.

Step 13: Double click the icon PIC ISP

COM Port COM 1 Communication Port

Browse Select file (ka) Download Up Direction Reset Download

Succeeded

Program: (FORWARD DIRECTION)

#include <16F877.H>




unsigned char data,a,b,c;

int i,j,i1,k=0x15;

unsigned char ls0[]={0x55,0x54,0x50,0x40,0x00,0x00,0x01,0x05,0x15,0x55};

//led0-led3 selector for forward direction.

unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce,0x0c0};

void init();

void initbuf();

void sensor();

void main()

{

init();

15

initbuf();

while(1)

{

start1:

for(j=0x00;j<0x09;j++)

{

i1=0x05;

for(i=0x00;i<0x09;i++)

{

start:

if(i<=0x04)

{

i2c_start();

i2c_write(sel[j]); //write the address for the deviceselection.

i2c_write(k); //write the register address.

i2c_write(ls0[i]); //write the data for lso register.

i2c_write(ls0[i1]); //write the data for ls1 register.

i1++;

}

if(j==0x08) //start the next rotation in the train.

goto start1;

if(i>=0x05)

{

i2c_start();

i2c_write(sel[j]);

i2c_write(k+1);

i2c_write(ls0[i-0x04]);

i2c_stop();

i2c_start();

i2c_write(sel[j+1]);

i2c_write(k);

i2c_write(ls0[i1-0x04]);

16

i1++;

}

if(i != 0x08)

delay_ms(300);

}

}

}

}

void init()

{

for(i=0;i<0x08;i++)

{

i2c_start();

i2c_write(sel[i]);

i2c_write(0x15);

i2c_write(0x00);

i2c_write(0x00);

i2c_stop();

}

}

void initbuf()

{

output_d(0x00); //noy glow the station2 signal.

output_low(PIN_E1);

output_high(PIN_E1);


output_low(PIN_E2);



output_low(PIN_B1);

17


}

Program: (REVERSE DIRECTION)

#include <16F877.H>

#include <stdio.h>




unsigned char a,b,c;

unsigned char ls1[]={0x55,0x15,0x05,0x01,0x00,0x00,0x40,0x50,0x54,0x55};

//led0-led3 selector for reverse direction.

unsigned char sel1[]={0x0ce,0xcc,0xca,0xc8,0xc6,0xc4,0xc2,0x0c0,0xce};

unsigned char i,i1,j,senout=0x00,senout1=0x00;

void init();

void initbuf();

void statB();

void statA();

void crossingon();

void crossingoff();

void sw();

void main()

{

init();

initbuf();

while(1)

{

start:

for(j=0x00;j<0x09;j++)

{

i1=0x05;

for(i=0x00;i<0x09;i++)

18

{

if(j==0x04)

crossingon();

if(j==0x06)

crossingoff();

if(j==0x01){

output_d(0x04); //glow the red led for station1 in forward.

output_low(PIN_E2);

output_high(PIN_E2);}

if(i<=0x04)

{

i2c_start();

i2c_write(sel1[j]); //write the address for the device selection.

i2c_write(0x06); //write the register address.

i2c_write(ls1[i]); //write the data for lso register.

i2c_start();

i2c_write(sel1[j]); //write the address for the device selection.

i2c_write(0x05); //write the register address.

i2c_write(ls1[i1]); //write the data for ls1 register.

i1++;

}

if(j==0x08) //start the next rotation in the train.

goto start;

if(i>=0x05)

{

i2c_start();

i2c_write(sel1[j]);

i2c_write(0x05);

i2c_write(ls1[i-0x04]);

19

i2c_stop();

i2c_start();

i2c_write(sel1[j+1]);

i2c_write(0x06);

i2c_write(ls1[i1-0x04]);

i1++;

}

i2c_stop();

output_low(PIN_C4);

output_low(PIN_C3);

if((j == 0x01) && (i >= 0x00)) //start the next rotation in the train.

statB();

if((j == 0x06) && (i >= 0x04)) //start the next rotation in the train.

statA();

if(senout ==0X00)

goto stop1;

senout++;

if(senout < 0X04)

delay_ms(200);

else if(senout == 0X04)

{

if(j==0x02){

ss: sw();

delay_ms(100);

if(b==0x40)

goto ss;

initbuf();

output_d(0x84); //80);

output_low(PIN_E2);


20

delay_ms(1000);

output_d(0x44); //40);

output_low(PIN_E2);


else{

ss1: sw();

if(c==0x80)

goto ss1;

output_d(0x02);

output_low(PIN_E2);


delay_ms(1000);

output_d(0x01);

output_low(PIN_E2);


}

if(j==0x05){

output_d(0xF1);

output_low(PIN_E1);


output_d(0x04); //40);

output_low(PIN_E2);


if((senout1 > 0x04) && (senout1 <=0x0a))

delay_ms(200);


delay_ms(200);

stop1:

if(senout1 == 0x00)

goto stop2;


delay_ms(200);

21


delay_ms(200);

stop2:

if(i != 0x08)

delay_ms(200);

}

}

}

}

void init()

{

for(i=0;i<0x08;i++)

{

i2c_start();

i2c_write(sel1[i]);

i2c_write(0x15);

i2c_write(0x00);

i2c_write(0x00);

i2c_stop();

}

}

void statB()

{

initbuf();


output_low(PIN_E1);


delay_ms(50); //decrement the speed for stop the train in

station1.

22

senout=0x01;

}

void statA()

{

initbuf();


output_low(PIN_E2);


delay_ms(50); //decrement the speed for stop the train in

station1.

senout=0x01;

}

void sw()

{

output_low(PIN_B4);

a=input_d(); //get the data from the buffer.


b=a;

b= b & 0x40; //check for switch1.

c=a;

c= c & 0x80; //check for switch2.

output_low(PIN_C4);

output_low(PIN_C3);

}

void initbuf()

{

output_d(0x00);

output_low(PIN_E0);



output_low(PIN_E1);


23


output_low(PIN_E2);



output_low(PIN_B1);


}

void crossingon()

{

output_d(0xF0);

output_low(PIN_E1);


output_d(0xFF);

output_low(PIN_E0);


}

void crossingoff()

{

output_d(0x01);

output_low(PIN_E1);


output_d(0x00);

output_low(PIN_E0);


}

Result:

The modern train controller was designed and verified the functionality using PIC16F877

based embedded trainer kit and found correct.

Ex.No:6

Date:

24

IMPLEMENTATION OF ELEVATOR CONTROLLER USING

EMBEDDED MICRO CONTROLLER

AIM:To move lift 1 to 4 floor from ground floor and give a beep.TOOLS REQUIRED:

Elevator kit

Keyboard

Interfacing bus

8051-Microcontroller

Power cord

PROCEDURE:

Step 1: Connect the microcontroller device with the keyboard and elevator kit.

Step 2: Design a program for the following condition using 8051 microcontroller.

i.Lift 1 moves from ground floor to fourth floor .

ii.lift 2 position in the seventh floor

iii. After reaching its position doors should be opened.

Step 3: Type the corresponding code by initializing with starting address(4100)

Step 4: Execute the program by RST GO-->Starting address(4100)Execute

Step 5: Observe the movement of lift through the LED and door opening condition using

buzzer.

Program:

org 4100h

mov a,#03hmov dptr,#0ffcchmovx @dptr,acall delaymovx @dptr,amov a,#80hmov dptr,#0ffc0hmovx @dptr,amov a,#01hmov dptr,#0ffc4hmovx @dptr,acall delaymov dptr,#0ffc0h

25

mov a,#40hmovx @dptr,acall delaymov a,#20hmovx @dptr,acall delaymov a,#10hmovx @dptr,acall delaymov a,#08hmovx @dptr,acall delaymov a,#0bhmov dptr,#0ffcchmovx @dptr,acall delaymov a,#03hmovx @dptr,a

here: sjmp heredelay: mov 31h,#0ffh

mov 30h,#0ffhd12: call delay1msd2: djnz 30h,d2

djnz 31h,d12ret

delay1ms:movtl0,#17hmov th0,#0fchcall t0delayret

t0delay: mov a,tmodanl a,#0f0horl a,#01mov tmod,asetb tr0jnb tf0,$clr tr0clr tf0retend

26

ADDRESS OP-CODE MNEMONICS DESCRIPTION

27

4100 org 4100H

start:

4100 74 03 mov a,#03h ;default open doors

4102 90 FF CC mov dptr,#stat_ou ;of lift1 & lift2

4105 F0 movx @dptr,a

4106 12 41 41 call delay

4109 74 02 mov a,#02h ;close door of lift1

410B F0 movx @dptr,a

410C 7480 mov a,#80h ;indicates lift1 is

410E 90 FF C0 mov dptr,#lift1 ;in gnd floor


4112 74 01 mov a,#01h ;indicates lift2 is

4114 90 FF C4 mov dptr,#lift2 ;in 7th floor


4118 12 41 41 call delay

411B 90 FF C0 mov dptr,#lift1

411E 74 40 mov a,#40h


4121 12 41 41 call delay

4124 74 20 mov a,#20h


4127 12 41 41 call delay

412A 74 10 mov a,#10h

412C F0 movx @dptr,a

28

412D 12 41 41 call delay

4130 74 08 mov a,#08h


4133 74 0B mov a,#0bh ;beep for door open

4135 90 FF CC mov dptr,#stat_ou


4139 12 41 41 call delay

413C 74 03 mov a,#03h ;open doors

413E F0 movx @dptr,a

413F here:

413F 80 FE sjmp here

4141 delay:

4141 75 31 0A mov count1,#10 ;for 1 seconds delay

4144 75 30 64 mov count,#100

4144 d12:

4147 12 41 51 call delay1ms

4147 d2:

414A D5 30 FA djnz count,d2

414D D5 31 F4 djnz count1,d12

4150 22 ret

4151 delay 1 ms: 1 Milli second

4151 75 8A 17 mov t10,#017h ;TL0=17h, The low

29

byte of timer()

4154 75 8C FC mov th0,#0fch ;TH0=FCh, The high

byte of timer()

4157 12 41 5B call t0delay ;Activate the timer0,

;and wait upto

415A 22

415B t0delay:

415B E5 89 mov a,tmod

415D 54 F0 anl a,#0f0h

415F 44 01 orl a,#t0_m1

4161 F5 89 mov tmod,a ; 2 Timer 0, mode 1

4163 D2 8C setb tr0 ; 1 Start the timer 0

4165 30 8D FD jnb tf0,$ ;OFFFF-(16 BIT TIMER

VALUE)+1

;Monitor timer flag 0

4168 C2 8C clr tr0 ;1 Stop the timer 0

416A C2 8D clr tf0 ;1 Clear timer flag 0

416C 22 ret ;1 Return from

subroutine

end

Result:

The elevator controller was implemented and tested using PIC micro controller.

Ex No: 7

30

Date

DESIGN OF PHASE LOCKED LOOP

Aim:

To design a phase locked loop and verify the functionality.

Software required:

Xilinx ISE 8.1.

Modelsim 5.5PE

Procedure:

1. Start the Xilinx tool ISE.

2. Create a project using the project wizard.

3. Select VHDL Module for writing the code in VHDL.

4. Initialize the entity declaration by input and output ports entry.

5. Write the architecture part of the coding in VHDL for the system of pll.

6. Compile the project

7. Select the simulate options and load the files

8. Select the view signals option and load the necessary signals.

9. Force the clock and data input and run the program.

10. View the simulated result of phase locked loop.

11. For the implementation of the phase locked loop locate the pins in the FPGA.

12. Create a bit file for the phase locked loop and download the same in the FPGA.

13. Verify the operation of phase locked loop in the FPGA.

Program:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pll is

Port ( datain : in std_logic; -- raw data input

clock : in std_logic; -- 64 bit clock

clrdcd : in std_logic; -- clear dcd when 8 ones are detected

dcd : out std_logic; -- data carrier detect output

31

rx_clock : out std_logic; -- recovered rx clock

dataout : out std_logic);-- received data output

end pll;

architecture Behavioral of pll is

signal counter : std_logic_vector(4 downto 0):= "00000"; -- counter 0...31

signal dcd_cntr : std_logic_vector(7 downto 0):= "00000000"; -- counter 0...255

signal edge : std_logic; --- edge detector output : data decision changed

signal dly_data : std_logic; -- delayed data for edge detector

signal q1 : std_logic; -- late clock

signal qe : std_logic; -- early clock

signal enable : std_logic; -- gets toggled every clock or when clock has to be adjusted

signal increment : std_logic := '0';

signal decrement : std_logic := '0';

signal clear_dcd : std_logic := '0';

signal reset_dcd : std_logic := '0';

begin

--- recovered rx clock for following stages

rx_clock <= counter(4);

process(clock, clrdcd, reset_dcd)

begin

if(clock'event and clock = '1') then

clear_dcd <= reset_dcd or clrdcd;

end if;

end process;

--- clock in new data

process(clock, datain)

begin


dataout <= datain;

end if;

end process;

32

-- rx clock counter

process(clock, enable, clrdcd)

begin


if(enable = '1') then

counter <= counter + '1'; -- increase counter

else

counter <= counter;

end if;

end if;

end process;

-- set early and late clocks

process(counter)

begin

if(counter = "10000" or counter = "01111") then

q1 <= '0';

qe <= '0';

elsif (counter(4) = '1') then --- late clock when counter > 32

q1 <= '1';

qe <= '0';

else

q1 <= '0'; --- early clock when counter < 31

qe <= '1';

end if;

end process;

-- adjust rx clock

process(clock, enable, clrdcd)

begin


--- increment clock when edge detect during early clock

if(qe = '1' and edge = '1') then

increment <= '1';

33

end if;

--- decrement clock when edge detect during late clock

if(qe = '1' and edge = '1') then

decrement <= '1';

end if;

--- clear after one step increment

if (enable = '1') then

if (increment = '1') then

increment <= '0';

enable <= '1';

else

enable <= '0';

end if;

else

--- clear after one step decrement

if (decrement = '1') then

decrement <= '0';

enable <= '0';

else

enable <= '1';

end if;

end if;

end if;

end process;

-- dcd detection

process(clock, edge, counter, clear_dcd)

begin

if(clear_dcd = '1') then

dcd_cntr <= (others => '0');

dcd <= '0';

reset_dcd <= '0';

elsif(counter(4)'event and counter(4) = '0') then

34

if(edge = '0') then -- sample at rising edge, if no data change increase

counter

if(dcd_cntr = 255) then

dcd <= '1'; -- assert dcd if dcd counter is at max

dcd_cntr <= dcd_cntr;

else

dcd <= '0';

dcd_cntr <= dcd_cntr + '1';

end if;

else

reset_dcd <= '1';

end if;

end if;

end process;

--- edge detector, input data has changed

process(clock, datain)

begin

if(clock'event and clock ='1') then

edge <= dly_data xor datain;

dly_data <= datain;

end if;

end process;

end Behavioral;

Result:

Thus the phase locked loop was designed and the functionality was verified using

Modelsim 5.5 PE.

35

Documents

Vlsi Lab Manual2