VLSI LAB-1

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AVANTHIS St.THERESSA INSTITUTE OF ENGG

&TECHNOLOGY::GARIVIDI

Vizianagaram Dist.(A.P)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

NAME: _________________________________________

ROLL NO: ______________________________________

BRANCH: ______________________________________

LABORATORY: _______________________________

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AVANTHIS St.THERESSA INSTITUTE OF ENGG

&TECHNOLOGY::GARIVIDI

Vizianagaram Dist.(A.P)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

THIS IS TO CERTIFY THAT THIS IS THE BONAFIDE RECORD OF THE WORK DONE IN

LABORATORY BY

MR./MS. BEARING REGD.

NO./ROLL NO OF COURSE DURING

Total Numbers of Total Numbers of

Experiments held Experiments done .

LAB-IN-CHARGE HEAD OF THE

DEPARTMENT

SIGNATURE OF EXTERNAL EXAMINER

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1. REALIZATION OF LOGIC GATES

AIM: To write a VHDL code logic gates and verify its functionality in both Software simulatorand Hardware kit.

HARDWARE REQUIREMENT: Xilinx Spartan 3E, adaptor, connecting cable, PC system.

SOFTWARE REQUIREMENT: Xilinx ISE 10.1, modelsim 6.5b.

AND GATE:

OR GATE:

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NAND GATE:

NOT GATE:

XOR GATE:

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XNOR GATE:

PROGRAM CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logicgates isport ( a: in std_logic;b: in std_logic;y: out std_logic_vector(7 downto 0));

End logicgates;

architecture Behavioral of logicgates isbegin

y(0)

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LOGIC APPROACH:

AND GATE:

The AND gate is an electronic circuit that gives a highoutput (1) only if all its inputs are

high. A dot (.) is used to show the AND operation i.e. A.B.

OR GATE:

The OR gate is an electronic circuit that gives a high output (1) if one or moreof its

inputs are high. A plus (+) is used to show the OR operation.

NAND GATE:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The

outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with

a small circle on the output. The small circle represents inversion.

NOR GATE:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The

outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a

small circle on the output. The small circle represents inversion.

NOT GATE:

The NOT gate is an electronic circuit that produces an inverted version of the input at its

output. It is also known as an inverter. If the input variable is A, the inverted output is known as

NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The

diagrams below show two ways that the NAND logic gate can be configured to produce a NOT

gate. It can also be done using NOR logic gates in the same way.

EXOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both,

of its two inputs are high. An encircled plus sign is used to show the Ex-OR operation.

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EXNOR GATE:

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low

output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a

small circle on the output. The small circle represents inversion.

RESULT ANALYSIS:

SOFTWARE: In the software analysis, we are going to force the input logic condition in the

simulation software (modelsim) and simulate the waveform for the given input. The functionality

of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORM:-

CONCLUSION:

Hence the VHDL code for the realization of logic gates has been verified and

the simulation waveform has been observed.

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2. PRIORITY ENCODER

AIM: To write a VHDL/Verilog HDL code for 8-3 Priority encoder and verify its functionalityin both Software simulator and Hardware kit.



CIRCUIT DIAGRAM:

TRUTH TABLE:

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VERILOG CODE:

module pencoder(DI,CLK,DO);

input [7:0] DI;

input CLK;

output reg [2:0] DO;

always@(posedge CLK)

begin

if(DI[7]==1'b1)

DO=3'b111;

else if (DI[7]==1'b0 && DI[6]==1'b1)

DO=3'b110;

else if(DI[7:6]==2'b00 && DI[5]==1'b1)

DO=3'b101;

else if(DI[7:5]==3'b000 && DI[4]==1'b1)

DO=3'b100;

else if(DI[7:4]==4'b0000 && DI[3]==1'b1)

DO=3'b011;

else if(DI[7:3]==5'b00000 && DI[2]==1'b1)

DO=3'b010;

else if(DI[7:2]==6'b000000 && DI[1]==1'b1)

DO=3'b001;

else if(DI[7:1]==7'b0000000 && DI[0]==1'b1)

DO=3'b000;end

endmodule

LOGIC APPROACH:-

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a

smaller number of outputs. The output of a priority encoder is the binary representation of the

original number starting from zero of the most significant input bit. They are often used to

control interrupt requests by acting on the highest priority request.

RESULT ANALYSIS:


simulation software (modelsim) and simulate the waveform for the given input . The

functionality of the circuit is verified by observing the waveform obtained.

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SIMULATION WAVEFORMS:

CONCLUSION:

Hence the VHDLVerilog HDL code for the Priority encoder has been verified and the

simulation waveform has been observed.

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3. RANDOM COUNTER

AIM: To write a VHDL code for 4-bit Random counter and verify its functionality in both

Software simulator and Hardware kit.


SOFTWARE REQUIREMENT: Xilinx ISE 10.1 , modelsim 6.5b.

RANDOM COUNTER CIRCUIT DIAGRAMS AND TRUTH TABLES:

CIRCUIT DIAGRAM:

TRUTH TABLE:

Enable(en) Clock(clk) Clear(clr) Q(output)

0 x x 0000

0 1 1 0000

1 1 1 0001

1 1 1 0010

1 1 1 0011

1 1 1 0100

1 1 1 0101

1 1 1 0110

1 1 1 0111

1 1 1 10001 1 1 1001

1 1 1 1010

1 1 1 1011

1 1 1 1100

1 1 1 1101

1 1 1 1110

1 1 1 1111

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q=~q;

end

end

endmodule

module random(o,clk);

output [3:0]o;

input clk;

xor (t0,o[3],o[2]);

assign t1=o[0];

assign t2=o[1];

assign t3=o[2];

tff u1(o[0],t0,clk);

tff1 u2(o[1],t1,clk);



endmodule

LOGIC APPROACH:

A Random counter counts from 0 to 2N

-1, where N is the number of bits/flip-flops in the

counter. Each flip-flop is used to represent one bit. The flip-flop in the lowest-order position is

complemented/toggled with every clock pulse and a flip-flop in any other position is

complemented on the next clock pulse provided all the bits in the lower-order positions are equal

to 1.

RESULT ANALYSIS:



functionality of the circuit is verified by observing the waveform obtained.

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CONCLUSION:

Hence the Verilog HDL code for the random counter has been verified and the simulation

waveform has been observed.

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4. SYNCHRONOUS RAM.

AIM: To write a VHDL code for 4-bit Synchronous RAM and verify its functionality in bothSoftware simulator and Hardware kit.



CIRCUIT DIAGRAM:

TRUTH TABLE:

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VHDL PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity synram is

generic (DATA_WIDTH :integer := 8;

ADDR_WIDTH :integer := 8 );

Port ( clk : in STD_LOGIC;

address : in STD_LOGIC_VECTOR (7 downto 0);

data : inout STD_LOGIC_VECTOR (7 downto 0);

cs : in STD_LOGIC;

we : in STD_LOGIC;

oe : in STD_LOGIC);end synram;

architecture Behavioral of synram is

----------------Internal variables----------------

constant RAM_DEPTH :integer := 2**ADDR_WIDTH;

signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range )of std_logic_vector

(DATA_WIDTH-1 downto 0);

signal mem : RAM (0 to RAM_DEPTH-1);

begin

-- Memory Write Block

-- Write Operation : When we = 1, cs = 1

MEM_WRITE:process (clk)

begin

if (rising_edge(clk)) then

if (cs = '1' and we = '1') then

mem(conv_integer(address))

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-- Memory Read Block

-- Read Operation : When we = 0, oe = 1, cs = 1

MEM_READ:process (clk) begin


if (cs = '1' and we = '0' and oe = '1') then

data_out

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CONCLUSION:

Hence the VHDL code for the synchronous RAM has been verified and the simulation

waveform has been observed.

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5. ALU

AIM: To write a VHDL code for 8-bit ALU and verify its functionality in both Software

simulator and Hardware kit.



CIRCUIT DIAGRAM:

TRUTH TABLE:

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VHDL PROGRAM:

library IEEE;




entity alu is

Port ( S : in STD_LOGIC_VECTOR (2 downto 0);

A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

F : out STD_LOGIC_VECTOR (7 downto 0));

end alu;

architecture Behavioral of alu is

beginPROCESS(S,A,B)

BEGIN

CASE S IS

WHEN "000"=> ---clear

F ---subtraction

F ---subtraction

F ---addition

F ---xor

F ---or

F ---and

F ---preset

F

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LOGIC APPROACH:

An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and

arithmetic micro-operations on a pair of n-bit operands (ex. A [3:0] and B [3:0]). The operations

performed by an ALU are controlled by a set of function-select inputs.

RESULT ANALYSIS:


simulation software (modelsim) and simulate the waveform for the given input. The functionality

of the circuit is verified by observing the waveform obtained.


CONCLUSION:

Hence the VHDL for the ALU has been verified and the simulation waveforms have been

observed

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6. UART MODEL

AIM: To write a VHDL code for 8-bit UART model and verify its functionality in both Software




TRANSMITTER FSM:

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VHDL PROGRAM:

UART RX:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;


entity Ruart is

Port ( RST : in STD_LOGIC;

CLK : in STD_LOGIC;

Dout : out STD_LOGIC_VECTOR (7 downto 0);

Rx : in STD_LOGIC;

RxRDY: out std_logic);

end Ruart;

architecture Behavioral of Ruart is

TYPE state_type IS (Idle, Start_Rx, Shift_Rx,Stop_Rx);

signal RxFSM: state_type;

signal TopRx:std_logic;

signal Rx_Reg: std_logic_vector( 7 downto 0);

signal RxBitCnt: integer range 0 to 10:=0;

constant NDBits: integer :=8;

beginRx_FSM: process (RST, CLK)

begin

if RST='1' then

Rx_Reg '0');

Dout '0');

RxBitCnt

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RxRDY -- wait on first data bit

if TopRx='1' then

RxFSM

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UART TX:

library IEEE;




entity suart is

Port ( RST : in STD_LOGIC;

CLK : in STD_LOGIC;

Din : in STD_LOGIC_VECTOR (7 downto 0);

LoaD : in STD_LOGIC;

TxBusy: out std_logic;

TX : out STD_LOGIC);

end suart;

architecture Behavioral of suart is

TYPE state_type IS (Idle, Load_Tx, Shift_Tx,Stop_Tx);

signal TxFSM: state_type;

signal RegDin: std_logic_vector(7 downto 0);

signal TopTx:std_logic;

signal Tx_Reg: std_logic_vector( 9 downto 0);

signal TxBitCnt: integer range 0 to 10:=0;

constant NDBits: integer :=8;

beginTX

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TxFSM

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RESULT ANALYSIS:



functionality of the gate is verified by observing the waveform obtained.

SIMULATION WAVEFORMS :( FOR UART RX)

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SIMULATION WAVEFORM :( For UART TX)

CONCLUSION:

Hence the VHDL code for the UART has been verified and the simulation waveform has

been observed.

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7. FIRE DETECTION AND CONTROL SYSTEM

USING COMBINATIONAL LOGIC CIRCUITS.

AIM: To write a VHSIC/Verilog HDL code for fire detection and control system using

combinational logic circuits and verify its functionality in both Software simulator and Hardware

kit.



BLOCK DIAGRAM:

VHDL PROGRAM:

library IEEE;




entity fire is


rst : in STD_LOGIC;

sensor : in STD_LOGIC_VECTOR (5 downto 0);

alarm : out STD_LOGIC;

actuator : out STD_LOGIC;

display : out STD_LOGIC_VECTOR (7 downto 0));

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end fire;

architecture Behavioral of fire is

begin

process (clk, rst) begin


if (rst = '1') then

alarm

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SIMULATION WAVEFORM:

CONCLUSION:

Hence the VHDL code for the fire detection and control system using combinational

logic circuits has been verified and the simulation waveform has been observed

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8.TRAFFIC LIGHT CONTROLLER USING

SEQUENTIAL LOGIC CIRCUITS

AIM: To write a VHDL code for traffic light controller using sequential logic circuitsand verifyits functionality in both software simulator and hardware kit.



CIRCUIT DIAGRAM:

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VHDL PROGRAM:

library IEEE;




entity tfcontroller_code is


rst : in STD_LOGIC;

Green : out STD_LOGIC;

Red : out STD_LOGIC;

Yellow : out STD_LOGIC);

end tfcontroller_code;

architecture Behavioral of tfcontroller_code is

signal count:integer range 0 to 10 := 0;

signal state:integer range 0 to 2 := 0;

begin

process(clk, rst)

begin

if(rst = '1') then

state

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when 1 => --Green Light

if(count=5) then

count

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RESULT ANALYSIS:





CONCLUSION:

Hence the VHDL code for the traffic light controller using sequential circuits has been

verified and the simulation waveform has been observed.

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9. PATTERN DETECTION USING MOORE

MACHINE

AIM: To write a VHDL code for Pattern detection using Moore machine in both Software




CIRCUIT DIAGRAM:

TRUTH TABLE:PRESENT STATE NEXT STATE OUTPUT (det_vld)

Seq=0 Seq=1A A B 0

B C B 0

C A D 0

D C A 1

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VHDL PROGRAM:

library IEEE;




entity pattern1 is

port(clk : in std_logic; --clock signal

reset : in std_logic;--reset signa

seq : in std_logic; --serial bit sequence//

det_vld : out std_logic--A '1' indicates the pattern -

--"1011" is detected in the sequence);

end pattern1;

architecture Behavioral of pattern1 is

type state_type is (A,B,C,D);--Defines the type for states in

--the state machine//

signal state : state_type := A;--Declare the signal with the

--corresponding state type//.

begin

process(clk)

begin

if( reset = '1' ) then

det_vld

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when C => if ( seq = '0' ) then

state

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CONCLUSION:

Hence the VHDL code for the pattern detection using moore machine has been verified

and the simulation waveform has been observed.

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10. FINITE STATE MACHINE (FSM) BASED

LOGIC CIRCUIT.

AIM: To write a VHDL code for Finite state machine (FSM) based logic circuit in both Software




STATE DIAGRAM:

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TRUTH TABLE:

Present state Next state output

S0 S0 S1 0 0

S1 S2 S1 0 0

S2 S0 S3 0 0

S3 S2 S4 0 0

S4 S2 S1 0 1

VHDL PROGRAM:

library ieee ;

use ieee.std_logic_1164.all;

entity seq_design is

port(a:in std_logic;

clock:in std_logic;reset:in std_logic;

x:out std_logic);

end seq_design;

architecture FSM of seq_design is

type state_type is (S0, S1, S2, S3);

signal next_state, current_state: state_type;

begin-- cocurrent process#1: state registers

state_reg: process(clock, reset)

begin

if (reset='1') then

current_state

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elsif a ='1' then

next_state x

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RESULT ANALYSIS:





CONCLUSION:

Hence the VHDL code for the FSM based logic circuit has been verified and the

simulation waveform has been observed.

Documents

VLSI LAB-1