Emblitz VLSI Lab Guide

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FPGA-EMBEDDED LAB

Resource

Guide for VLSI-Verilog and VLSI-

VHDL Programming

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Lab Manual This document is released under Emblitz Technologies Pvt Ltd License and can be freely distributed

and copied for non-commercial uses. Kindly cite the original authors

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FPGA-Embedded Lab Manual

Lab in-Charge

Shruthi.H.S

[email protected]

Rajendra S.P

[email protected]

mailto:[email protected]

mailto:[email protected]

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Table of Contents 1.1 Introduction to FPGA ............................................................................................................... 5

1.2 Commercially available FPGAs ............................................................................................ 5

1.3 Xilinx SRAM-based FPGAs ..................................................................................................... 6

1.4 Emblitz Xilinx Spartan 3E Development Board ............................................................ 8

1.5 Emblitz FPGA Development Boards .............................................................................. 10

1.6 Working with Spartan 3E FPGA ....................................................................................... 16

1.7 Steps to perform experiment using FPGA-Verilog Simulator ............................223

1.8 Steps to perform experiments using FPGA-VHDL simulator .............................334

1.9 FPGA-Verilog simulator’s additional features ............................................................ 38

1.10 Useful resources for students .......................................................................................409

1.11 Contact Information............................................................................................................ 40

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Chapter 1

1.1 Introduction to FPGA

What is an FPGA?

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured

by the customer or designer after manufacturing—hence "field-programmable". The FPGA

configuration is generally specified using a hardware description language (HDL), similar to

that used for an application-specific integrated circuit (ASIC). FPGAs can be used to

implement any logical function that an ASIC could perform. The ability to update the

functionality after shipping, partial re-configuration of the portion of the design and the low

non-recurring engineering costs relative to an ASIC design offer advantages for many

applications.

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of

reconfigurable interconnects that allow the blocks to be "wired together". Logic blocks can be

configured to perform complex combinational functions, or merely simple logic gates like

AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be

simple flip-flops or more complete blocks of memory. As the only type of FPD that supports

very high logic capacity, FPGAs have been responsible for a major shift in the way digital

circuits are designed.

1.2 Commercially available FPGAs

There are two basic categories of FPGAs on the market today:

1. SRAM-based FPGAs and

2. antifuse-based FPGAs.

In the first category, Xilinx and Altera are the leading manufacturers in terms of number of

users, with the major competitor being AT&T. For antifuse-based products, Actel, Quicklogic

and Cypress, and Xilinx offer competing products.

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1.3 Xilinx SRAM-based FPGAs

The basic structure of Xilinx FPGAs is array-based, meaning that each chip comprises a two

dimensional array of logic blocks that can be interconnected via horizontal and vertical

routing channels. Xilinx introduced the first FPGA family, called the XC2000 series, in about

1985 and now offers more than six generations. We will focus on the most widely used and

more popular Spartan 3E family. The Spartan-3E family of Field-Programmable Gate Arrays

(FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer

electronic applications. The five-member family offers densities ranging from 100,000 to 1.6

million system gates. The xilinx SRAM based FPGA is Shown below:

XILINX SRAM based FPGA

Spartan-3E family architecture consists of five fundamental programmable functional

elements:

1. Configurable Logic Blocks (CLBs) contains 2 or more identical slices, each slice has 2

flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as

flip-flops or latches. CLBs perform a wide variety of logical functions as well as store

data.

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Configurable Logic Blocks

2. Input/Output Blocks (IOBs): IOB provides interface between the package pins and

CLBs. Each IOB can work as uni- or bi-directional I/O. Outputs can be forced into High

Impedance. Inputs and outputs can be registered advised for high-performance I/O.

Inputs can be delayed. Support a variety of signal standards, including four high-

performance differential standards. Double Data-Rate (DDR) registers are included

Different Blocks of SRAM –based FPGA

3. Block RAM: Dedicated blocks of memory (18k blocks). Use multiple blocks for larger

memories.

4. Multiplier Blocks: This block accept two 18-bit binary numbers as inputs and

calculate the product.

5. Digital Clock Manager (DCM): This Block provide self-calibrating, fully digital

solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock

signals.

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1.4 Emblitz Xilinx Spartan 3E Development Board

The Emblitz Xilinx Spartan-3E Starter Kit shown below highlights the unique features of the

Spartan-3E FPGA family and provides a convenient development board for embedded

processing applications.

Features:

Xilinx XC3S100E Spartan-3E FPGA

Up to 108 user-I/O pins

145 pin FBGA package

100k gates

72k Block RAM

15k Distributed RAM

240 CLB slice

100,000 gate Xilinx Spartan 3E FPGA

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JTAG programming port

XCF04S Xilinx Platform Flash ROM to store FPGA configurations

Large collection of I/Os including eight LEDs and four slide switches

LCD and 7 segment displays

RS 232 and VGA ports

VGA display port

On-board USB-based FPGA/CPLD download/debug interface

100 MHz clock oscillator

Ethernet port with physical layer controller

User-selectable oscillator, plus a socket for a second oscillator

100 pin user I/O and peripheral module connection

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1.5 Emblitz FPGA Development Boards

Emblitz Technologies Pvt, Ltd offers wide range of Development Kits. Some of the VLSI kits

are given below,

VLSI STARTER KIT(100E)


FPGA XILINX 250 STARTER KIT

VLSI STARTER KIT

Features:

• 100,000 gate Xilinx Spartan 3E FPGA

• JTAG programming port

• XCF04S Xilinx Platform Flash ROM to store FPGA configurations

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• Large collection of I/Os including eight LEDs and four slide switches

• LCD and 7 segment displays

• RS 232 and VGA ports

• Ethernet port with physical layer controller

• User-selectable oscillator, plus a socket for a second oscillator

• 100 pin user I/O and peripheral module connection

FPGA Features:

• 100k gates

• 108 I/OS

• 72k Block RAM

• 15k Distributed RAM

• 240 CLB slease

Contents of Kit:

• VLSI kit

• USB cable

• TAG cable

• Parallel port cable

• LCD module

• Supplied DVD containing software (Xilinx ISE), Example codes, Schematics, Connection diagram, Data Sheets, User Manual and other details to use the product.

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Kit Features:










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FPGA Features:

• 250k gates

• 108 I/OS

• 72k Block RAM


• 240 CLB slease

Contents of Kit:

• VLSI kit

• USB cable

• TAG cable


• LCD module

• Supplied DVD containing software (Xilinx ISE), Example codes, Schematics, Connection

diagram, Data Sheets, User Manual and other details to use the product.

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FPGA XILINX 250 STARTER KIT

Kit Features:










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FPGA Features:

• 250k gates

• 108 I/OS

• 72k Block RAM


• 240 CLB slease

Contents of Kit:

• VLSI kit

• USB cable

• TAG cable


• LCD module

• Supplied DVD containing software (Xilinx ISE), Example codes, Schematics, Connection

diagram, Data Sheets, User Manual and other details to use the product.

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1. 6 Working with Spartan 3E FPGA

The FPGAs are programmed using Hardware Description Languages (HDL).The characteristic

that distinguishes the HDL from other programming languages is, as the name suggests any

code written in a HDL generates the virtual hardware for that code unlike c, c++.

VHDL programming is similar to assembly level programming, which requires elaborate

programming and often prone errors. To make programming much easier and user friendly

some of the concepts of C Language were borrowed resulting in very like C language called

Verilog Hardware Description Language.

Standard Development languages available for programming FPGAs are listed below,

VHDL (Very high speed integrated circuits Hardware Description Language).

Verilog (Very like C- Logic).

Handle –C etc.

FPGA Development Cycle is as follows:

Create new project , Select either VHDL or Verilog module

Select the input , output ports

Develop the code

Synthesis the code

Simulate your FPGA design

Place, map and route the design

Generate the bit file

Download the bit file to the FPGA hardware

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Verilog Programming

Basic syntax of a standard Verilog program is:

module <module name>(input,output);

$declaration section

$Procedural Blocks

end module

Any program of the verilog starts with the module<module name> followed by input, output section. Input, output section includes the hardware inputs and outputs of the program code.

Declaration section: In verilog declaration can be of two types

1. Nets - represents structural connections between components.

2. Registers - represent variables used to store data.

Types of Nets

Register Data Types

Registers store the last value assigned to them until another assignment statement changes their value.

Registers represent data storage constructs.

You can create arrays of the regs called memories.

Register data types are used as variables in procedural blocks.

A register data type is required if a signal is assigned a value within a procedural block

Procedural blocks begin with keyword initial and always.

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Procedural Blocks Verilog behavioral code is inside procedures blocks, but there is a exception, some behavioral code also exist outside procedures blocks. There are two types of procedural blocks in Verilog

initial : initial blocks execute only once at time zero (start execution at time zero).

always : always blocks loop to execute over and over again, in other words as name means, it executes always.

Examples:-

INITIAL Block ALWAYS Block

If a procedure block contains more then one statement, those statements must be enclosed within

Sequential begin - end block

Parallel fork - join block

Hello world program using Verilog

//-----------------------------------------------------------

// This is my first Verilog Program

// Design Name : hello_world

// File Name : hello_world.v

// Function : This program will print "hello world”

// Try this program using FPGA-Verilog simulator and get the

// output as “Hello World” in output window.

//-----------------------------------------------------------

Initial begin clk = 0;

reset = 0; enable = 0; data = 0;

end

always@(posedge clk) begin : D_FF

if (reset == 1)

q <= 0;

else

q <=d;

end

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//-----------------------------------------------------------

module hello_world;

initial begin

$display ("Hello World");

$finish;

end endmodule // End of Module hello_world

//-----------------------------------------------------------

VHDL Programming

VHDL programming consists of the following concepts,

Libraries:

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_signed.all;

Use ieee.std_logic_unsigned.all;

Data Types:

bit values: '0', '1'

boolean values: TRUE, FALSE

integer values: -(231) to +(231 - 1)

std_logic values: 'U','X','1','0','Z','W','H','L','-'

U' = uninitialized

'X' = unknown

'W' = weak 'X‘

'Z' = floating

'H'/'L' = weak '1'/'0‘

'-' = don't care

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Entity:

Define inputs and outputs

Example:

Entity test is

Port( A,B,C,D: in std_logic;

E: out std_logic);

End test

Entity

Architecture: Schematic of which shown :

Define functionality of the chip

X <= A AND B;

Y <= C AND D;

E <= X OR Y;

Architecture

Signal: All internal variables

Signal X,Y : std_logic;

Signal

Inputs and Outputs

Chip

A

B

C

D

E

ChipA

B

C

D

EX

Y

Chip

Signal

A

B

C

D

EX

Y

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VHDL Feature:

Case insensitive - inputa, INPUTA and InputA are refer to same variable

Comments

‘--’ until end of line

If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line

Statements are terminated by ‘;’

Signal assignment: ‘<=’

User defined names: letters, numbers, underscores (‘_’).start with a letter

VHDL Structure:

Library - Definitions, constants

Entity - Interface

Architecture - Implementation, function

VHDL is rich in language abstractions. Abstractions are description of design in different method. The different methods are given below,

Structural Description Method: expresses the design as an arrangement of interconnected components It is basically schematic

Behavioral Description Method: describes the functional behavior of a hardware design in terms of circuits and signal responses to various stimuli The hardware behavior is described algorithmically

Data-Flow Description Method: is similar to a register-transfer language This method describes the function of a design by defining the flow of information from one input or register to another register or output

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Final Code:

//----------------------------------------------------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TEST IS

PORT (A,B,C,D : IN STD_LOGIC;

E : OUT STD_LOGIC);

END TEST;

ARCHITECTURE BEHAVIOR OF TEST IS

SIGNAL X,Y : STD_LOGIC;

BEGIN

X <= (not A) AND B;

Y <= C AND D;

E <= X OR Y;

END BEHAVIOR;

//-----------------------------------------------------------

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1. 7 Steps to perform experiment using FPGA-Verilog Simulator

The Steps executive a FPGA verilog code successfully on the Hardware using Xilinx ISE tool are as follows pictorially,

Double click on the Xilinx ISE icon on the desktop. The IDE will open as snap shown below,

1. Create new Project :File new project

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2. Project name is mentioned as xor1, and Top level source type is HDL.

3. Select Device and Design flow for the Project as given below,

Family: Spartan 3E

Device: XC3S100E

Package: TQ144

Speed:-4

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4. Select New Source

5. Select Verilog Module, Write the name of the file. Press Next.

6. The example shown here is XOR gate.

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7. Select the input output ports, 2 input XOR gate has A, B as inputs and C as output.

8. Select the respective ports by clicking on the dropdown symbol.

9. After this step, Click on NextFinish NEXTFinish. At this stage below shown window, with XOR in source window along with the device is seen.

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10. Click on XOR.V icon in source window, the code module will open, complete the code, here statement assign c= a^b; is written. Save the file in DOT V format. ex: xor.v

11. Right click on xc3s100e-5tq44, select add to source.

12. In Add to source window, select file and open.

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13. To include UCF file, in process window select Assign Package Pin under user constraints, Select Yes to add UCF file.

14. In case if unsure of the no of input and output at the beginning, there is another option to assign input , output directions to the Pin, by double click on the UCF file in source window.

15. Select the location of the inputs and outputs also as shown,

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16. Right Click on Synthesis and Select RUN

17. If Synthesis is successful, a tick in green shown beside it, if not cross mark red is seen. In this case verify that programming logic, syntax and simulation steps are correct.

18. Next step after Synthesis is to Implement design, Right click on implement Design and select RUN.

19. Implementing Design is done in 3 stages, i.e. Translate, Map, Place and Route as shown below,

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20. Right click on Generating Programming file, select RUN, IMPACT window will open give FINISH.

21. Click on initialize Chain in tool bar, as shown

22. If the hardware is detected, below shown message will be displayed, along with Xilinx processor name XS3C100E

23. Select Cancel All, if Assign new configure file window opens,

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24. Right Click on the Processor XS3C100E highlighted in green, select Assign new configuration file, select bit file of your program. Here I will be select the xor.bit file as shown,

25. Any warnings of startup clock bit stream, give OK.

26. Now, to program the Processor, right click on it and select Program

27. In programming properties window, verify, Erase block programming are ticked. Give ok. The processor will be programmed. The output will be seen on the hardware.

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28. Note that the above steps from 24 are all used to program the Processor XS3C100E, the programming can done only till this step to see output through processor.

To see output through Flash below mentioned steps should be followed.

Double click on PROM file form, select Xilinx PROM give Next, Select the PROM xcf04s -524288 ADD. Select Next and FINISH.

29. ADD device to Bit stream, select bit file of your design and open.

30. If you wish to add another device do so, else give No in Add new device window.

31. Double click on Generate file the below mentioned message will be displayed.

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32. Select Boundary Scan window, Right click on Flash, select Assign new configuration file, select file in dot mcs format. Here it will be XOR.mcs give open.

33. To program the Flash, right click on the Chip and select Program.

34. In programming properties window, all the options should be unclicked.

35. Warning related to verify gives ok Ok to proceed. The following message after successful programming is shown,

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1. 8 Steps to perform experiments using FPGA-VHDL simulator

The Steps executive a FPGA VHDL code successfully on the Hardware using Xilinx ISE tool are as follows pictorially,

Double click on the Xilinx ISE icon on the desktop. The IDE will open as snap shown below,

1. Create new Project :File new project

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2. Project name is mentioned as xor1, and Top level source type is HDL.

3. Select Device and Design flow for the Project as given below,

Family: Spartan 3E

Device: XC3S100E

Package: TQ144

Speed:-4

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4. Select New Source

5. Select VHDL Module, Write the name of the file. Press Next. The example shown here

is XOR gate.

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6. Select the input output ports, 2 input XOR gate has A, B as inputs and C as output.

7. Select the respective ports by clicking on the dropdown symbol.

8. After this step, Click on NextFinish NEXTFinish. At this stage below shown window, with XOR in source window along with the device is seen.

9. Click on XOR.V icon in source window, the code module will open, complete the code, here statement assign c= a^b; is written. Save the file in DOT VHD format. ex: xor.vhd

10. From here on, the steps to see output through XS3C100E and Flash XCF04s are same as the Steps followed in FPGA –Verilog Programming.

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1. 9 FPGA-Verilog and FPGA-VHDL simulator’s additional features

1. To see the hardware realization of the design, under Synthesis select View RTL Schematic below shown window will be seen.

2. Double click on the standard cell, the internal cell details can be obtained.

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3. Double Click on each cell to see their respective configuration

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1. 10 Useful resources for students

http://www.xilinx.com/support/documentation/application_notes/xapp463.pdf

http://www.xilinx.com/support/index.htm#nav=sd-nav-link-156334&tab=tab-sd

http://vhdlguru.blogspot.com/

http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html

http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/index.html

http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html

http://www.overmapped.com/

http://www.xilinx.com/itp/xilinx10/books/docs/sim/sim.pdf

http://www.sandstrom.org/systemde.htm

http://www.cse.scitech.ac.uk/disco/publications/FPGA_overview.pdf

http://www.cosmiac.org/pdfs/EDK_Tutorial4_sims.pdf

http://www.techdesignforums.com/eda/eda-topics/verified-rtl-to-gates/firmware-verification-using-systemverilog-ovm/

http://vlsitech.blogspot.com/2008/07/vlsi-books.html

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1. 11Contact Information

FOR QUOTATION AND FOR MORE DETAILS CONTACT:

Emblitz Technologies Pvt Ltd,

#738/33, 12th Main, 3rd Blk, Rajajinagar, Bangalore 560010 India

www.emblitz.com, [email protected] Phones: 90 80 23140344, 90 80 23146229,

Mobile: 09449104615, 09980562847

Documents

Emblitz VLSI Lab Guide