LIST OF EXPERIMENTS

1.Modeling of Sequential Digital system using VHDL. 2.Modeling of Sequential Digital system using Verilog. 3.Design and Implementation of ALU using FPGA. 4.Simulation of NMOS and CMOS circuits using SPICE. 5.Modeling of MOSFET using C. 6.Implementation of FFT, Digital Filters in DSP Processor. 7.Implementation of DSP algorithms using software package. 8.Implementation of MAC Unit using FPGA

EX.NO:1.a DATE: DESIGN OF HALF ADDERUSING VHDL AIM: To design a Half adder using VHDL. SOFTWARE REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b. Step 3: Declare output ports s, c. Step 4:Begin the process using behavioral architecture. Step 5:Assign s= a b. Step 6: Assign c=a.b. Step 7: End the process. THEORY: The half adder operation needs two binary inputs, augends and add end bits and two binary outputs are sum and carry. SUM Carry = = a a.b b

In multi-digit addition, we have to add two bytes along with the carry of the previous digit addition. Effectively such addition requires addition of three bits. This is not possible with the half adder

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ha is Port ( a,b: in STD_LOGIC; s,c: out STD_LOGIC); end ha; architecture Behavioral of ha is begins