Vlsi Lab File

7/30/2019 Vlsi Lab File

1/24

EXPERIMENT NO. 1

AIM: STUDY OF TANNER TOOLS

THEORY: Tanner Tools

Tanner EDA is a suite of tools for the design of integrated circuits. Tanner EDA is mainly used toanalyze circuits at switch level & gate level.These are tool used to enter schematics, perform SPICEsimulations, do physical design (i.e., chip layout), perform design rule checks (DRC) and layoutversus schematic (LVS) checks.

Tanner EDA Design Tools

S-edit - a schematic capture tool

T-SPICE - the SPICE simulation engine integrated with S-edit

L-edit - physical design tool

W-edit - waveform formatting

S-EDIT

S-Edit is a powerful design capture & entry tool that can generate netlists directly usable in T-Spice

simulations. It provides an integrated environment for editing circuits, setting up and runningsimulations and probing the results. It also provides the ability to perform SPICE simulations of thecircuit. These circuits that can be driven forward into a physical layout.


2/24

L-EDIT

L-edit refers to Flexible to do micromachining design, PCB layout, and other CAD work. L-Edit/DRC -it indentifies any design faults(widths, spacing, overlaps),Layout EDITor L-Edit/Extract- generates acircuit " which is used for SPICE simulation netlist "


3/24

W-EDIT

It is not just a waveform viewer but a robust analysis tool Built-in measurements like max, min,average, intersect, rms, over/undershoot, amplitude, error, crossing, delay, frequency, rise/fall time,settling time, duty cycle, slew rate, etc. It has easy measurement methods by selecting traces &

applying options.


4/24

T-SPICE

It is a complete design capture and simulation solution that provides accuracy. The role of T-Spice isto help design and verify a circuit operation. T-Spice simulation results allow circuit designers toverify and fine-tune designs before submitting them for fabrication. It performs fast, accurate

simulations for analog and mixed-signal IC designs and fully supports foundry models for reliable andaccurate simulations.


5/24

TYPES OF ANALYSIS

DC Operating Point Analysis

DC Transfer Analysis Transient Analysis AC Analysis

DC operating point analysis finds the circuit steady-state condition.

DC Transfer Analysis is used to study the voltage or current at a set of points in a circuit as afunction of the voltage or current at another set of points. This is done by sweeping the sourcevariables.

AC Analysis characterizes the circuit behaviour dependence on small signal input frequency.

Transient Analysis provides information on how circuit elements vary with time.

LATEST VERSION

Windows: Version 15.22(XP, Vista, Win 7)

Linux (RHEL): Version 15.22


6/24

EXPERIMENT NO. 2

AIM: TO DESIGN NMOS TRANSISTOR AND TO STUDY ITS I-V CHARACTERISTICS

THEORY: The metal oxide semiconductor field-effect transistor (MOSFET) is a transistor used for

amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gateelectrode can induce a conducting channel between the two other contacts called source and drain.The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figureshows the schematic diagram of the structure of an nMOS device before and after channelformation.

a): nMOSFET before channel formation Fig. (1b): nMOSFET structure after channel for

CODE: *VI Plot NMOS

M1 2 1 0 0 NMOS W=1U L=0.18U

v1 1 0 1.8v

vds 2 0 1.8v

.dc vds 0 1.8 0.02 sweep v1 0 1.8 0.3

.include "C:\Documents and Settings\student\Desktop\MODEL_0.18.md"


7/24

.print i(M1)

.probe

.end

CONCLUSION: The characteristics of an NMOS transistor can be explained as follows. Three regionsof operation:- Cut-off mode:

MOSFET: VGS < VT , VGD < VT with VDS > 0.

- Linear or Triode mode:

MOSFET: VGS > VT , VGD > VT , with VDS > 0.

- Saturation mode:

: MOSFET: VGS > VT , VGD < VT (VDS > 0).


8/24


9/24

EXPERIMENT-3

AIM: TO DESIGN PMOS TRANSISTOR AND TO STUDY ITS I-V CHARACTERISTICS

THEORY: The metal oxide semiconductor field-effect transistor (MOSFET) is a transistor used foramplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gateelectrode can induce a conducting channel between the two other contacts called source and drain.The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figureshows the schematic symbol of the structure of an pMOS device before and after channel formation.

CODE:

***PMOS**

M1 3 2 1 1 PMOS L=0.18U W=1u ps = 20 pd = 4.include "C:\Documents and Settings\Administrator\Desktop\180nm.md"vgs 2 1 DC -1.8vvds 3 1 DC -1.8v

.DC vds 0.0 -1.8v -0.2 sweep vgs 0 -1.8v -0.2

.probe

.print dc I(M1)

.end


10/24

CONCLUSION: The characteristics of a PMOS transistor can be explained as follows. Three regions of operation:

-Cut-off-mode: MOSFET: VGS VT , Id=0.

-Linear or Triode mode: MOSFET: VGS < VT , VDS > VGS-VT.

-Saturation mode: MOSFET: VGS < VT and VDS VGS -VTH


11/24


12/24

EXPERIMENT NO. 4

AIM: TO DESIGN A CMOS INVERTER AND STUDY ITS DC CHARACTERISTICS

THEORY: CMOS is also sometimes referred to as complementary-symmetry metal oxide

semiconductor . The words "complementary-symmetry" refer to the fact that the typical digitaldesign style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxidesemiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristicsof CMOS devices are high noise immunity and low static power consumption. Significant power isonly drawn while the transistors in the CMOS device are switching between on and off states.Consequently, CMOS devices do not produce as much waste heat as other forms of logic, forexample transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices.

CODE:

M1 3 1 2 2 PMOS L=0.18U W=2u ps = 20 pd = 4

M2 3 1 0 0 NMOS L=0.18U W=4U ps = 20 pd = 4

VDD 2 0 1.8V

c1 3 0 0.01nf

*V3 3 0

V1 1 0 1.8V

**.TRAN 500PS 20PS


13/24

.DC V1 0.0 1.8 0.002

.PROBE

.PRINT DC v(1) v(3)

.PRINT DC I(M2)

.PRINT DC P(VDD)

**.print dc p(c1)

.END

CONCLUSION: Here we have shown the status of both NMOS and PMOS transistor in all the regionsof the characteristics. We can also draw the characteristics, starting with the VIcharacteristics of PMOS and NMOS characteristics.


14/24


15/24

EXPERIMENT-5:

AIM: TO DESIGN CMOS INVERTER USING NMOS AS DRIVER & ENHANCEMENT NMOSTRANSISTOR AS LOAD USING SPICE &COMPARE THE DC TRANSFER CHARACTERSTICS ANDPOWER DISSIPATION LEVEL OF CMOS INVERTER USING SPICE.

THEORY: It consists of two opposite polarity MOSFETs the NMOS and the PMOS with theirgates connected together at the input; the applied voltage is denoted by An NMOS-PMOSgroup with a common gate is called a complementary pair, which gives us the C inCMOS., the complementar y pair forms the basis for CMOS logic circuits. The inverteroutput voltage is taken from the common drain terminals. The transistors are connected ina manner that ensures that only one of the MOSFETs conducts when the input is table at alow or high voltage; this is due to the use of the complementary arrangement.

CODE:

m1 2 2 3 0 nmos L=0.18U W=0.5U ps = 20 pd = 4m2 3 1 0 0 nmos L=0.18U W=0.5U ps = 20 pd = 4

VDD 2 0 1.8Vc1 3 0 0.01nf*V3 3 0V1 1 0 1.8V

.include "C:\Documents and Settings\Administrator\Desktop\180nm.md"

.DC V1 0.0 1.8 0.002

.probe

.print DC V(1) V(3)

.PRINT DC I(M2)

.PRINT DC P(VDD)

.end


16/24

CONCLUSION:

The DC characteristics of the inverter are portrayed in the voltage transfer characteristic, which is aplot of Vout as a function of Vin. This is obtained by varying the input voltage Vin in the range from 0

to VDD and finding the output voltage Vout. The VTC for the circuit is obtained by starting with aninput voltage of Vin =0v and then increasing it up to a value of Vin =VDD. This results in the plotshown in the characteristic graph.


17/24

EXPERIMENT NO-6

AIM: TO STUDY THE EFFECT ON DC TRANSFER CHARACTERISTICS OF A CMOS INVERTER BY

CHANGING THE W/L RATIO OF THE TRANSISTORS

THEORY: CMOS is also sometimes referred to as complementary-symmetry metal oxide

semiconductor . The words "complementary-symmetry" refer to the fact that the typical digitaldesign style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxidesemiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristicsof CMOS devices are high noise immunity and low static power consumption. Significant power isonly drawn while the transistors in the CMOS device are switching between on and off states.Consequently, CMOS devices do not produce as much waste heat as other forms of logic, forexample transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-

channel devices.

CODE:

M1 3 1 2 2 PMOS L=0.18U W=1u ps = 20 pd = 4

M2 3 1 0 0 NMOS L=0.18U W=0.5U ps = 20 pd = 4

VDD 2 0 1.8V

c1 3 0 0.01nf

*V3 3 0

V1 1 0 1.8V

**.TRAN 500PS 20PS.DC V1 0.0 1.8 0.002


18/24

.PROBE

.PRINT DC v(1) v(3)

.PRINT DC I(M2)

.PRINT DC P(VDD)

**.print dc p(c1)

.END

When PMOS L=0.18U W=2.5u NMOS L=0.18U W=2U


19/24

CONCLUSION: By increasing the width of pull-up transistor the dc transfer characteristics are shiftedto the right and by increasing the width of the pull down transistor characteristics are shifted to theleft.


20/24

EXPERIMENT-7

AIM: TO DESIGN NAND GATE IN CMOS TECHNOLOGY AND SIMULATE THE CHARACTERSTICS

USING SPICE.

THEORY: Nand Gate is the basic gate and it is also referred as Universal Gate. The output is lowwhenever both inputs are high and high otherwise.

In case of the NAND gates the PMOS were in parallel and the NMOS were in series. The MOSFETs actas switches. When both inputs are high, the n-MOSFETs switch on to connect the output to ground.If either input is low, the path to ground is cut off, and one of the p-MOSFETs switches on to connectthe output to +5V. The schematic diagram is shown below:

CODE:

***nand Gate***

mn1 4 2 1 1 pmos w=5u l=0.18umn2 4 3 1 1 pmos w=5u l=0.18umn3 4 2 5 0 nmos w=5u l=0.18umn4 5 3 0 0 nmos w=5u l=0.18u

C1 4 0 0.1pVdd 1 0 dc 5vva 2 0 PULSE (5 0 0 1n 1n 10n 20n)


21/24

vb 3 0 PULSE (5 0 0 1n 1n 15n 30n).include "C:\Documents and Settings\Administrator\Desktop\180nm.md".tran 0.1ns 40ns.probe.power vdd.print tran v(2) v(3)

.print tran v(4)**.print p(Va).end

CONCLUSION: The I-V characteristics are also obtained for the four different modes . Transient characteristics of the NAND gate has been successfully verified.


22/24

EXPERIMENT-8

AIM: TO DESIGN NOR GATE IN CMOS TECHNOLOGY AND SIMULATE THE CHARACTERSTICSUSING SPICE.

THEORY: Nor Gate is the basic gate and it is also referred as Universal Gate.

A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1),a LOW output (0) results. NOR is the result of the negation of the OR operator.

In case of the NOR gates the PMOS are in series and the NMOS in parallel. PMOS will be switched onwhen Vout is connected to Vcc. PMOS will be switched off when Vout is not connected to Vcc. Theschematic diagram is shown below:


23/24

CODE:

***nor Gate***

mn1 1 2 5 1 pmos w=5u l=0.18umn2 5 3 4 1 pmos w=5u l=0.18umn3 4 2 0 0 nmos w=5u l=0.18umn4 4 3 0 0 nmos w=5u l=0.18u

C1 4 0 0.1pVdd 1 0 dc 5vva 2 0 PULSE (5 0 0 1n 1n 10n 20n)vb 3 0 PULSE (5 0 0 1n 1n 14n 30n)

.include "C:\Documents and Settings\Administrator\Desktop\180nm.md"

.tran 0.1ns 40ns

.probe

.power vdd

.print tran v(2) v(3)

.print tran v(4)**.print p(Va).end


24/24

CONCLUSION: Transient characteristics of the NOR gate has been successfully verified.