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Experiment No: 1

Aim: To study the MOSFET characteristics with varying VGS for both pmos and nmos.

Software Required: Design Architect IC by mentor graphics

Theory: P-type metal-oxide-semiconductor logic uses p-type metal-oxide-semiconductor field effect

transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors have four 

modes of operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity

saturation.

The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate outputand positive supply voltage, while a resistor is placed between the logic gate output and the negative

supply voltage. The circuit is designed such that if the desired output is high, then the PUN will be active,

creating a current path between the positive supply and the output.

While PMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so

the whole circuit can be made with PMOS FETs), it has several shortcomings as well. The worst problem

is that a DC current flows through a PMOS logic gate when the PUN is active, that is whenever the output

is high. This leads to static power dissipation even when the circuit sits idle.

N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effecttransistors (MOSFETs) to implement logic gates and other digital circuits. NMOS transistors

have four modes of operation: cut-off (or sub-threshold), triode, saturation (sometimes called

active), and velocity saturation.

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic

gate output and negative supply voltage, while a resistor is placed between the logic gate output

and the positive supply voltage. The circuit is designed such that if the desired output is low,

then the PDN will be active, creating a current path between the negative supply and the output.

Circuit Diagram:-

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output:

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Experiment No: 2

Aim: To study the Transient analysis of CMOS inverter with varying W and L.

Software Required: Design Architect IC by mentor graphics

Theory: CMOS (complementary metal-oxide semiconductor) is the semiconductor technology

used in the transistors that are manufactured into most of today's computer microchips.

Semiconductors are made of silicon and germanium, materials which "sort of" conduct

electricity, but not enthusiastically. Areas of these materials that are "doped" by adding

impurities become full-scale conductors of either extra electrons with a negative charge (N-type

transistors) or of positive charge carriers (P-type transistors). In CMOS technology, both kinds of 

transistors are used in a complementary way to form a current gate that forms an effective meansof electrical control. CMOS transistors use almost no power when not needed. As the current

direction changes more rapidly, however, the transistors become hot. This characteristic tends to

limit the speed at which microprocessors can operate. CMOS (complementary metal-oxide

semiconductor) is the semiconductor technology used in the transistors that are manufactured

into most of today's computer microchips. Semiconductors are made of silicon and germanium,

materials which "sort of" conduct electricity, but not enthusiastically. Areas of these materials

that are "doped" by adding impurities become full-scale conductors of either extra electrons with

a negative charge (N-type transistors) or of positive charge carriers (P-type transistors). In

CMOS technology, both kinds of transistors are used in a complementary way to form a current

gate that forms an effective means of electrical control. CMOS transistors use almost no power 

when not needed. As the current direction changes more rapidly, however, the transistors become

hot. This characteristic tends to limit the speed at which microprocessors can operate.

 

Circuit Diagram:-

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Wave output :-

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Experiment No: 3(a)

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Aim: To study the transient analysis of  NOR gate.

Software Required: Design Architect IC by Mentor Graphics

Theory:  The NOR gate is a digital logic gate that implements logical NOR - it behaves

according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate

are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR is the result of 

the negation of the OR operator. NOR is a functionally complete operation—combinations of 

 NOR gates can be combined to generate any other logical function. By contrast, the OR operator 

is monotonic as it can only change LOW to HIGH but not vice versa.

In most, but not all, circuit implementations, the negation comes for free— 

including CMOS and TTL. In such logic families, the only way to implement OR is with 2 or more gates, such as a NOR followed by an inverter. A significant exception is some forms of 

the domino logic family.

Symbol and Truth Table :

Circuit Diagram:-

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Output :-

 

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Experiment No. 3(b)

Aim: To study the transient analysis of NAND gate

Software used: DESIGNER IC by mentor graphics

THEORY:

 NAND gates are one of the two basic logic gates (the other being NOR logic) from which any

other logic gates can be built. Due to this property, NAND and NOR gates are sometimes called

"universal gates". However, modern integrated circuits are not constructed exclusively from a

single type of gate. Instead, EDA tools are used to convert the description of a logical circuit to

a netlist of complex gates (standard cells) or transistors (full custom approach).

Symbol and Truth Table:

Circuit Diagram:

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Output:

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Experiment No. 4(a)

AIM: To study the transient analysis of XOR gate

Software used: DESIGNER IC by mentor graphics

THEORY:

The XOR gate (sometimes EOR gate or EXOR gate) is a digital logic gate that implements

an exclusive disjunction; that is, it behaves according to the truth table . A true output (1) results

if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) and both are

true (1), a false output (0) results. A way to remember XOR is "one or the other but not both". It

represents the inequality function, i.e., the output is HIGH (1) if the inputs are not alike

otherwise the output is LOW (0).

Symbol and Truth Table :

Circuit Diagram :

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Output :

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Experiment No. 4(b)11

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Aim: To study the transient analysis of XNOR gate

Software used: DESIGNER IC by mentor graphics

THEORY:

The XNOR gate (sometimes spelled "exnor" or "enor") is a digital logic gate whose function is

the inverse of the exclusive OR (XOR ) gate. The two-input version implements logical equality, 

 behaving according to the truth table. A HIGH output (1) results if both of the inputs to the gate

are the same. If one but not both inputs are HIGH (1), a LOW output (0) results

Symbol and Truth Table :

Circuit Diagram :

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Output :

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Experiment No: 5

Aim: To study the transient analysis of D-type latch

Software Required: Design Architect IC by mentor graphics

Theory: This latch exploits the fact that in the two active input combinations (01 and 10) of a

gated SR latch R is the complement of S. The input NAND stage converts the two D input states

(0 and 1) to these two input combinations for the next SR latch by inverting the data input signal.

The low state of the enable signal produces the inactive "11" combination. Thus a gated D-latch

may be considered as a one-input synchronous SR latch. This configuration prevents from

applying the restricted combination to the inputs. It is also known as transparent latch, data latch,

or simply gated latch. It has a data input and an enable signal (sometimes named clock,

or control). The word transparent comes from the fact that, when the enable input is on, the

signal propagates directly through the circuit, from the input D to the output Q.

Circuit Diagram:

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Output:

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Experiment No: 6(a)

Aim: To study the transient analysis of a 2*1 mux using PTL analysis

Software Required: Design Architect IC by mentor graphics

Theory:  In electronics, pass transistor logic (PTL) describes several logic families used in the

design of integrated circuits. It reduces the count of transistors used to make different logic gates,

 by eliminating redundant transistors.

A typical CMOS design for the 2*1 multiplexer is shown in Fig .1 for a 2*1 MUX. A MUX

selects one form a set of logic inputs to connect with the output.

Fig .1- 2*1 Mux using PTL analysis

Circuit Diagram:

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Output:

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Output:

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