VLSI Design Lab New

7/31/2019 VLSI Design Lab New

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AL-Falah School of Engineering & Technology (An Autonomous Institute)

A L - F a l a h S c h o o l o f E n g i n e e r i n g & T e c h n o l o g y Page 1

VLSI Design Lab

M.Tech VLSI Design

Department of Electronics & Communication EngineeringAL-Falah School of Engineering & Technology

Dhauj Faridabad Haryana India


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L-T-P Int Ext Total0-0-3 50 100 150

Code: MEVLSI-511Paper: VLSI Design Lab

List of experiments using Tanner Tools

1. Design the layout for PMOS in layout editor.

2. Design the layout for NMOS in layout editor.

3. Design the layout for CMOS inverter with equal rise and fall time in layout editor.

4. Design the layout for 2-lnput AND 3-lnput NOR gate in layout editor.

5. Design the layout for 2-lnput and 3-lnput NAND gate in layout editor.

6. Design the layout for 2-lnput and 3-lnput Ex-OR gate in layout editor.

7. Design the layout for 2-lnput and 3-lnput Ex-NOR gate in layout editor.

8. Design the layout for clocked S-R flip-flop in layout editor.

Note: The Scheme of awarding the grades to a student in the course will be supplied by theUniversity to the examiner. Teachers are allowed to perform other experiments relevant to the lab.


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INDEX

S.No. TITLE Page No.

1. Integrated Circuit Layout 4

2. Integrated Circuit Design 5

3. Tanner IC Work Flow 10

7. L-EDIT 12

8. LVS (Layout Vs Schematic) 27

9. Layout Examples 29

(a) Nand Gate 29

(b) Nor Gate 30

(c) Transmission Gate 32

(d) Xor Gate using TX gate 33

(e) Xnor Gate 35

(f) 4*1 Multiplexer 37

(g) Full Adder 39

(h) Parallel Adder 42


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Integrated Circuit Layout

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousandsoftransistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and

communication technologies were being developed. The microprocessor is a VLSI device. The term is nolonger as common as it once was, as chips have increased in complexity into the hundreds of millions oftransistors.

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation ofan integrated circuit in terms of planar geometric shapes which correspond to the patterns ofmetal, oxide, orsemiconductor layers that make up the components of the integrated circuit.When using a standard process - where the interaction of the many chemical, thermal, and photographicvariables are known and carefully controlled - the behavior of the final integrated circuit depends largely onthe positions and interconnections of the geometric shapes. A layout engineer's job is to place and connectall the components that make up a chip so that they meet all criteria. Typical goals are performance, size,and manufacturability.

The layout must pass a series of checks in a process known as verification. The two most common checks inthe verification process are Design Rule Checking (DRC), and Layout Versus Schematic (LVS). When allverification is complete the data is translated into an industry standard format, typically GDSII, and sent to asemiconductor foundry. The process of sending this data to the foundry is called tapeout due to the fact thedata used to be shipped out on a magnetic tape. The foundry converts the data into another format and usesit to generate the photomasks used in a photolithographic process ofsemiconductor device fabrication.

In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, much likethe early days ofPCB design. Modern IC Layout is done with the aid ofIC layout editor software, or evenautomatically using EDA tools, including place and route tools or schematic driven layout tools. Themanual operation of choosing and positioning the geometric shapes is informally known as "polygonpushing".
http://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Communicationhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Geometric_shapehttp://en.wikipedia.org/wiki/Metalhttp://en.wikipedia.org/wiki/Silicon_oxidehttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Manufacturabilityhttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Layout_versus_schematichttp://en.wikipedia.org/wiki/GDSIIhttp://en.wikipedia.org/wiki/Tapeouthttp://en.wikipedia.org/wiki/Photomaskhttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Fabrication_(semiconductor)http://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/IC_layout_editorhttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Schematic_driven_layouthttp://en.wikipedia.org/wiki/Polygonhttp://en.wikipedia.org/wiki/Polygonhttp://en.wikipedia.org/wiki/Schematic_driven_layouthttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/IC_layout_editorhttp://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/Fabrication_(semiconductor)http://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Photomaskhttp://en.wikipedia.org/wiki/Tapeouthttp://en.wikipedia.org/wiki/GDSIIhttp://en.wikipedia.org/wiki/Layout_versus_schematichttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Manufacturabilityhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Silicon_oxidehttp://en.wikipedia.org/wiki/Metalhttp://en.wikipedia.org/wiki/Geometric_shapehttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Communicationhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Integrated_circuit


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Integrated circuit design

Integrated circuit design, or IC design, is a subset ofelectrical engineering, encompassing the particularlogic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturizedelectronic components built into an electrical network on a monolithic semiconductor substrate by

photolithography.

IC design can be divided into the broad categories ofdigital and analog IC design. Digital IC design is usedto produce components such as microprocessors, FPGAs, memories (RAM, ROM, and flash) and digitalASICs. Digital design focuses on logical correctness, maximizing circuit density, and placing circuits sothat clock and timing signals are routed efficiently. Analog IC design also has specializations in power ICdesign and RF IC design. Analog IC design is used in the design ofop-amps, linear regulators, phase lockedloops, oscillators and active filters. Analog design is more concerned with the physics of the semiconductordevices such as gain, matching, power dissipation, and resistance. Fidelity of analog signal amplificationand filtering is usually critical and as a result, analog ICs use larger area active devices than digital designsand are usually less dense in circuitry.

Modern ICs are enormously complicated. A large chip, as of 2006, may well have more transistors thanthere are people on Earth. The rules for what can and cannot be manufactured are also extremely complex.An IC process as of 2006 may well have more than 600 rules. Furthermore, since the manufacturing processitself is not completely predictable, designers must account for its statistical nature. The complexity ofmodern IC design, as well as market pressure to produce designs rapidly, has led to the extensive use ofautomated design tools in the IC design process. In short, the design of an IC using EDA software is thedesign, test, and verification of the instructions that the IC is to carry out.

Fundamentals

Integrated circuit design involves the creation of electronic components, such as transistors, resistors,capacitors and the metallic interconnect of these components onto a piece of semiconductor, typicallysilicon. A method to isolate the individual components formed in the substrate is necessary since thesubstrate silicon is conductive and often forms an active region of the individual components. The twocommon methods are p-n junction isolation and dielectric isolation. Attention must be given to powerdissipation of transistors and interconnect resistances and current density of the interconnect, contacts andvias since ICs contain very tiny devices compared to discrete components, where such concerns are less ofan issue. Electromigration in metallic interconnect and ESD damage to the tiny components are also ofconcern. Finally, the physical layout of certain circuit subblocks is typically critical, in order to achieve thedesired speed of operation, to segregate noisy portions of an IC from quiet portions, to balance the effects ofheat generation across the IC, or to facilitate the placement of connections to circuitry outside the IC.

Design steps

A typical IC design cycle involves several steps:

1. Feasibility study and die size estimate2. Functional verification3. Circuit/RTL design4. Circuit/RTL simulation Logic simulation
http://en.wikipedia.org/wiki/Electrical_engineeringhttp://en.wikipedia.org/wiki/Boolean_logichttp://en.wikipedia.org/wiki/Circuit_designhttp://en.wikipedia.org/wiki/Integrated_circuitshttp://en.wikipedia.org/wiki/Electronic_componenthttp://en.wikipedia.org/wiki/Electrical_networkhttp://en.wikipedia.org/wiki/Monolithichttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Digitalhttp://en.wikipedia.org/wiki/Analog_electronicshttp://en.wikipedia.org/wiki/Microprocessorshttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/RAMhttp://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/ASIChttp://en.wikipedia.org/wiki/Radio_frequencyhttp://en.wikipedia.org/wiki/Op-amphttp://en.wikipedia.org/wiki/Linear_regulatorhttp://en.wikipedia.org/wiki/Phase_locked_loophttp://en.wikipedia.org/wiki/Phase_locked_loophttp://en.wikipedia.org/wiki/Oscillatorhttp://en.wikipedia.org/wiki/Active_filterhttp://en.wikipedia.org/wiki/Design_ruleshttp://en.wikipedia.org/wiki/Statisticshttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Transistorshttp://en.wikipedia.org/wiki/Resistorshttp://en.wikipedia.org/wiki/Capacitorshttp://en.wikipedia.org/wiki/Interconnecthttp://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Wafer_(electronics)http://en.wikipedia.org/wiki/P-n_junction_isolationhttp://en.wikipedia.org/w/index.php?title=Dielectric_isolation&action=edit&redlink=1http://en.wikipedia.org/wiki/Interconnecthttp://en.wikipedia.org/wiki/Contactshttp://en.wikipedia.org/wiki/Viashttp://en.wikipedia.org/wiki/Electromigrationhttp://en.wikipedia.org/wiki/Electrostatic_dischargehttp://en.wikipedia.org/wiki/Functional_verificationhttp://en.wikipedia.org/wiki/SPICEhttp://en.wikipedia.org/wiki/Logic_simulationhttp://en.wikipedia.org/wiki/Logic_simulationhttp://en.wikipedia.org/wiki/SPICEhttp://en.wikipedia.org/wiki/Functional_verificationhttp://en.wikipedia.org/wiki/Electrostatic_dischargehttp://en.wikipedia.org/wiki/Electromigrationhttp://en.wikipedia.org/wiki/Viashttp://en.wikipedia.org/wiki/Contactshttp://en.wikipedia.org/wiki/Interconnecthttp://en.wikipedia.org/w/index.php?title=Dielectric_isolation&action=edit&redlink=1http://en.wikipedia.org/wiki/P-n_junction_isolationhttp://en.wikipedia.org/wiki/Wafer_(electronics)http://en.wikipedia.org/wiki/Siliconhttp://en.wikipedia.org/wiki/Interconnecthttp://en.wikipedia.org/wiki/Capacitorshttp://en.wikipedia.org/wiki/Resistorshttp://en.wikipedia.org/wiki/Transistorshttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Statisticshttp://en.wikipedia.org/wiki/Design_ruleshttp://en.wikipedia.org/wiki/Active_filterhttp://en.wikipedia.org/wiki/Oscillatorhttp://en.wikipedia.org/wiki/Phase_locked_loophttp://en.wikipedia.org/wiki/Phase_locked_loophttp://en.wikipedia.org/wiki/Linear_regulatorhttp://en.wikipedia.org/wiki/Op-amphttp://en.wikipedia.org/wiki/Radio_frequencyhttp://en.wikipedia.org/wiki/ASIChttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/RAMhttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/Microprocessorshttp://en.wikipedia.org/wiki/Analog_electronicshttp://en.wikipedia.org/wiki/Digitalhttp://en.wikipedia.org/wiki/Photolithographyhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Monolithichttp://en.wikipedia.org/wiki/Electrical_networkhttp://en.wikipedia.org/wiki/Electronic_componenthttp://en.wikipedia.org/wiki/Integrated_circuitshttp://en.wikipedia.org/wiki/Circuit_designhttp://en.wikipedia.org/wiki/Boolean_logichttp://en.wikipedia.org/wiki/Electrical_engineering


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5. Floorplanning6. Design review7. Layout8. Layout verification9. Static timing analysis10.Layout review11.Design For Test and Automatic test pattern generation

12.Design for manufacturability (IC)13.Mask data preparation14.Wafer fabrication15.Die test16.Packaging17.Post silicon validation18.Device characterization19.Tweak (if necessary)20.Datasheet generation Portable Document Format21.Ramp up22.Production

23.Yield Analysis / Warranty Analysis Reliability (semiconductor)24.Failure analysis on any returns25.plan for next generation chip using production information if possible

Digital design

Roughly speaking, digital IC design can be divided into three parts

ESL design: This step creates the user functional specification. The user may use a variety oflanguages and tools to create this description. Examples include a C/C++ model, SystemC,SystemVerilog Transaction Level Models.

RTL design: This step converts the user specification (what the user wants the chip to do) into aregister transfer level (RTL) description. The RTL describes the exact behavior of the digital circuitson the chip, as well as the interconnections to inputs and outputs.

Physical design: This step takes the RTL, and a library of available logic gates, and creates a chipdesign. This involves figuring out which gates to use, defining places for them, and wiring themtogether.

Note that the second step, RTL design, is responsible for the chip doing the right thing. The third step,physical design, does not affect the functionality at all (if done correctly) but determines how fast the chipoperates and how much it costs.

RTL design

This is the hardest part, and the domain of functional verification. The spec may have some tersedescription, such as encodes in the MP3formator implements IEEE floating-point arithmetic. Each of theseinnocent looking statements expands to hundreds of pages of text, and thousands of lines of computer code.It is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the usermay throw at it. Many techniques are used, none of them perfect but all of them useful extensive logicsimulation, formal methods, hardware emulation, lint-like code checking, and so on.
http://en.wikipedia.org/wiki/Integrated_circuit_layouthttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Design_For_Testhttp://en.wikipedia.org/wiki/Design_For_Testhttp://en.wikipedia.org/wiki/Automatic_test_pattern_generationhttp://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Mask_data_preparationhttp://en.wikipedia.org/wiki/Mask_data_preparationhttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Semiconductor_fabrication#Wafer_test_and_device_testhttp://en.wikipedia.org/wiki/Semiconductor_fabrication#Wafer_test_and_device_testhttp://en.wikipedia.org/wiki/Integrated_circuit_packaginghttp://en.wikipedia.org/wiki/Integrated_circuit_packaginghttp://en.wikipedia.org/wiki/Post_silicon_validationhttp://en.wikipedia.org/wiki/Post_silicon_validationhttp://en.wikipedia.org/wiki/Portable_Document_Formathttp://en.wikipedia.org/wiki/Reliability_(semiconductor)http://en.wikipedia.org/wiki/Failure_analysishttp://en.wikipedia.org/wiki/Failure_analysishttp://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/C%2B%2Bhttp://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/SystemVeriloghttp://en.wikipedia.org/wiki/Transaction-level_modelinghttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Functional_verificationhttp://en.wikipedia.org/wiki/MP3http://en.wikipedia.org/wiki/IEEE_floating-point_arithmetichttp://en.wikipedia.org/wiki/IEEE_floating-point_arithmetichttp://en.wikipedia.org/wiki/Logic_simulationhttp://en.wikipedia.org/wiki/Logic_simulationhttp://en.wikipedia.org/wiki/Formal_methodshttp://en.wikipedia.org/wiki/Hardware_emulationhttp://en.wikipedia.org/wiki/Lint_programming_toolhttp://en.wikipedia.org/wiki/Lint_programming_toolhttp://en.wikipedia.org/wiki/Hardware_emulationhttp://en.wikipedia.org/wiki/Formal_methodshttp://en.wikipedia.org/wiki/Logic_simulationhttp://en.wikipedia.org/wiki/Logic_simulationhttp://en.wikipedia.org/wiki/IEEE_floating-point_arithmetichttp://en.wikipedia.org/wiki/MP3http://en.wikipedia.org/wiki/Functional_verificationhttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/Transaction-level_modelinghttp://en.wikipedia.org/wiki/SystemVeriloghttp://en.wikipedia.org/wiki/SystemChttp://en.wikipedia.org/wiki/C%2B%2Bhttp://en.wikipedia.org/wiki/C_(programming_language)http://en.wikipedia.org/wiki/Failure_analysishttp://en.wikipedia.org/wiki/Reliability_(semiconductor)http://en.wikipedia.org/wiki/Portable_Document_Formathttp://en.wikipedia.org/wiki/Post_silicon_validationhttp://en.wikipedia.org/wiki/Integrated_circuit_packaginghttp://en.wikipedia.org/wiki/Semiconductor_fabrication#Wafer_test_and_device_testhttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Mask_data_preparationhttp://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Automatic_test_pattern_generationhttp://en.wikipedia.org/wiki/Design_For_Testhttp://en.wikipedia.org/wiki/Static_timing_analysishttp://en.wikipedia.org/wiki/Integrated_circuit_layout


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A tiny error here can make the whole chip useless, or worse. The famous Pentium FDIV bug caused theresults of a division to be wrong by at most 61 parts per million, in cases that occurred very infrequently. Noone even noticed it until the chip had been in production for months. Yet Intel was forced to offer to replace,for free, every chip sold until they could fix the bug, at a cost of $475 million (US).

Physical design

Here are the main steps of physical design. In practice there is not a straightforward progression -considerable iteration is required to ensure all objectives are met simultaneously. This is a difficult problemin its own right, called design closure.

Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pinsare assigned and large objects (arrays, cores, etc.) are placed.

Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip. Placement: The gates in the netlist are assigned to nonoverlapping locations on the die area. Logic/placement refinement: Iterative logical and placement transformations to close performance

and power constraints. Clock insertion: Balanced buffered clock trees are introduced into the design. Routing: The wires that connect the gates in the netlist are added. Postwiring optimization: Remaining performance (Timing Closure), noise (Signal Integrity), and

yield (Design for Manufacturability) violations are removed. Design for manufacturability: The design is modified, where possible, to make it as easy and

efficient as possible to produce. This is achieved by adding extra vias or adding dummymetal/diffusion/poly layers wherever possible while complying to the design rules set by thefoundry.

Final checking: Since errors are expensive, time consuming and hard to spot, extensive errorchecking is the rule, making sure the mapping to logic was done correctly, and checking that themanufacturing rules were followed faithfully.

Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.
http://en.wikipedia.org/wiki/Pentium_FDIV_bughttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Design_closurehttp://en.wikipedia.org/wiki/Floorplanninghttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Placement_(EDA)http://en.wikipedia.org/wiki/Clock_Distribution_Networkshttp://en.wikipedia.org/wiki/Routing_(EDA)http://en.wikipedia.org/wiki/Timing_Closurehttp://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Formal_equivalence_checkinghttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Tape-outhttp://en.wikipedia.org/wiki/Photomaskhttp://en.wikipedia.org/wiki/Mask_data_preparationhttp://en.wikipedia.org/wiki/Mask_data_preparationhttp://en.wikipedia.org/wiki/Photomaskhttp://en.wikipedia.org/wiki/Tape-outhttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Design_rule_checkinghttp://en.wikipedia.org/wiki/Formal_equivalence_checkinghttp://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Timing_Closurehttp://en.wikipedia.org/wiki/Routing_(EDA)http://en.wikipedia.org/wiki/Clock_Distribution_Networkshttp://en.wikipedia.org/wiki/Placement_(EDA)http://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Floorplanninghttp://en.wikipedia.org/wiki/Design_closurehttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Pentium_FDIV_bug


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Process corners

Process corners provide digital designers the ability to simulate the circuit while accounting for variations inthe technology process.

A simple CMOS Operational Amplifier Layout

Analog design

Before the advent of the microprocessor and software based design tools, analog ICs were designed usinghand calculations. These ICs were basic circuits, op-amps are one example, usually involving no more thanten transistors and few connections. An iterative trial-and-error process and "overengineering" of devicesize was often necessary to achieve a manufacturable IC. Reuse of proven designs allowed progressivelymore complicated ICs to be built upon prior knowledge. When inexpensive computer processing becameavailable in the 1970s, computer programs were written to simulate circuit designs with greater accuracythan practical by hand calculation. The first circuit simulator for analog ICs was called SPICE (SimulationProgram with Integrated Circuits Emphasis). Computerized circuit simulation tools enable greater IC designcomplexity than hand calculations can achieve, making the design of analog ASICs practical. Thecomputerized circuit simulators also enable mistakes to be found early in the design cycle before a physical

device is fabricated. Additionally, a computerized circuit simulator can implement more sophisticateddevice models and circuit analysis too tedious for hand calculations, permitting Monte Carlo analysis andprocess sensitivity analysis to be practical. The effects of parameters such as temperature variation, dopingconcentration variation and statistical process variations can be simulated easily to determine if an IC designis manufacturable. Overall, computerized circuit simulation enables a higher degree of confidence that thecircuit will work as expected upon manufacture.
http://en.wikipedia.org/wiki/Process_cornershttp://en.wikipedia.org/wiki/Op-amphttp://en.wikipedia.org/wiki/SPICEhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Monte_Carlo_analysishttp://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/File:Vlsiopamp2.gifhttp://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Design_for_manufacturability_(IC)http://en.wikipedia.org/wiki/Monte_Carlo_analysishttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/SPICEhttp://en.wikipedia.org/wiki/Op-amphttp://en.wikipedia.org/wiki/Process_corners


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Coping with variability

A challenge most critical to analog IC design involves the variability of the individual devices built on thesemiconductor chip. Unlike board-level circuit design which permits the designer to select devices that haveeach been tested and binned according to value, the device values on an IC can vary widely which areuncontrollable by the designer. For example, some IC resistors can vary 20% and of an integrated BJT

can vary from 20 to 100. To add to the design challenge, device properties often vary between eachprocessed semiconductor wafer. Device properties can even vary significantly across each individual IC dueto doping gradients. The underlying cause of this variability is that many semiconductor devices are highlysensitive to uncontrollable random variances in the process. Slight changes to the amount of diffusion time,uneven doping levels, etc. can have large effects on device properties.The design techniques necessary to reduce the effects of the device variation are:

Using the ratios of resistors, which do match closely, rather than absolute resistor value. Using devices with matched geometrical shapes so they have matched variations. Making devices large so that statistical variations becomes an insignificant fraction of the overall

device property. Segmenting large devices, such as resistors, into parts and interweaving them to cancel variations. Using common centroid device layout to cancel variations in devices which must match closely

(such as the transistor differential pair of an op amp).

Fortunately for IC design, the absolute values of the devices are less critical than the identical matching ofdevice performance. However, this fabrication variability forces certain design techniques and prevents theuse of other design techniques familiar to the board-level designer.
http://en.wikipedia.org/wiki/Binhttp://en.wikipedia.org/wiki/Bipolar_junction_transistorhttp://en.wikipedia.org/wiki/Gradientshttp://en.wikipedia.org/w/index.php?title=Common_centroid&action=edit&redlink=1http://en.wikipedia.org/wiki/Op_amphttp://en.wikipedia.org/wiki/Op_amphttp://en.wikipedia.org/w/index.php?title=Common_centroid&action=edit&redlink=1http://en.wikipedia.org/wiki/Gradientshttp://en.wikipedia.org/wiki/Bipolar_junction_transistorhttp://en.wikipedia.org/wiki/Bin


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Tanner IC Work Flow

Tanner Tools are fully-integrated solutions consisting of tools for schematic entry, circuit simulation,waveform probing, full-custom layout editing, placement and routing, netlist extraction, LVS and designrule checking (DRC) verification.
http://www.tanner.com/EDA/images/screens/scrn_Designflow_lg.jpg


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Introduction

This document gives a rough overview of how to design & simulate things with Tanner Tools. There arefour basic steps:

1. Design the schematic in S-EDIT.2. Simulate the schematic to make sure it behaves as you expect using T-SPICE.3. Layout the schematic in L-EDIT.4. Perform an LVS (Layout VS Schematic) to make sure your layout is functionally the same as the

schematic you designed in S-EDIT.5. Simulate the layout using T-SPICE with a high-level spice model, making sure L-EDIT generates

the parasitic capacitances so they are included in the simulation.

What follows is a brief overview of the steps.


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L-EDITCMOS Inverter Structure: -

Double click on L-Edit;File -> new


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Now copy TDB (Tanner Data Base) file from browsePath for TDB FileC:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit andLVS\Tech\Mosis\morbn20.tdbAnd Click OK

Goto cell -> new


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Name the cell->

Grids spacing can be minimized or maximized usingor + signTo change the technology Goto setup-> Design


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Select Lambda or microns accordingly and click okBefore designing layout we need to remember following equationsN Diffusion = N select and Active (1)

P Diffusion = P select and Active - (2)

From layer palette, we can select layer then for drawing layer we need to switch at Drawing boxes asfollows

Now we can start layout designingWe are Taking Example of CMOS Layout designBackground of L-Edit is P-Substrate by default

We need to design PMOS, First draw active


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Now draw P select over Active with keeping in mind Lambda based design rules

Now draw poly over it accordingly

Now draw metal1 to design Contact


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Now draw Active Contact for Active region

We have designed source, gate and drainNow we need to put this in N-Well

We can perform DRC (Design Rule Check) at every stage


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If we are violating any Design rule then it will be shown in Error verification navigator

On pointing any error, it will be shown in corresponding layout, as follows

It is called lens, now we need to edit N-well

We can check DRC at every stage


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Now we need to draw Body terminal, Gate contact

After designing Body terminal (n select+ active+metal1+active contact), we need to design Gate contact

In case of Poly Layer, we need to draw Poly contact

To define port, go to (A)


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Type the name of port;


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Similarly we can design N MOS; and after connecting these two, CMOS layout will look like as follows


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Now we can extract netlist by doing some settings


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Now select Extract standard rule set, and click on pencil

Now we need to include Extract file, and Spice output file at desired locationLocation for .ext file isC:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit andLVS\Tech\Mosis\morbn20.ext


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Define location for output files

In output, select Names (writing nodes)

Click ok, now go to extract button


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Click on extract, An spice file will open as follows

We can open this spice file in T-Spice and can perform desired analysisWe need to include hp05.md file for analysis


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We need to insert some spice commands to perform transient analysis :

VVoltageSource_1 Vdd Gnd DC 5VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n).PRINT TRAN V(vin).PRINT TRAN V(vout).tran 1ns 500ns

After saving spice file, we can simulate it, W-Edit will invoked and we can check the response:


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LVS(Layout Vs Schematic)

We got two output files (one from S-Edit and second from L-Edit), Now we can compare results by usingLVS

Double click on LVS, and file -> new &Select file type-> LVS setup, then ok


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We need to browse spice netlist files for layout netlist and Schematic netlist

After including these files, we need to run verification as follows &Results can be checked from Verification Window.

Both netlists are equal.


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LAYOUT EXAMPLES:

1. NAND gate:

NAND gate layout

Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"M1 1 a vdd 7 PMOS L=1u W=2.75uM2 vdd b 1 7 PMOS L=1u W=2.75uM3 5 a gnd 4 NMOS L=1u W=2.75uM4 1 b 5 4 NMOS L=1u W=2.75uvdd vdd gnd 5Va a gnd PULSE (0 5 0 100n 300n 3u 6u)Vb b gnd PULSE (0 5 0 100n 300n 6u 12u)

.tran .1u 100u

.print tran v(1) v(a) v(b)

.END


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Waveform:

2. NOR Gate:


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Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"

M1 outputa a gnd 7 NMOS L=1u W=2.75uM2 gnd b outputa 7 NMOS L=1u W=2.75uM3 5 a vdd 4 PMOS L=1u W=2.75uM4 outputa b 5 4 PMOS L=1u W=2.75uvdd vdd gnd 5Va a gnd PULSE (0 5 0 100n 300n 3u 6u)Vb b gnd PULSE (0 5 0 100n 300n 6u 12u).tran .1u 100u.print tran v(outputa) v(a) v(b).END

Waveform:


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3. TRANSMISSION GATE:

Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"

M1 out a in 4 PMOS L=1u W=2.5uM2 out a in 3 NMOS L=1u W=2.5u

vdd vdd gnd 5vVin in gnd PULSE (0 5 0 1u 1u 4u 10u)Va a gnd PULSE (0 5 0 1u 1u 4u 10u).tran .1u 40u.print in out

.END

Waveform:


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4. XOR GATE USING TX GATES

Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"M1 outputa bbar inta 10 PMOS L=1u W=2.75uM2 outputa b a 8 PMOS L=1u W=2.75uM3 inta a vdd 7 PMOS L=1u W=2.5uM4 outputa bbar a 6 NMOS L=1u W=3uM5 outputa b inta 6 NMOS L=1u W=3u

M6 inta a 4 6 NMOS L=1u W=3uvdd vdd gnd 5vVa a gnd PULSE (0 5 0 1u 1u 4u 10u)Vb b gnd PULSE (0 5 0 1u 1u 4u 10u)Vbbar bbar gnd PULSE (5 5 0 1u 1u 4u 10u).tran .1u 40u.print a bbar outputa

.END


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Waveform:


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5. XNOR GATE

Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"M1 out b 3 10 PMOS L=1u W=2.75uM2 3 a vdd 9 PMOS L=1u W=2.5uM3 out bbar a 7 PMOS L=1u W=2.75uM4 out b a 6 NMOS L=1u W=3uM5 3 a gnd 6 NMOS L=1u W=3uM6 out bbar 3 6 NMOS L=1u W=3uvdd vdd gnd 5Va a gnd PULSE (0 5 0 1u 1u 4u 10u)Vb b gnd PULSE (0 5 0 1u 1u 4u 10u)Vbbar bbar gnd PULSE (5 5 0 1u 1u 4u 10u).tran .1u 40u.print a bbar out.END


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6. 4X1 MUX

Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"M1 out s2 16 9 PMOS L=1u W=5uM2 16 s1 B 7 PMOS L=1u W=5uM3 out s2bar 1 5 PMOS L=1u W=5uM4 1 s1bar A 3 PMOS L=1u W=5uM5 out s2 1 23 NMOS L=1u W=5uM6 1 s1 A 23 NMOS L=1u W=5uM7 out s2 11 31 PMOS L=1u W=5uM8 11 s1bar D 29 PMOS L=1u W=5uM9 out s2bar 14 27 PMOS L=1u W=5uM10 14 s1 C 25 PMOS L=1u W=5uM11 out s2bar 11 23 NMOS L=1u W=5uM12 11 s1 D 23 NMOS L=1u W=5uM13 out s2 14 23 NMOS L=1u W=5uM14 14 s1bar C 23 NMOS L=1u W=5uM15 out s2bar 16 23 NMOS L=1u W=5uM16 16 s1bar B 23 NMOS L=1u W=5uVa a gnd PULSE (0 5 0 0 0 2u 4u)Vb b gnd PULSE (0 5 0 0 0 4u 8u)Vc c gnd PULSE (0 5 0 0 0 8u 16u)


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Vd d gnd PULSE (0 5 0 0 0 16u 32u)Vs1 s1 gnd PULSE (0 5 0 0 0 16u 32u)Vs1bar s1bar gnd PULSE (0 5 16u 0 0 16u 32u)Vs2bar s2bar gnd PULSE (0 5 32u 0 0 32u 64u)Vs2 s2 gnd PULSE (0 5 0 0 0 32u 64u).tran .1u 200u

.print v(s1) v(s2) v(out)

.END

Waveform


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7. FULL ADDER


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Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"M1 vdd c 6 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM2 17 c vdd 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5u

M3 6 b 5 20 PMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM4 vdd b 17 20 PMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM5 5 a 2 20 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM6 S0 2 vdd 20 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM7 2 12 17 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM8 gnd c 4 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM9 14 c gnd 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5uM10 4 b 3 16 NMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM11 gnd b 14 16 NMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM12 3 a 2 16 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM13 S0 2 gnd 16 NMOS L=1u W=3u AD=12.75p PD=14.5u AS=7.5p PS=8u

M14 2 12 14 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM15 12 c 13 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM16 vdd b 19 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM17 13 b vdd 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM18 17 a vdd 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM19 19 a 12 20 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM20 vdd a 13 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM21 vdd 12 carry 20 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14uM22 12 c 11 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM23 gnd b 15 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM24 11 b gnd 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u

M25 14 a gnd 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM26 15 a 12 16 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM27 gnd a 11 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM28 gnd 12 carry 16 NMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14uvdd vdd gnd 5v.tran 1m 100mva a gnd 0vvb b gnd 5vvc c gnd 5v.print tran v(a) v(s0) v(carry).end


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Waveform


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8. Four Bit Parallel Adder

Spice File:

.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Toolsv13.0\hp05.md"M1 vdd c 6 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM2 6 b0 5 22 PMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM3 5 a0 2 22 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM4 s0 2 vdd 22 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM5 2 16 10 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM6 gnd c 4 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM7 4 b0 3 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM8 3 a0 2 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM9 s0 2 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8u

M10 2 16 8 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM11 vdd c 10 22 PMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM12 16 c 11 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM13 vdd b0 10 22 PMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM14 vdd b0 14 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM15 11 b0 vdd 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM16 10 a0 vdd 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM17 14 a0 16 22 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM18 vdd a0 11 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM19 gnd c 8 69 NMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM20 16 c 9 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u

M21 gnd b0 8 69 NMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM22 gnd b0 12 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM23 9 b0 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM24 8 a0 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM25 12 a0 16 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM26 gnd a0 9 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM27 vdd c0 23 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM28 28 c0 vdd 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5uM29 vdd 16 c0 22 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u


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M30 23 b1 21 35 PMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM31 21 a1 17 35 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM32 s1 17 vdd 35 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM33 17 27 28 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM34 gnd c0 20 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM35 25 c0 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5u

M36 gnd 16 c0 69 NMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14uM37 20 b1 19 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM38 19 a1 17 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM39 s1 17 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM40 17 27 25 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM41 27 c0 29 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM42 vdd b1 28 35 PMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM43 vdd b1 32 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM44 29 b1 vdd 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM45 28 a1 vdd 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM46 32 a1 27 35 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8u

M47 vdd a1 29 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM48 vdd 27 c1 35 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14uM49 27 c0 26 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM50 gnd b1 25 69 NMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM51 gnd b1 30 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM52 26 b1 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM53 25 a1 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM54 30 a1 27 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM55 gnd a1 26 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM56 gnd 27 c1 69 NMOS L=1u W=3u AD=13.5p PD=15u AS=12p PS=14uM57 vdd c1 40 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4u

M58 45 c1 vdd 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5uM59 40 b2 39 54 PMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM60 39 a2 34 54 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM61 s2 34 vdd 54 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM62 34 44 45 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM63 gnd c1 38 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM64 42 c1 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5uM65 38 b2 37 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM66 37 a2 34 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM67 s2 34 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM68 34 44 42 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u

M69 44 c1 46 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM70 vdd b2 45 54 PMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM71 vdd b2 50 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM72 46 b2 vdd 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM73 45 a2 vdd 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM74 50 a2 44 54 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM75 vdd a2 46 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM76 vdd 44 c2 54 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14uM77 44 c1 43 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8u


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M78 gnd b2 42 69 NMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM79 gnd b2 47 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM80 43 b2 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM81 42 a2 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM82 47 a2 44 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM83 gnd a2 43 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u

M84 gnd 44 c2 69 NMOS L=1u W=3u AD=15p PD=16u AS=12p PS=14uM85 vdd c2 60 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM86 64 c2 vdd 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5uM87 60 b3 59 72 PMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4uM88 vdd b3 64 72 PMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM89 59 a3 53 72 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM90 s3 53 vdd 72 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM91 53 63 64 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM92 gnd c2 58 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM93 61 c2 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=8.25p PS=8.5uM94 58 b3 57 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=1.5p PS=4u

M95 gnd b3 61 69 NMOS L=1u W=3u AD=8.25p PD=8.5u AS=7.5p PS=8uM96 57 a3 53 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM97 s3 53 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8uM98 53 63 61 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM99 63 c2 65 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM100 vdd b3 71 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM101 65 b3 vdd 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM102 64 a3 vdd 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM103 71 a3 63 72 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM104 vdd a3 65 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM105 vdd 63 c3 72 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u

M106 63 c2 62 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM107 gnd b3 68 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=4uM108 62 b3 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM109 61 a3 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=8uM110 68 a3 63 69 NMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PS=8uM111 gnd a3 62 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14uM112 gnd 63 c3 69 NMOS L=1u W=3u AD=13.5p PD=15u AS=12p PS=14uvdd vdd gnd 5v.tran 1m 100mva0 a0 gnd 0vvb0 b0 gnd 5v

vc c gnd 5vva1 a1 gnd 5vvb1 b1 gnd 0vva2 a2 gnd 0vvb2 b2 gnd 5vva3 a3 gnd 5vvb3 b3 gnd 0v.print tran v(s0) v(s1) v(s2) v(s3) v(c3).end


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Waveform: