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DESCRIPTION

• rakesh asery

TYPICAL DESIGN FLOW

A typical design flow for designing VLSI IC circuits is shown in figure. Unshaded blocks show the level of design representation, shaded blocks show process of design flow.

• rakesh asery

Experiment No:- Aim: - To Design Half Adder using Verilog and simulate the same using Xilinx ISE Simulator.

TOOLS REQUIRED: - PC, Xilinx ISE.

THEORY: -

The half-adder adds two inputs bits and generates a carry and sum, which are the two outputs of half-adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry. The truth table for the half adder is:-

S=AxorB

C=AandB

VERILOG CODE

GATE LEVEL:-

reg A,B;

wire C,S;

ha_h(A,B,C,S);

initial

begin

A=1'b0;

B=1'b1;

• rakesh asery

#10 b=1'b0;

#10 \$finish;

end

endmodule

DATA FLOW:-

input A,B,S,C;

assign S=A^B;

assign C=A&B;

endmodule

BEHAVIORAL:-

input a,b;

output sum, carry;

reg sum,carry;

always@(a,b)

case({a,b})

2'b00:begin sum = 1'b0;carry = 1'b0;end

2'b01:begin sum=1'b1;carry=1'b0;end

2'b10:begin sum=1'b1;carry=1'b0;end

2'b11:begin sum=1'b0;carry=1'b1;end

endcase

endmodule

• rakesh asery

SCHEMATIC DIAGRAM: -

• rakesh asery

TIMING INPUT : -

SIMULATION RESULTS: -

RESULT: - Half Adder is designed using Verilog module and simulated the same using Xilinx ISE Simulator

• rakesh asery

Experiment No:-Aim: - To Design Multiplexer 4x1 using Verilog and simulate the same using Xilinx ISE Simulator

TOOLS REQUIRED: - PC, Xilinx ISE.

THEORY: -

Multiplexer means many into one. Multiplexer is a combinational circuit used to multiplex several signals into a single one. We can multiplex signals in power of 2. Ex: 4X1 MUX can be used to multiplex 4 different signals and produce 1 common output using select lines.

Figure shows 4X1 MUX. Its output equation can be written as:-

O = I0S0S1+ I1S0S1+ I2S0S1+ I3S0S1

• rakesh asery

VERILOG CODE

GATE LEVEL:-

module RAKESHMUX4X1(i0, i1, i2, i3, s0, s1, out);

input i0,i1,i2,i3,s0,s1;

output out;

wire y0,y1,y2,y3;

wire s1n,s0n;

not(s1n,s1);

not(s0n,s0);

and(y0,i0,s1n,s0n);

and(y1,i1,s1n,s0);

and(y2,i2,s1,s0n);

and(y3,i3,s1,s0);

or(out,y0,y1,y2,y3);

endmodule

DATA FLOW:-

module RAKSHKMUX(out,i0,i1,i2,i3,s0,s1);output out;input i0,i1,i2,i3,s0,s1; assign out=(~s1&~s0&i0); assign out=(~s1&s0&i1);assign out=(s1&~s0&i2);assign out=(s1&s0&i3); endmodule

• rakesh asery

BEHAVIOURAL:-

module RAKSHKMUXR4x1(out, i0, i2, i3, i1, s0, s1);

output out;

input i0,i1,i2,i3,s0,s1;

reg out;

always@(i0 or i1 or i2 or i3 or s0 or s1)

case({s1,s0})

2'b00: out=i0;

2'b01: out=i1;

2'b10: out=i2;

2'b11: out=i3;

endcase

endmodule

SCHEMATIC DIAGRAM: -

• rakesh asery

• rakesh asery

TIMING INPUT: -

SIMULATION RESULTS: -

RESULT: Multiplexer 4x1 is designed using Verilog module and simulated the same using Xilinx ISE Simulator.

• rakesh asery

Experiment No:- Aim: - To Design Full Adder using Verilog and simulate the same using Xilinx ISE Simulator.

TOOLS REQUIRED: - PC, Xilinx ISE.

THEORY: -

The full-adder adds three inputs bits and generates a carry and sum, which are the two outputs of full adder. The input variables of a full adder are called the augend and addend bits. The output variables are the sum and carry. The truth table for the full adder is:-

S=AxorBxorC

CA=(AandB)or(BandC)or(CandA)

VERILOG CODE

GATE LEVEL:-

output sum,carry;

input a,b,c;

wire w,x,y,z;

xor(w,a,b);

xor(sum,w,c);

and(x,a,b);

• rakesh asery

and(y,a,c);

and(z,b,c);

or(carry,x,y,z);

endmodule

DATA FLOW: -

module RAKSHKFULLADDER(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

assign sum = a ^ b ^ c;

assign carry = (a&b) | (b&c) | (c&a);

endmodule

BEHAVIOURAL: - module fullbev(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

reg sum,carry;

always@(a or b or c)

case({a,b,c})

3'b000:begin sum=0;carry=0;end

• rakesh asery

3'b001:begin sum=1;carry=0;end

3'b010:begin sum=1;carry=0;end

3'b011:begin sum=0;carry=1;end

3'b100:begin sum=1;carry=0;end

3'b101:begin sum=0;carry=1;end

3'b110:begin sum=0;carry=1;end

3'b111:begin sum=1;carry=1;end

endcase

endmodule

SCHEMATIC DIAGRAM: -

• rakesh asery

TIMING INPUT : -

SIMULATION RESULTS: -

RESULT: - Multiplexer Full Adder is designed using Verilog module and simulated the same using Xilinx ISE Simulator.

• rakesh asery

Experiment No:-[4a] Aim: - To Design D Flip-flop using Verilog and simulate the same using Xilinx ISE Simulator.

TOOLS REQUIRED: - PC, Xilinx ISE.

THEORY: -

It is also known as a "data" or "delay" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

If clock=1 then Output Q=D.

VERILOG CODE

BEHAVIOURAL: - module RAKSHKDFF(Q, CLK, D);

output Q,CLK,D;

reg Q;

initial Q=0;

always@(CLK or D)

if(CLK)

• rakesh asery

begin

if(D)

Q

• rakesh asery

TIMING INPUT : -

SIMULATION RESULTS: -

RESULT: - Multiplexer D Flip-flop is designed using Verilog module and simulated the same using Xilinx ISE Simulator.

• rakesh asery

Experiment No:-[4b]Aim: - To Design JK Flip-flop using Verilog and simulate the same using Xilinx ISE Simulator.

TOOLS REQUIRED: - PC, Xilinx ISE.

THEORY: -

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop

The characteristic equation of the JK flip-flop is:

Qnext=J&Q+K&Q.

VERILOG CODE

BEHAVIOURAL: - module RAKSHKJKFF(CLK,J, K, Q, Qnot);

input CLK,J,K,Q,Qnot;

reg Q,Qnot;

initial Q=0;

initial Qnot=1;

always @ (posedge CLK)

• rakesh asery

case({J,K})

2'b 00:begin Q=Q; Qnot=Qnot; end

2'b 01:begin Q=0; Qnot=1; end

2'b 10:begin Q=1; Qnot=0; end

2'b 11:begin Q=~; Qnot=~Qnot; end

endcase

endmodule

SCHEMATIC DIAGRAM: -

• rakesh asery

TIMING INPUT : -

SIMULATION RESULTS: -

RESULT: - Multiplexer JK Flip-flop is designed using Verilog module and simulated the same using Xilinx ISE Simulator.

• rakesh asery

Experiment No:-Aim: - To Design Counter using Verilog and simulate the same using Xilinx ISE Simulator.TOOLS REQUIRED: - PC, Xilinx ISE.

THEORY: -

Counters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.

In electronics counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:

Asynchronous (ripple) counter changing state bits are used as clocks to subsequent state flip-flops Synchronous counter all state bits change under control of a single clockDecade counter counts through ten states per stage Up/down counter counts both up and down, under command of a control inputRing counter formed by a shift register with feedback connection in a ring Johnson counter a twisted ring counterCascaded countermodulus counter.

ASYNCHRONOUS (RIPPLE) COUNTER:-

• rakesh asery

This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from 0000 until it reaches an output 1001 (decimal 9). Both outputs QA and QD are now equal to logic 1 and the output from the NAND gate changes state from logic 1 to a logic 0 level and whose output is also connected to the CLEAR ( CLR ) inputs of all the J-K Flip-flops. This signal causes all of the Q outputs to be reset back to binary 0000 on the count of 10. Once QAand QD are both equal to logic 0 the output of the NAND gate returns back to a logic level 1 and the counter restarts again from 0000. We now have a decade or Modulo-10 counter.

BINARY SYNCHRONOUS COUNTER:-

Binary 4-bit Synchronous Up Counter

To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next stat

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