EE5780 Advanced VLSI CAD - Michigan Technological pages.mtu.edu/~zhuofeng/EE5780Fall2013_files/Lecture_08...8.2 Z. Feng MTU EE5780 Advanced VLSI CAD Introduction Chips are mostly made

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  • Z. Feng MTU EE5780 Advanced VLSI CAD8.1

    EE5780 Advanced VLSI CAD

    Lecture 8 Interconnect Modeling and AnalysisZhuo Feng

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.2

    Introduction Chips are mostly made of wires called interconnect

    In stick diagram, wires set size Transistors are little things under the wires Many layers of wires

    Wires are as important as transistors Speed Power Noise

    Alternating layers run orthogonally

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.3

    Wire Geometry Pitch = w + s Aspect ratio: AR = t/w

    Old processes had AR

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.4

    Layer Stack AMI 0.6 m process has 3 metal layers Modern processes use 6-10+ metal layers Example:

    Intel 180 nm process

    M1: thin, narrow (< 3) High density cells

    M2-M4: thicker For longer wires

    M5-M6: thickest For VDD, GND, clk

    Layer T (nm) W (nm) S (nm) AR

    6 1720 860 860 2.0

    1000

    5 1600 800 800 2.0

    1000

    4 1080 540 540 2.0

    7003 700 320 320 2.2

    7002 700 320 320 2.2

    7001 480 250 250 1.9

    800

    Substrate

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.5

    Wire Resistance = resistivity (*m)

    R = sheet resistance (/) is a dimensionless unit(!)

    Count number of squares R = R * (# of squares)

    l

    w

    t

    1 Rectangular BlockR = R (L/W)

    4 Rectangular BlocksR = R (2L/2W) = R (L/W)

    t

    l

    w w

    l

    l lR Rt w w

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.6

    Choice of Metals Until 180 nm generation, most wires were aluminum Modern processes often use copper

    Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier

    Metal Bulk resistivity (*cm)Silver (Ag) 1.6Copper (Cu) 1.7Gold (Au) 2.2Aluminum (Al) 2.8Tungsten (W) 5.3Molybdenum (Mo) 5.3

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.7

    Sheet Resistance Typical sheet resistances in 180 nm process

    Layer Sheet Resistance (/)Diffusion (silicided) 3-10Diffusion (no silicide) 50-200Polysilicon (silicided) 3-10Polysilicon (no silicide) 50-400Metal1 0.08Metal2 0.05Metal3 0.05Metal4 0.03Metal5 0.02Metal6 0.02

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.8

    Contacts Resistance Contacts and vias also have 2-20 Use many contacts for lower R

    Many small contacts for current crowding around periphery

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.9

    Wire Capacitance Wire has capacitance per unit length

    To neighbors To layers above and below

    Ctotal = Ctop + Cbot + 2Cadj

    layer n+1

    layer n

    layer n-1

    Cadj

    Ctop

    Cbot

    ws

    t

    h1

    h2

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.10

    Capacitance Trends Parallel plate equation: C = A/d

    Wires are not parallel plates, but obey trends Increasing area (W, t) increases capacitance Increasing distance (s, h) decreases capacitance

    Dielectric constant = k0

    0 = 8.85 x 10-14 F/cm k = 3.9 for SiO2 Processes are starting to use low-k dielectrics

    k 3 (or less) as dielectrics use air pockets

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.11

    M2 Capacitance Data Typical wires have ~ 0.2 fF/m

    Compare to 2 fF/m for gate capacitance

    0

    50

    100

    150

    200

    250

    300

    350

    400

    0 500 1000 1500 2000

    Cto

    tal (

    aF/

    m)

    w (nm)

    Isolated

    M1, M3 planes

    s = 320s = 480s = 640s= 8

    s = 320s = 480s = 640

    s= 8

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.12

    Diffusion & Polysilicon Diffusion capacitance is very high (about 2 fF/m)

    Comparable to gate capacitance Diffusion also has high resistance Avoid using diffusion runners for wires!

    Polysilicon has lower C but high R Use for transistor gates Occasionally for very short wires between gates

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.13

    Lumped Element Models Wires are a distributed system

    Approximate with lumped element models

    3-segment -model is accurate to 3% in simulation

    L-model needs 100 segments for same accuracy! Use single segment -model for Elmore delay

    C

    R

    C/N

    R/N

    C/N

    R/N

    C/N

    R/N

    C/N

    R/N

    R

    C

    L-model

    R

    C/2 C/2

    R/2 R/2

    C

    N segments

    -model T-model

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.14

    Crosstalk A capacitor does not like to change its voltage

    instantaneously. A wire has high capacitance to its neighbor.

    When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too.

    Called capacitive coupling or crosstalk.

    Crosstalk effects Noise on nonswitching wires Increased delay on switching wires

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.15

    Crosstalk Delay Assume layers above and below on average are quiet

    Second terminal of capacitor can be ignored Model as Cgnd = Ctop + Cbot

    Effective Cadj depends on behavior of neighbors Miller effect

    A BCadjCgnd Cgnd

    B V Ceff(A) MCFConstantSwitching with ASwitching opposite A

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.16

    Crosstalk Delay Assume layers above and below on average are quiet

    Second terminal of capacitor can be ignored Model as Cgnd = Ctop + Cbot

    Effective Cadj depends on behavior of neighbors Miller effect

    A BCadjCgnd Cgnd

    B V Ceff(A) MCFConstant VDD Cgnd + Cadj 1Switching with A 0 Cgnd 0Switching opposite A 2VDD Cgnd + 2 Cadj 2

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.17

    Crosstalk Noise Crosstalk causes noise on nonswitching wires If victim is floating:

    model as capacitive voltage divider

    Cadj

    Cgnd-v

    Aggressor

    Victim

    Vaggressor

    Vvictim

    adjvictim aggressor

    gnd v adj

    CV V

    C C

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.18

    Driven Victims Usually victim is driven by a gate that fights noise

    Noise depends on relative resistances Victim driver is in linear region, agg. in saturation If sizes are same, Raggressor = 2-4 x Rvictim

    11

    adjvictim aggressor

    gnd v adj

    CV V

    C C k

    aggressor gnd a adjaggressor

    victim victim gnd v adj

    R C Ck

    R C C

    Cadj

    Cgnd-v

    Aggressor

    Victim

    Vaggressor

    Vvictim

    Raggressor

    Rvictim

    Cgnd-a

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.19

    Coupling Waveforms

    Aggressor

    Victim (undriven): 50%

    Victim (half size driver): 16%

    Victim (equal size driver): 8%Victim (double size driver): 4%

    t (ps)0 200 400 600 800 1000 1200 1400 1800 2000

    0

    0.3

    0.6

    0.9

    1.2

    1.5

    1.8

    Simulated coupling for Cadj = Cvictim

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.20

    Noise Implications So what if we have noise? If the noise is less than the noise margin, nothing

    happens Static CMOS logic will eventually settle to correct

    output even if disturbed by large noise spikes But glitches cause extra delay Also cause extra power from false transitions

    Dynamic logic never recovers from glitches Memories and other sensitive circuits also can

    produce the wrong answer

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.21

    Wire Engineering Goal: achieve delay, area, power goals with

    acceptable noise Degrees of freedom:

    Width Spacing Layer Shielding

    Del

    ay (n

    s): R

    C/2

    Wire Spacing(nm)

    Cou

    plin

    g: 2C

    adj /

    (2C

    adj+C

    gnd)

    00.20.40.6

    0.81.01.21.4

    1.61.82.0

    0 500 1000 1500 20000

    0.1

    0.2

    0.3

    0.4

    0.5

    0.6

    0.7

    0.8

    0 500 1000 1500 2000

    320480640

    Pitch (nm)Pitch (nm)

    vdd a0 a1gnd a2vdd b0 a1 a2 b2vdd a0 a1 gnd a2 a3 vdd gnd a0 b1

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.22

    Steady state responsewill be of same frequencybut different mag & phase

    t910cos3 910 810x5f

    100

    F121020

    RCj

    jH

    1

    1

    AC Analysis of Interconnect Circuits

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.23

    H 1

    1 2

    2+--------------------------=

    105 106 107 108 109 1010 10110

    0.333

    0.667

    1

    H atan=

    105 106 107 108 109 1010 1011-2

    -1

    0

    radians/sec

    radians/sec

    Focusing on the steady state solution we can analyze the mag and phase responses

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.24

    Formulate nodal equations:

    Given a particular value, solve for

    )()()( jIjVjY n

    Translate complex voltage into magnitude and phase

    )( jVn

    Problems with Cs as

    Bigger problem for L as

    0

    LjZL LjYL

    1

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.25

    Nodal analysis does not like infinite conductance

    General solution is to treat L like a voltage sourceand use auxiliary equations for inductor currents

    LjZL LjYL

    1

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.26

    Sometimes analog designers prefer poles / zerosinstead of a freq. domain mag. and phase plots

    We start by formulating the equations using sinstead of j

    )()()( suBsxGsxsC

  • Z. Feng MTU EE5780 Advanced VLSI CAD8.27

    Consider a linear interconnect ckt example

    We can stamp these eqns. into the form

    )()()( sBusxGsxsC

    inV

    1G 2G

    5G

    3G

    6G

    4G

    1sC 2sC 3sC 4sC

    6sC

    CsC5sC

    3218