Lecture1 Vlsi Cad introduction

9/23/2010

1

Introduction to Computer Aided Design

Physical Design Automation

256a1

Physical Design Automation

Malgorzata Marek‐Sadowska

256 A

Goals of the course

• Introduce fundamental concepts and algorithms used in CAD layout of ICs and IC‐based systems

• Provide a broad and state of the art context for electronic design automation

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• Identify promising new areas and problems for research

Administrative details

• Instructor: Malgorzata Marek‐Sadowska

– 4111 Howard Frank Hall

– [email protected]

– 893‐2721

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– Office hours: Tuesday 4‐5pm or by appointment.

• Grading:

– Homeworks : 20%

– Final project : 70%

– Project presentation: 10%

Moore’s Law (1965)

The number of transistors that can be integrated on single chip would double about every two years

Dual Core Itanium with 1.7B transistors

256a 4Courtesy, Intel ®

Technology scaling road map (ITRS)

YearYear 20042004 20062006 20082008 20102010 20122012Feature size (nm)Feature size (nm) 9090 6565 4545 3232 2222Integration (BT)Integration (BT) 22 44 66 1616 3232

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• Fun facts about 45nm transistors

– 30 million can fit on the head of a pin

– You could fit more than 2,000 across the width of a human hair

– If car prices had fallen at the same rate as the price of a single transistor has since 1968, a new car today would cost about 1 cent

Courtesy: M.J.Irwin, PSU

Technology scaling road map

YearYear 20042004 20062006 20082008 20102010 20122012Feature size (nm)Feature size (nm) 9090 6565 4545 3232 2222Integration (BT)Integration (BT) 22 44 66 1616 3232Delay = CV/IDelay = CV/I 0 70 7 0 70 7 >0 7>0 7 Delay Scaling will

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• More fun facts about 45nm transistors– It can switch on and off about 300 billion times a second

– A beam of light travels less than a tenth of an inch during the time it takes a 45nm transistor to switch on and off

Delay = CV/I Delay = CV/I ScalingScaling

0.70.7 ~0.7~0.7 >0.7>0.7 Delay Scaling will slow down


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Technology scaling road map

YearYear 20042004 20062006 20082008 20102010 20122012Feature size (nm)Feature size (nm) 9090 6565 4545 3232 2222

Intg. Capacity (BT)Intg. Capacity (BT) 22 44 66 1616 3232

Delay = CV/IDelay = CV/I 0 70 7 0 70 7 >0 7>0 7 Delay ScalingDelay Scaling

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• A 60% decrease in feature size increases the heat flux (W/cm2) by six times


0.70.7 ~0.7~0.7 >0.7>0.7 Delay Scaling Delay Scaling will slow downwill slow down

Energy/Logic Op Energy/Logic Op ScalingScaling

~0.35~0.35 ~0.5~0.5 >0.5>0.5 Energy Scaling will slow down


Technology Scaling Road Map

YearYear 20042004 20062006 20082008 20102010 20122012

Feature size (nm)Feature size (nm) 9090 6565 4545 3232 2222

Intg. Capacity (BT)Intg. Capacity (BT) 22 44 66 1616 3232

Delay = CV/IDelay = CV/I 0 70 7 0 70 7 >0 7>0 7 Delay ScalingDelay Scaling

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0.70.7 ~0.7~0.7 >0.7>0.7 Delay Scaling Delay Scaling will slow downwill slow down

Energy/Logic Op Energy/Logic Op ScalingScaling

>0.35>0.35 >0.5>0.5 >0.5>0.5 Energy Scaling Energy Scaling will slow downwill slow down

Process VariabilityProcess Variability Medium High Very High

• Transistors in a 90nm part have 30% variation in frequency, 20x variation in leakage


VLSI Chip Power Density

1000

10000

W/cm

2)

Nuclear

Rocket

Nozzle

Sun’s

Surface

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4004

8008

8080

8085

8086

286386

486Pentium®

P6

1

10

100

1970 1980 1990 2000 2010

Year

Power Density (W

Hot Plate

Reactor

Source: Intel

Scaling

• Wire delay trends:

» wire pitch must continue to shrink because smaller transistors must be connected.

• Time-distance trends:

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Time distance trends:

» rule of thumb: RC=internal gate delay for optimal signal speed delay => buffering scheme and signal drive region.

» if gate delay decreases, the signal drive distance will decrease faster-than-linear.

Consequences

• IC chip will be a set of isolated islands of logic

• It is impossible to build super-highways to improve this delay

• Commonly used architectural elements like

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Commonly used architectural elements like register files and crossbar switches that increase size nonlinearly with complexity will not scale well on more advanced processes with slower wires and faster clocks.

A generic multi‐core platform

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

General and General and special purpose special purpose cores (PEs)cores (PEs)

PEs likely to have PEs likely to have the same ISAthe same ISA

NIC

R

NIC

R

NIC

R

NIC

R

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PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

PEMemory

the same ISAthe same ISA

Interconnect Interconnect fabricfabric

Network on Network on Chip (NoC)Chip (NoC)

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

NIC

R

Courtesy: M.J. Irwin (PSU)

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Rapid Increase in Manufacturing Cost

$50

Process (um) 2.0 … 0.8 0.6 0.35 0.25 0.18 0.13 0.10

Single Mask t ($K)

1.5 1.5 2.5 4.5 7.5 12 40 60 40

60

$2.0

$2.5

sk S

et (

$M)

$40

$60

k ($

K)

256a 13Source: EETimes

cost ($K)

# of Masks 12 12 12 16 20 26 30 34

Mask Set cost ($K)

18 18 30 72 150 312 1,000 2,0007.5

12

40

$0.0

$0.5

$1.0

$1.5

250nm 180nm 130nm 100nm

Tot

al C

ost

for

Mas

0

$10

$20

$30

$40

Cos

t/M

ask

The Cost of Next Generation Product

Wireless chip case

Networking chip case

20

30

40

50

Total Product Cost ($M) $30M ~ $50M @ 90nm

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0.18um 0.13um 90nm

10

0.15

Engineering Cost – 60% up

Manufacturing Cost – 40% up

NRE/Mask Cost – 100% up

ProductCost

Respin cost – 78% up

Source: Altera Corporation

The Process of Design

Design

Initial concept: what is the function performed by the design?

Implementation

Design

Debug

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Initial concept: what is the function performed by the design?Constraints: Timing? Area? Cost?Map abstract functional blocks into circuit realizations

Implementation

Assemble primitives into more complex building blocksComposition via wiringChoice among alternatives

DebugFaulty systems: design, composition, component, modeling flawsDesign to make debugging easierTesting, diagnosing, and troubleshooting

Simplified model of design• Behavior

– Functions the system must implement; with constraints such as time, area, power, etc.

– Implementation‐independent description.

• Register– Components and their interconnections.

– Standard components ROM ASIC PLD

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– Standard components, ROM, ASIC,PLD.

– Timing constraints for components.

• Gate– Low‐level components and nets in terms of ASIC library

• Mask – Physical layout of IC board.

Circuit Specification

Logic Optimization

Design flow

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Logic Optimization

Technology Mapping

Placement and Routing

Functional Specification

Architectural and functional design

Schematic diagram

Functional verification

Design of sub circuits

Assembling sub circuitsdesign

Input

Logic synthesis

Logic and circuit simulation

Symbolic design, compaction

Placement, routing, compaction

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Layout

Layout verification

Mask data processing

Fab data

Physical

Design rule checking, circuitextraction, electrical rule checking

Fracturing, over and under sizing

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Physical Design

• Mapping logic to physical implementation– Implementation

• Selecting components– locations

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– wiring

– shapes

– Examples• TTL chips on a PC board

• FPGA

• Custom CMOS chip

ai2.1 ai2.2

Deep Submicron Design Challenges

• Physical effects are increasingly significant

– Parasitics, reliability issues, power management, process variation, etc.

• Design complexity is high

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Design complexity is high

– Multi‐functionality integration

– Design verification is a major limitation on time‐to‐market

• Cost of fabrication facilities and mask making has increased significantly

Major challenges felt at physical design level:

• Mask printability

• Unbuffered signal reachability

• Parameter variations

• Power dissipation

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• Power dissipation

• Power/Ground variations

Printing

0.25µ 0.18µLayout

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0.13µ 90‐nm 65‐nm

Courtesy Synopsys Inc.

Mask Costs

Design Mask

OPC Fracture

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Mask Cost Data Volume

OPC, PSM, Fill increased feature complexity increased mask cost

Courtesy Synopsys Inc.

Design Rules Explosion

Number of design rules per process node

400

500

600

700

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0

100

200

300

0.35um 0.25um 180nm 150nm 130nm 90nm

Courtesy: A.B.Kahng, UCSD

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Interconnect Synthesis

Constraints:

• Delay

• Skew

• Signal integrity

SizingTopology

Optimized interconnect designs:

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• Signal integrity

...

Spacing• Other possible optimizations: buffer insertion, simultaneous device and interconnect sizing

…• Automatic solutions guided by accurate interconnect models

Process Variation

• In film thickness, lateral dimensions, doping

• Measured:

– From wafer to wafer

di di i di

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– From die to die – inter‐die

– Across die – intra‐die or process tilt

Process Variation Sources

• Wafer: topography, reflectivity

• Reticle: CD error, proximity effects, defects

• Stepper: Lens heating, focus, dose, lens aberrations

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aberrations

• Etch: Power, pressure, flow rate

• Resist: Thickness, refractive index

• Develop: Time, temperature, rinse

• Environment: Humidity, pressure

Important Device Variations

• Channel length L– Photolithography proximity effects– Optics deviations– Plasma etch dependencies

• Oxide thickness tox– Well‐controlled ‐‐ only significant between wafers

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• Threshold voltageVt– Varying doping– Annealing effects– Mobile Q in gate oxide– Discrete dopant variations (few dopant atoms in transistors)

Inter‐chip variation

• Many of the sources of variation affect all objects on the same layer of the same chip.

• Examples:

– Metal or dielectric layers might be thicker/thinner

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– Each exposure could be over/under exposed

– Each layer could be over/under etched

Interconnect Variations

• Line width and line spacing

– Photolithography

– Etching proximity effects

• Metal and dielectric thickness

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– Chemical Mechanical Polishing

• Contact resistance

– Contact dimensions

– Etch and clean steps

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Interconnect variation

• Looking at chip cross section

• Pitch is well controlled, so spacing is not independent

P5

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These dimensions can vary independently

Pitch is well controlled

P1

P2

P3

P4

P0

Width and spacing are not independent

Intra‐chip Deterministic Variation

• Optical Proximity Effects

• Metal Density Effects

• Center vs corner focus

You draw this: You get this:

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g

Reducing leakage power• Most important for mobile and internet servers, as

important as speed !

• Standby leakage – power consumed when whole chip is idle, Tj is NOT high

(Spec temp. for mobile at 50C)

– impact on battery life for portable devices

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• Active leakage– power consumed due to device leakage when chip is

working, and Tj is high (110C)• Subthreshold and Gate leakage significantly higher

– impact on overall chip thermal design power and frequency• Ptot=Pswitch + Pleak,,

Leakage Gating with Sleep Transistor

• Leakage is a main concern below 90nm• Partition the chip to allow individual control of the sleep transistors

– Sleep transistor is on while the block is working– Sleep transistor is off while the block is idle

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Block A

SleepControl

Block B

SleepControl

Block C

SleepControl

Block D

SleepControl

Sleep transistors in timing• Difficult to comprehend in STA

– Many cells share same virtual ground through one sleep transistor (legged/distributed in reality)

– Voltage of virtual ground depends on current drawn by all active gates on same sleep transistor

• Need to guarantee max/min voltage on virtual ground• How to verify statically min/max GND voltage

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y y / g

• Need cell models and interaction models for cells on different virtual ground– Logic grouping, by time of common switching– Estimate current needed in worst case

• Lack of support in timing tools is main limiting factor for using this technique

Why Automated Design Optimization?

• Complexity (circuits and design processes)– Abstraction level of optimization

– Abstraction level of design restriction

• Design times (and redesign times)

• Design metrics in digital circuits:

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– Timing: signal delay in critical paths

– Area

– Power dissipation

• Design metrics in analog circuits:– Various: bandwidth, gain, noise figure, etc., etc.

– Specific circuit knowledge required

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Implementation Choices

Custom Semicustom

Digital Circuit Implementation Approaches Memories

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Standard CellsCompiled Cells

Macro Cells

Cell‐based

Pre‐diffused(Gate Arrays)

Pre‐wired(FPGA's)

Array‐based

Source: J. Rabaey, UCB.

• Very high capacity today ‐‐ 10‐100M transistors

• Very high speed – 500MHz+

– Integration

– Specificity

• Can use any design style

– Full Custom

Application Specific Integrated Circuits

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– Standard‐cell (synthesized) – dominating methodology due to manufacturing considerations

– Hybrid

• Long fabrication time

– Weeks‐months from completed design to product

• Only economical for high‐volume parts

– Making the masks required for fabrication is becoming very expensive, in the order of $1M per design

CMOS IC Design: ASIC Perspective

STANDARD IC

FIELD

ASIC

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FULLCUSTOM

SEMI‐CUSTOM

FIELDPROGRAM‐MABLE

STANDARDCELL

GATE ARRAY,SEA OF GATES CPLDFPGA

DRAM – design‐manufacturing characteristics

• Enablers:

– Highly regular, low grain replicated layout patterns

• Problems:

Li h hi l i

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– Lithographic resolution

• Unique features:

– Very high manufacturing volume

DRAM – design‐manufacturing characteristics

• Abstraction level of key design decision:– Mask geometry, polygon level

• Granularity of manipulated objects:– Individual IC regions

• Predictability/modeling:

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Predictability/modeling:– The best possible

• Reusability: Maximal• Design flexibility: High• Design cost: Very high• Performance: Best possible

Gate Array Design

• Array of prefabricated gates/transistors

• Map cell‐based design onto gates

• Wire up gates

– in routing channels between gates

– over top of gates (sea of gates)

– predefined wiring patterns to convert transistors to gates

• CAD problems

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• CAD problems

– placement of gates/transistors onto fixed sites

– global and local wire routing in fixed space

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Gate Array — Sea‐of‐gates

rows of

cellsuncommitted

VDD

GND

polysilicon

metal

possiblecontact

UncommitedCell

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routing channel

In1 In2 In3 In4

Out

CommittedCell(4‐input NOR)

Source: J. Rabaey, UCB.

What is an FPGA?

• Field Programmable Gate Array

• Gate Array– Two‐dimensional array of logic gates

– Traditionally connected with customized metal

– Every logic circuit (customer) needs a custom‐manufactured chip

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Every logic circuit (customer) needs a custom‐manufactured chip

• Field Programmable– Customized by programming after manufacture

– One FPGA can serve every customer

• FPGA: re‐programmable hardware

Field‐Programmable Gate Arrays• Based on Configurable Logic Blocks (CLB)

CLB CLB CLB CLBCLB CLB CLB



•Types: SRAM and fuse/anti‐fuse

•Fuse‐based are cheaper, smallerand slower than SRAM‐based.

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•Switchboxes in SRAM‐based FPGACan occupy 70% of the chip area.

•SRAM very desirable in developmentphase due to re‐programmability.

Programmable Logic Devices

• Early version: Mask‐Programmable Gate Arrays– Build standard layout of transistors on chip

– Customer specifies wiring to connect transistors into gates/system

– Only has to go through last few mask steps of fabrication process, so faster than full chip fabrication

– May become popular again in the near future

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• Newer version: Programmable Logic Devices (PLD)– Use AND‐OR array to implement arbitrary boolean functions

– Programmed by burning fuses that define connection from input wires to gates

– Customer site programming allows rapid prototyping

– Limited capacity, functionality• Generally have to be used in conjunction with other parts to hold state

• Used to implement logic with moderate number of inputs (< 20)

Today ‐ Two Major Types of Programmable Logic

• CPLD (complex programmable logic device)

– coarse‐grained two‐level AND‐OR programmable logic arrays (PLAs)

– fast and more predictable delay

– simpler interconnect structures

• FPGA (field programmable gate array)

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FPGA (field programmable gate array) – fine‐grained logic cells

– high logic density

– good design flexibility

FPGA design‐manufacturing characteristics

• Enablers:

– Use of memory elements to customize prefabricated devices

• Problems:– Poor cost/performance ratio

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/p

• Unique features:– Short TAT (total turnaround time)

– No or very low NRE (non‐recurring expenses )

– Field‐reprogrammable

– Platform‐based design

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FPGA design‐manufacturing characteristics

• Abstraction level of key decision:

– Netlist

• Granularity of manipulated objects:– Logic/gate level

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g /g

• Predictability: high

• Reusability: Very high

• Design flexibility: very limited

• Design cost: very low

• Performance: very low

Standard Cell Design• Design circuit using standard cells

– cells are small numbers of gates, latches, etc.

• Technology mapping selects cells

• Place and wire them– cells placed in rows

• all cells same height, different widthsFunctionalmodule(RAM

Routingchannel

Logic cellFeedthrough cell

Row

s of

cel

ls

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– wiring between rows or over the cells

• CAD problems

– cell placement ‐ row and location within row

– wiring in channels

– minimize area, delay

(RAM,multiplier, …)

Standard Cell — Example

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[Brodersen92]

Standard Cell – The New Generation

Cell‐structurehidden underinterconnect layers

256a 52Source: J. Rabaey, UCB.

ASIC design‐manufacturing characteristics

• Enablers:

– Advanced EDA infrastructure

• Problems:

– Lithographic resolution

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g p

– Cost

• Unique features:

– Complex and expensive design process that can be justified only for very high volume IC devices

ASIC design‐manufacturing characteristics

• Abstraction level of key design decision:– All levels – logic an above

• Granularity of manipulated objects:– Standard cells and macros

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• Predictability: poor

• Reusability: moderate

• Design flexibility: low

• Design cost: moderate

• Performance: much below possible

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General Cell Design

• Generalization of standard cells

• Cells can be large, irregularly shaped– standard cells, RAMs, ROMs, datapaths, etc.

• Used in large designs– e.g. Pentium has datapaths, RAM, ROM, standard cells, etc.

• CAD problems

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– placement and routing of arbitrary shapes is difficult

Data path

CacheRAM

Std. Cells

DecodePLA

uCodeROM

FPGAs vs. Standard Cell ASICs

ParameterParameter FPGAFPGA Standard CellStandard CellCAD tool CostCAD tool Cost $2000$2000 $Millions$Millions

Mask CostMask Cost 00 $1.4M US @ 90 nm$1.4M US @ 90 nm

Bug FixBug Fix 1 hour1 hour ~10 weeks~10 weeks

Electrical & Electrical & Vendor’sVendor’s

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Optical Check Optical Check & Debug& Debug

Vendor’s Vendor’s ProblemProblem

Your Problem!Your Problem!

Time to Time to MarketMarket FastFast SlowSlow

Die SizeDie Size 2X to 20X2X to 20X 1X1X

Volume Cost Volume Cost 1X to 20X1X to 20X 1X1X

SpeedSpeed 0.3X to 0.6X0.3X to 0.6X 1X1X

PowerPower 2X to 5X2X to 5X 1X1XSource: Altera Corporation

Std Cell ASIC Development Cost Trend

pmen

t Costs ($M)

20

25

30

35

40

45

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Total D

evelop

Note: Conservative estimate; does not include re‐spins.

0

5

10

15

0.18 µm 0.15 µm 0.13 µm 90 nm 65 nm 45 nm

Masks & Wafers Test & Product Engineering

Software Design/Verification & Layout

Source: Altera Corporation

Result: Declining ASIC StartsResult: Declining ASIC StartsResult: Declining ASIC StartsResult: Declining ASIC Starts

Standard Cell/Gate Arrays

8000

10000

12000

gn Starts

256a 58Source: Dataquest/Gartner

0

2000

4000

6000

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

Desig

The Custom Approach

Intel 4004

256a 59Courtesy Intel

Design Methods

• Full custom design

– no constraints ‐ output is geometry

• highest‐volume, highest performance designs

– requires some handcrafted design

• 5‐10 transistors/day for custom layout

– use to design cells for other methods

– primary CAD tools

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• layout editor, plotter

• Cell‐based design

– compose design using a library of cells

– at board‐level, cells are chips

– cell = single gate up to microprocessor


• partitioning

• placement and routing

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Design Methods

• Symbolic design

– reduce problem to topology

– let tools determine geometry (following design rules)

– can reuse same topology when design rules change

• e.g. shrink wires from 2 microns to 1 micron

– used mostly to design cells

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• Procedural design

– “cells” are programs

– module generation ‐ ROMs, RAMs, PLAs

– silicon compilation ‐module assembly from HLL

• Analysis and verification

– design rule checking ‐ geometry widths, spacings ok?

– circuit extraction ‐ geometry => circuit

– interconnect verification ‐ circuit A == circuit B?

Analysis and Verification

• Analysis

– circuit extraction

• determine circuit from geometry

• compute circuit parameters from geometry

• resistance, capacitance, transistor sizes

– feed back to logic design, place & route

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• Verification

– design rules

• geometry rules ‐ e.g. widths, spacings

• electrical rules ‐ e.g. no floating gate inputs

– interconnect

• compare designed and extracted circuit

• pin‐point difference if there is one

– catch human and CAD tool bugs

Traditional design flow• Synthesis uses simple model for wire loads

» optimizes a measure which captures the number of wires

» gate delays• Layout design phase does not change gate

implementations

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p» optimizes summation of wire lengths» or a measure of topological longest delay

• Mismatches between predicted delays after synthesis and actual delays are of the order 100-200%.

High‐performance logical/physical flow

• logic optimization is poorly able to:– initially estimate delay in wires

– perform incremental logic optimization ‐ each iteration results in major perturbation in design

• place and route is poorly able to:

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– perform accurate timing analysis

– perform timing‐driven place and route (i. e. accept forward constraints)

– perform incremental place and route ‐ each iteration results in major perturbation in design

Timing closure problem causing 10’s, 100’s, 1000’s of iterations

Typical problems addressed in Physical Design

• Routing– Input:

• Sets of terminals to be connected

• design rules (layers, wire‐width, spacing (if any), size contacts …)

– Output:• Geometry of wires and contacts

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y

• adjusted component locations (if any)

– Routing phases:• global (loose routing)

• final (detailed routing)

– Routing techniques depend on the overall structure and style of the layout

• Placement– Input

• A set of components (transistors, (pre‐placed) layout blocks, dimensions, terminal locations)

• A list of connections to be made (net list)

• Design rules and constraints, e.g. scheme of legal slots on a gate array

– Output• Position and orientation of components

• Area estimate

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– Objectives• Minimal chip area subject to wireability

• Cost functions

– Placement techniques are very dependent on the specific placement problem at hand.

• Components on PC board

• standard cells

• Gate Arrays

• macro cells

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• Compaction (spacing)

– Input:• (possibly symbolic) layout (components and wires)

• design rules

– Output:

• legal layout with minimized area, i.e. positions of components f

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and dimensions of wires are adapted in a way to minimize chip area

– Initial layout may be illegal

– Sometime component dimensions are adjusted as well (resizing)

– Technology migration

• Design rule checking

– Input

• Hierarchical layout description, i.e. set of polygons, macros and macro‐cells

• set of design rules: minimal width, spacing, enclosure …

– Output

• Location of design rule violations

F t t b h k d ft t fi t b i l t d b “B l

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• Features to be checked oftem must first be isolated by “Boolean mask operations”.

Green AND red

Transistor gate

width

length

• Circuit extraction

– Input

• Full layout

• Possibly label information

– Output

• circuit level net list

• transistors

• wires

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• capacitance

• resistors

– Main sub‐tasks:

• device recognition (by Boolean mask operation)

• analysis of devices to calculate parameters

• extraction of connectivity information

• Mask data preparation– Fracturing

• Input: polygons

• Output: rectangles, trapezoids

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– Over/under‐sizing• Input: polygons

• Output: polygons with extended/retracted boundary

Techniques proven useful in all these subtasksof physical design and mask data processing

• Graph theory

– We use graphs to represent relations between objects

– An object might be:

• a piece of geometry, component

• a routing channel, a contact

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– A relation could be:

• is located above

• must be processed before

• is connected to

• Typical problems in graph theory:

– Proof or calculation of a property

• connection

• tree structure

• acyclic

• planarity

• chromatic number

– Derivation of specific sub graphs

• connected components

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connected components

• decomposition into paths

• find one (or all) paths between two specified nodes

• find one (or all) spanning trees

– Calculation of optimal sub graphs

• shortest/longest paths

• minimal spanning trees

• minimal cut sets

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Computational geometry deals with algorithmic aspects of geometrical problems

• Often restricted to one plane

• Objects:– points

– lines and line segments

– planar subdivision of the plane (stright line embedding of planar

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planar subdivision of the plane (stright line embedding of planar graphs)

• Typical questions:– intersection (segment with segment, polygon with a polygon)

– point location

– decomposition problems

– efficient storage and retrieval

256A class• Graph algorithms• General techniques• Data structures• Signal routing• Steiner trees• Placement• Floor planning

Cl k ti

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• Clock routing• Partitioning• Cell design• Physical design of FPGAs• Layout verification

Documents

Lecture1 Vlsi Cad introduction