CpE408: VLSI Physical Design and Testing

CATALOG DATAVLSI CAD algorithms for partitioning, floor planning, placement, routing, layout, and compaction. Test process and equipment, fault modeling and simulation, defects, Automatic Test Pattern Generation (ATPG), built-in self-test, design for testability.

COREQUISITES AND PREREQUISITESPrerequisites: CpE 300 and EE 320. All prerequisites must be completed with a grade of C or better. Advanced Standing required.

CREDITS-CONTACT HRS:3 Credit hrs, 2.5 Contact hrs/weekRelevant Textbooks1. Kahng, J. Lienig, I. Markov, J. Hu. VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer; 1st edition, 20112. M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.Course CoordinatorVenkatesan MuthukumarCourse InstructorVenkatesan Muthukumar, Mei YangCourse Topics1. Introduction to VLSI design cycles2. Basic algorithms of VLSI physical design.3. EDA in physical design – partitioning, floor planning and pin assignment, placement, global and detailed routing, over-the-cell routing and via minimization, clock and power routing, compaction4. Testing and fault detection in digital design - test process and equipment, logic and fault modeling, combinational & sequential atpg, functional testing, delay test, built-in self test, design for testabilityCourse OutcomesUpon completion of this course, students will be able to:1. Knowledge of VLSI design process flow (4) [1,2]2. Analyze VLSI design challenges and relate them to issues in physical synthesis. (1,2,4,7) [1,2]3. Formulate optimization problems as graph problems, as linear/integer programming problems, and as AI-based problems (1,2,4,7) [1,2]4. Formulate, explore, and report VLSI physical synthesis problems as optimization problems. (1,2,4,7) [1,2]5. Design simple algorithms to solve basic partitioning, placement, floorplanning and routing problems. (1,2,4,7) [1,2]

6. Analyze and determine faults in combinational and sequential circuits. (1,2,4,7) [1,2]7. Analyze and generate test vectors, design for test. (1,2,4,7) [1,2]8. Read current papers in physical VLSI design, VLSI CAD, Testing and communicate as formal presentations. (1,2,4,7) [1,2,3,5]Program Outcomes1. An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics2. An ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors3. An ability to communicate effectively with a range of audiences4. An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts5. An ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives6. An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions7. An ability to acquire and apply new knowledge as needed, using appropriate learning strategies.UULO COURSE OUTCOMES1. Intellectual Breadth and Lifelong Learning2. Inquiry and Critical Thinking3. Communication4. Global/Multicultural Knowledge and Awareness5. Citizenship and EthicsComputer UsageStudents use VLSI tools to create and analyze layouts and tests for VLSI systems. Synopsys and Cadence tools. GradingHomework Assignments = 40%Computer Assignments = 30% Midterms, Final = 30%Course Syllabus Preparer and DateVenkatesan Muthukumar, 10/26/2019