ECE357: Introduction to VLSI CAD

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  • ECE357: Introduction to VLSI CAD

    Prof. Hai Zhou

    Electrical Engineering & Computer Science

    Northwestern University

    1

  • Logistics

    Time & Location: MWF 11-11:50 TECH L160

    Instructor: Hai Zhou haizhou@ece.northwestern.edu

    Office: L461

    Office Hours: W 3-5P

    Teaching Assistant: Chuan Lin

    Texts:VLSI Physical Design Automation: Theory & Practice, Sait

    & Youssef, World Scientific, 1999.

    Reference:2

  • An Introduction to VLSI Physical Design, Sarrafzadeh &

    Wong, McGraw Hill, 1996.

    Grading: Participation-10% Project-30% Midterm-30%Homework-30%

    Homework must be turned in before class on each due date,late: -40% per day

    Course homepage:www.ece.northwestern.edu/~haizhou/ece357

    2

  • What can you expect from the course

    Understand modern VLSI design flows (but not the detailsof tools)

    Understand the physical design problem

    Familiar with the stages and basic algorithms in physicaldesign

    Improve your capability to design algorithms to solveproblems

    Improve your capability to think and reason

    3

  • What do I expect from you

    Active and critical participation

    speed me up or slow me down if my pace mismatches

    yours

    Your role is not one of sponges, but one of whetstones;

    only then the spark of intellectual excitement can

    continue to jump over

    Read the textbook

    Do your homeworks

    You can discuss homework with your classmates, but

    need to write down solutions independently

    4

  • VLSI (Very Large Scale Integrated) chips

    VLSI chips are everywhere

    computers

    commercial electronics: TV sets, DVD, VCR, ...

    voice and data communication networks

    automobiles

    VLSI chips are artifacts

    they are produced according to our will ...

    5

  • Design: the most challenging human activity

    Design is a process of creating a structure to fulfill arequirement

    Brain power is the scarcest resource

    Delegate as much as possible to computersCAD

    Avoid two extreme views:

    Everything manual: impossiblemillions of gates

    Everything computer: impossible either

    6

  • Design is always difficult

    A main task of a designer is to manage complexity

    Silicon complexity: physical effects no longer be ignored

    resistive and cross-coupled interconnects; signal

    integrity; weak and faster gates

    reliability; manufacturability

    System complexity: more functionality in less time

    gap between design and fabrication capabilities

    desire for system-on-chip (SOC)

    7

  • CAD: A tale of two designs

    Targethardware design

    How to create a structure on silicon to implement a

    function

    Aidsoftware design (programming)

    How to create an algorithm to solve a design problem

    Be conscious of their similarities and differences

    8

  • Emphasis of the course

    Design flow

    Understand how design process is decomposed into

    many stages

    What are the problems need to be solved in each stage

    Algorithms

    Understand how an algorithm solves a design problem

    Consider the possibility to extend it

    Be conscious and try to improve problem solving skills

    9

  • Basics of MOS Devices

    The most popular VLSI technology: MOS(Metal-Oxide-Semiconductor).

    CMOS (Complementary MOS) dominates nMOS andpMOS, due to CMOSs lower power dissipation, highregularity, etc.

    Physical structure of MOS transistors and their schematicicons: nMOS, pMOS.

    Layout of basic devices:

    CMOS inverter

    CMOS NAND gate

    CMOS NOR gate

    10

  • MOS Transistors

    n n

    psubstrate

    drain sourcegate

    insulator (SiO )2

    substrate

    drain source

    gate

    ntransistorschematic icon

    conductor (polysilicon)

    diffusion

    The nMOS switch passes "0" well.

    drain sourcegate

    insulator (SiO )2

    substrate

    drain source

    gate

    schematic icon

    conductor (polysilicon)

    diffusion

    pp

    nsubstrate

    ptransistor

    The pMOS switch passes "1" well.

    11

  • A CMOS Inverter

    A B

    GND

    VDD

    Metal Metaldiffusion contact

    Diffusion

    Polysilicon

    A B1 00 1

    pMOS transistor

    nMOS transistor

    A B

    pchannel (pMOS)

    nchannel (nMOS)

    VDD

    GND

    layout

    12

  • A CMOS NAND Gate

    A

    GND

    VDD

    Metal

    Diffusion

    Polysilicon

    BC

    A B C

    0011

    0101

    AB

    VDD

    GND

    0

    C

    111

    layout

    13

  • A CMOS NOR GateA B C

    0011

    0101

    A

    B

    VDD

    GND

    00

    1

    0

    C

    A

    GND

    VDD

    Metal

    Diffusion

    Polysilicon

    BC

    layout

    14

  • Current VLSI design phases

    Synthesis (i.e. specification implementation)

    1. High level synthesis (459 VLSI Algorithmics)

    2. Logic synthesis (459 VLSI Algorithmics)

    3. Physical design (This course)

    Analysis (implementation semantics)

    Verification (design verification, implementation

    verification)

    Analysis (timing, function, noise, etc.)

    Design rule checking, LVS (Layout Vs. Schematic)

    15

  • Physical Design

    Physical design converts a structural description into ageometric description.

    Physical design cycle:

    1. Circuit partitioning

    2. Floorplanning

    3. placement, and pin assignment

    4. Routing (global and detailed)

    5. Compaction

    16

  • Design Styles

    Different design styles

    Full custom Standard cell Gate array FPGA CPLD SPLD SSI

    Issues ofVLSI circuits

    Performance Area Cost Timetomarket

    Performance, Area efficiency, Cost, Flexibility

    17

  • Full Custom Design Style

    Data path

    ROM/RAM

    A/D converter

    I/O PLA

    Controller

    Random logic

    I/O padspins

    overthecell routing

    via(contact)

    18

  • Standard Cell Design Style

    D

    D D

    A

    A

    A

    A

    B

    B B

    BB

    C

    C

    Cell A Cell B

    Cell C Cell D Feedthrough Cell

    library cells

    19

  • Gate Array Design Style

    I/O pads

    pins

    prefabricated transistor array

    customized wiring

    20

  • FPGA Design Style

    logicblocks

    routing tracks

    switchesPrefabricated all chip components

    21

  • SSI/SPLD Design Stylex1 1y x2 y2 x3 y3 x4 y4

    F= i=14 xi yi

    x1

    1y

    x2

    y2

    x3

    y3

    x4

    y4

    F

    GND

    Vcc VccVcc

    GNDGND

    74LS86 74LS0074LS02

    x1

    1y

    x2y2

    x3y3x4y4

    F

    AND array

    OR array

    F

    x1 1y x2 y2

    x3y3x4y4

    (a) 4bit comparator. (b) SSI implementation.

    (c) SPLD (PLA) implementation. (d) Gate array implementation.

    22

  • Comparisons of Design Styles

    Full Standard Gatecustom cell array FPGA SPLD

    Cell size variable fixed height fixed fixed fixedCell type variable variable fixed programmable programmableCell placement variable in row fixed fixed fixedInterconnections variable variable variable programmable programmable

    * Uneven height cells are also used.

    23

  • Comparisons of Design Styles

    Full Standard Gatecustom cell array FPGA SPLD

    Fabrication time + +++ ++Packing density +++ ++ + Unit cost in large quantity +++ ++ + Unit cost in small quantity + +++ +Easy design and simulation ++ +Easy design change ++ ++Accuracy of timing simulation + +Chip speed +++ ++ +

    + desirable not desirable

    24

  • Design-Style Trade-offs

    1 10 102 103 104 105 106

    1

    10

    102

    103

    optimal solution

    SPLDsCPLDs

    FPGAs

    SSIs

    Logic Capacity (Gates)

    Turnaround Time (Days)

    Fullcustom

    104

    107

    semicustom

    25

  • Algorithms 101

    Algorithm: a finite step-by-step procedure to solve aproblem

    Requirements:

    Unambiguity: can even be followed by a machine

    Basic: each step is among a given primitives

    Finite: it will terminate for every possible input

    26

  • A game

    An ECE major is sitting on the Northwestern beach andgets thirsty, she knows that there is an ice-cream booth

    along the shore of Lake Michigan but does not know

    wherenot even north or south. How can she find the

    booth in the shortest distance?

    Primitives: walking a distance, turning around, etc.

    27

  • A first solution

    Select a direction, say north, and keep going until find thebooth

    Suppose the booth is to the south, she will never stop... ofcourse, with the assumption she follows a straight line, not

    lake shore or on earth

    28

  • Another solution

    Set the place she is sitting as the origin

    Search to south 1 yard, if not find, turn to north

    Search to north 1 yard, if not find, turn to south

    Search to south 2 yard, if not find, turn to north

    Search to north 2 yard, if not find, turn to south

    ... (follow the above pattern in geometric sequence 1, 2, 4,8, ...)

    29

  • OR

    n = 1;

    While (not find) do

    n = n+ 1;

    Search to south 2n, and turn;

    Search to north 2n, and turn;

    29