Ms Vlsi-cad Syllabus_aug 2010

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MASTER OF SCIENCE (MS) IN

VLSI-CADSYLLABUS[August 2010]

1

MS VLSI-CAD Program Structure

MS VLSI-CAD I SemesterInternal Assessment 50 Duration of Exam in Hrs. Final Exam 50

No of Hrs/weekPractical Tutorial Lecture Credit

EDA 60 1 EDA 603 EDA 605 EDA 607

Data Structures & Algorithms High Level Digital Design Digital Systems & VLSI Design CAD for VLSI Elective 1

MMS 601 / ESD 601 / ESI 601 ESD 616.1

3 3 3 3 3 15

-

3 3 3 3 3 12 27

4 3 3 3 4 1 1 1 4 1 25

3 3 3 3 3 3 3 3 -

50 50 50 50 50 50 50 50 100 100

50 50 50 50 50 50 50 50 -

100 100 100 100 100 100 100 100 100 100

EDA 623 EDA 625 EDA 627 EDA 633 EDA 635

High Level Digital Design Lab Digital Systems & VLSI Design Lab CAD for VLSI Lab Mini Project 1 Seminar 1 TOTAL

Total

Sub Code

Subject Name

Commo n With

Maxim um Marks

2

MS VLSI-CAD II SemesterInternal Assessment 50 Duration of Exam in Hrs. Final Exam 50

No of Hrs/weekPractical Tutorial Lecture Credit

EDA 602 EDA 604 EDA 606 EDA 608

Digital Signal Processing Advanced VLSI Design Advanced Logic Synthesis Low Power VLSI Design Elective 2 Advanced VLSI Design Lab Advanced Logic Synthesis Lab Low Power VLSI Design Lab Mini Project 2 Seminar 2 TOTAL

MMS 603 / ESD 602 / VSD 616.1 / ESI 616.1 / EWT 618.1 VSD 616.2

3

-

3

4

3

50

50

100

3 3 3 3 15

-

3 3 3 3 12 27

3 3 3 4 1 1 1 4 1 25

3 3 3 3 3 3 3 -

50 50 50 50 50 50 50 100 100

50 50 50 50 50 50 50 -

100 100 100 100 100 100 100 100 100

EDA 624 EDA 626 EDA 628 EDA 634 EDA 636

Third & Fourth SemesterEDA 699 Project Work 40 90

Total Number of Credits to Award Degree

Total

Sub Code

Subject Name

Commo n With

Maxim um Marks

3

List of ElectivesElective 1 Sub CodeEDA 615.1 EDA 615.2 EDA 615.3 EDA 615.4

Elective 2 Common WithMMS 615.1 / ESD 605 / ESI 603

SubjectSystem Software Verification & Testing VLSI for Multimedia & Telecommunication Systems Large Area Micro Electronics

Sub CodeEDA 616.1 EDA 616.2 EDA 616.3 EDA 616.4 EDA 616.5 EDA 616.6

SubjectLinux & Scripting Languages High Speed Digital Design VLSI Signal Processing System-On-Chip Design RF Microelectronics Chip Design Nano Electronics

Common WithESD 615.2 / ESI 616.2

MS VLSI-CAD I Semester (Syllabus)EDA 601 / MMS 601 / ESD 601 / ESI 601: Data Structures and Algorithms1.0 [L-T-P-C: 3-0-3-4] Introduction 1.1 Algorithm Specification 1.2 Performance Analysis Algorithm Analysis Techniques 2.1 Analysis of Recursive Programs 2.2 Solving Recurrence Equations 2.3 A General Solution for a large class of Recurrences 4

2.0

3.0

Elementary data structures 3.1 Implementation of Lists 3.2 Stacks 3.3 Queues Sorting & Searching Techniques 4.1 Quick sort, Heap sort, Merge sort 4.2 Binary search, linear search, fibonacci search Operations on Sets 5.1 Introduction to Sets 5.2 A Linked- List implementation of Sets 5.3 The Dictionary 5.4 The Hash Table Data Structure Trees 6.1 6.2 6.3 Graphs 7.1 7.2 7.3 7.4 7.5 Basic Terminology Implementation of Trees Binary Trees Basic definitions Representation of Graphs Minimum Cost Spanning Tree Single Source Shortest Paths All-Pairs Shortest Path

4.0

5.0

6.0

7.0

8.0

Algorithm Design Techniques 8.1 Divide-and-Conquer Algorithms 8.2 Dynamic Programming 8.3 Greedy Algorithms 8.4 Backtracking NP-Hard and NP-Complete Problems

9.0

Reference Books Introduction to Algorithms : Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest. Design & Analysis of Algorithms : Aho, Hopcroft and Ulmann Data structures and algorithm analysis in C : Mark Allen Weiss Computer Algorithms : Ellis Horowitz, Sartaj Sahni, Sanguthevar Rajasekaran

5

EDA 603 / ESD 616.1: High Level Digital Design[L-T-P-C: 3-0-0-3] Section 1 Review of Digital Design 10 Hrs

a. Combinational circuits - Design steps Arithmetic Circuits - Full adder, Serial Adder, Adder/Subtractor, Ripple Carry Chain, Carry Look-Ahead adder, Carry Select Adder, ALU, Parity Generator, Comparator, Multiplier. b. PLA, PAL, PLD, CPLD, ROM, FPGA Introduction c. Sequential circuits - Design steps Flip-flops, registers, counters d. Finite State Machines Introduction to FSMs, capabilities, minimization and transformation of sequential machines Synchronous and asynchronous FSMs Mealy and Moore machines State assignment of synchronous sequential machines Structure of sequential machines Verification and testing of sequential circuits Section 2 SystemVerilog for design Section 3 Introduction FPGA Spartan III Architecture Section 4 Application on Digital Design a. FIFO Design [SNUG Paper] b. Cordic Algorithm [IEEE Paper] c. Floating Point Arithmetic Blocks [IEEE Paper] Floating point Addition Floating point Subtraction Floating point Multiplication Floating point Division d. AMBA Bus Specification [ARM Specification] 15 Hrs 7 Hrs 10 Hrs

Total no. of hours: 42 Reference Books An Engineering Approach to Digital Design by Flectcher SystemVerilog for design by Stuart Sutherland, Simon Davidmann, Peter Flake 6

SNUG Paper [freely available] IEEE Paper [MU campus available] ARM Specification

EDA 605: Digital Systems & VLSI Design[L-T-P-C: 3-0-0-3] Part A: Digital Systems & VLSI Design 1.0 Review of logic families 1.1 Different logic families and their comparison 1.2 Logic levels & Noise margin features 1.3 Fan-in, Fan-out, Active load, Sinking & Sourcing currents 1.4 Propagation delay 1.5 MOS technology and VLSI MOS transistor theory 2.1 Introduction 2.2 MOS device design equations 2.3 CMOS inverter DC characteristics 2.4 Static load MOS inverters 2.5 Pass transistor, Transmission gate, tristate inverter Circuit characterization 3.1 Resistance estimation 3.2 Capacitance estimation 3.3 Switching characteristics 3.4 CMOS gate transistor sizing 3.5 Power dissipation 3.6 Scaling principles CMOS circuit and layout design 4.1 CMOS logic gate design 4.2 Basic physical design of simple gates 4.3 CMOS logic structures 4.4 Clocking strategies Memory, registers & System timing aspects 5.1 3 transistor memory cell 5.2 nMOS pseudo static memory cell, Two 4-bit words of RAM array Part B: Process Technology 7

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0

Review of semiconductors Crystal Growth & Wafer Preparation Contamination Control Wafer Fabrication CMOS process technology - n-well, p-well, twin-tub, SOI and Bi-CMOS process. Oxidation Photolithography Doping Deposition Metallization Wafer test, Evaluation and packaging.

Reference Books M. M. Mano, Digital Design, Prentice Hall, 1984 Neil H. E. Weste, Kamran Eshraghian, Principles of CMOS VLSI Design: A systems perspective, Second Edition, Addison Wesley, 1999. Douglas A Pucknell & Kamran Eshraghian, Basic VLSI design: Systems and Circuits Microchip Fabrication, by Peter Van Zant, 3rd Edition, McGraw-Hill, International Edition. VLSI Technology, by S.M. Sze, 2nd Edition, McGraw-Hill International Edition.

EDA 607: CAD for VLSI[L-T-P-C: 3-0-0-3] A. GRAPH THEORY : 1.0 Paths and circuits 1.1 Walks, Paths, Circuits, Connected Graphs, Connected Components, Eulers graph, Operations on graphs, TSP. 3 Hrs

2.0 3.0 4.0 5.0

Cut sets and cut vertices 3 Hrs 2.1 All cut-sets, connectivity and separability, isomorphism. Trees and fundamental circuits 3.1 Distance, center, binary trees, spanning trees, fundamental circuits Planar and dual graphs 4.1 Kuratowskis graphs, detection of planarity, dual. Eulerian and Hamiltonian tours 5.1 Finding Eulerian circuits, Coloring graphs edge 3 Hrs 1 Hr 3 Hrs

8

Coloring, vertex coloring, face coloring. B. CAD FOR VLSI: 6.0 Layout Compaction 6.1 Design rules, symbolic layout, Algorithms for layout compaction 3 Hrs

7.0

Placement and Partitioning 4 Hrs 7.1 Circuit representation, Wire length estimation, Types of placement problems, Placement algorithms, and partitioning algorithms Floor planning 2 Hrs 8.1 Floor planning concepts, Shape Functions and Floor plan sizing Routing 6 Hrs 9.1 Global routing, algorithms for global routing, local routing, types of local routing problems, Area Routing, algorithms for area routing, Channel routing, algorithms for channel routing. Logic synthesis and verification 4 Hrs 10.1 Introduction to Combinational logic synthesis, Binary decision diagrams, ITE & ITE-CONTSNT algorithm in two level logic synthesis. High level logic synthesis 9 Hrs 11.1 Need for high-level logic synthesis, Design representation Transformations, Partitioning, Scheduling, Allocation. and

8.0

9.0

10.0

11.0

Total no of hours: 41 Reference Books Graph theory - Narsingh Deo (Prentice-Hall of India private ltd) Graph theory - Gibbons Algorithms for VLSI Design Automation - Sabih H. Gerez (John Wiley and Sons) High Level Synthesis -Introduction to chip and System Design Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin (Kluwer Academic Publishers) Logic synthesis and verification algorithms - Gary D. Hachtel, Fabio Somenzi ( Kluwer Academic Publishers) Computer aided logical design with emphasis on VLSI Frederick J Hill, Gerald R. Peterson (john Wiley & sons)

Elective - 19

EDA 615.1 / MMS 615.1 / ESD 605 / ESI 603: System Software[L-T-P-C: 3-0-3-4] 1.0 Assemblers 1.1 Designing one pass and two pass assemblers 1.2 Macro-processors Loaders and linkers 2.1 Static linking 2.2 Dynamic Linking Lexical Analyzers: 2.3.1 Regular Expr