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May 2012 Dynamic Programming 1 Dynamic Programming and Some VLSI CAD Applications Shmuel Wimer Bar Ilan Univ. Eng. Faculty Technion, EE Faculty

Dynamic Programming and Some VLSI CAD Applications

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Dynamic Programming and Some VLSI CAD Applications. Shmuel Wimer Bar Ilan Univ. Eng. Faculty Technion, EE Faculty. Outline. NP Completeness paradox Efficient matrix multiplication by dynamic programming Dynamic programming in a tree model Optimal tree covering in technology mapping - PowerPoint PPT Presentation

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Page 1: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 1

Dynamic Programming andSome VLSI CAD Applications

Shmuel WimerBar Ilan Univ. Eng. Faculty

Technion, EE Faculty

Page 2: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 2

Outline

• NP Completeness paradox

• Efficient matrix multiplication by dynamic programming

• Dynamic programming in a tree model

– Optimal tree covering in technology mapping

– Optimal floor planning

– Optimal buffer insertion

• Dynamic programming as sequential decision problem

– Resource allocation

– The knapsack problem

– Automatic cell layout generation

– Optimal wire sizing

Page 3: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 3

NP Completeness Paradox

1 2 1 2Let , , , and the sizes , , , in constitute an

arbitrary instance of PARTITION Problem, where we ask whether there exists

satisfying .

n n

a A a A A

A a a a s a s a s a

A A s a s a

Z

1 2

If is an odd integer than we the answer is NO. Otherwise,

define a Boolean function , , as follows:

there exists a subset , , , , ,

otherwise

a A

i a A

B s a

t i j

T A a a a s a jt i j

F

11, iff either 0 or . For 1 and 0 2 ,

iff either 1, or and 1, . The answer is

then YES iff , 2 .

i i

t j T j j s a i n j B t i j T

t i j T s a j t i j s a T

t n B T

Page 4: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 4

1 2 3 4 5

1 2 3 4 5

, , , , ,

1, 9, 5, 3 and 8.

A a a a a a

s a s a s a s a s a

Example :

j

i0 1 2 3 4 5 6 7 8 9 10 11 12 13

1

2

3

4

5

T T F F F F F F F F F F F F

T T F F F F F F F T T F F F

T T F F F T T F F T T F F F

T T F T T T T F T T T F T T

T T F T T T T F T T T T T T

1 2 4 3 51 9 3 13 26 2s a s a s a s a s a

Page 5: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 5

Here is the paradox: It is easy to define an iterative

algorithm to fill the entries of the table. Conplexity

of such algorithm is very low polynimial in table

size .nB

Have we found a polynomial algorithm to PARTITION,

thus proving that P=NP?

Every can be coded at the input by a string of

log . The length of the input of PARTITION

is therefore log . is not bounded by any

polynomial function of log .

i

i

s a

O s a

O n B nB

O n B

Page 6: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 6

The NP completeness of PARTITION stronly depends

on allowing arbitrary large input numbers. If those are

bounded in advance, the algorithm is polynomial time.

We call such algorithms l.pseudo - polynomia

Page 7: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 7

Optimal Matrix-Chain Multiplication

Let , and be , and matrices, respectively.

consider the cost of computing

as the number of products.

A B C k l l m m n

D ABC AB C A BC

1The elements of are given by ,

1 , 1 , i.e., products are required

for the matrix mltiplication.

mrs rt tstE BC E B C

r l s n l m n

100,5 5,50 100 5 50

For 10, 100,

10,100 10 100 50

5,50 1

5 and 50,

7500

10,100 100,5 10 100

0

70 5 505 500

B C

A B

l n

C

m

A

k

Page 8: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 8

We could calculate upfront the best paranthesization,

but how many paranthesization exist?s

1 2

: How to paranthesize chain multiplication

to minimize # products?nA A AProblem

We could split the matrix product at any 1 1

into:

multiply matrices multiply matrices .

k n

k n k

Page 9: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 9

1

1

This yields the recurrsive equation

1 if 1 ,

if 2nk

nP n

nP k P n k

.. 1

1

.. 1..

..

Denote the result of . For 1,

paranthesization is a tree whose root splits

into and . Optimal paranthesization implies

optimal paranthesization of and

i j i ji

i ji

i k k j

i k

A A A A i k j

A A A

A A

A A

1.. each.k j

3 21whose solution is 4 1 .

is exponential in .

nP n n

P n n

Page 10: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 10

.. 1

1

Let [ , ] be minimal number of scalar multiplications

to produce . Let size be . Then

0 if[ , ]

min [ , ] [ 1, ]

i j i ii

ji ki k j

m i j

A A p p

m i jm i k m k j p p p

if

i j

i j

Optimal solution solves recurrsively subproblems.

Optimal solution must contain optimal solutions

of subproblems.

1..

[1, ] is then the smallest number of scalar

multiplications to compute .n

m n

A

Page 11: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 11

2

Recurrence is not better than exploring all

parenthesizations since it expands a full binary

tree and same [ , ] is computed many times,

while only distinct [ , ] exist.

m i j

O n m i j

Let [ , ] denote the split index at which [ , ]

is obtained. The trick is to compute [ , ] in

increasing order of chain length = . We use

two tables [1.. ,1.. ] and [1.. ,1.. ] to store

[ , ] and

s i j m i j

m i j

l j i

m n n s n n

m i j

[ , ], resp.s i j

Page 12: Dynamic Programming and Some VLSI CAD Applications

Overlapping solutions of sub - problems are memorized.

May 2012 Dynamic Programming 12

3

Matrix-chain product minimization can be computed

in time.O n

Page 13: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 13

1 2

// initialize length-1 chai

( , , , ) {

for ( 1 to ) { [ , ] 0 }

for ( 2 t

ns

// increasing chain lengtho ) {

for ( 1 to 1) {

// set starting index

np p p

i n m i i

l n

i n l

j i l

MatrixChainOrder

..

1; {

[ , ] ;

for ( to 1

// set ending index

// initialize smallest number of scalar products

/) {

/ set the split of

// [ , ] and [ 1,

] are known

! i jA

m i k m k j

m i j

k i j

1 [ , ] [ 1, ] ;

if ( [ , ]) { [ , ] ; [ , ] }

} } }

return tables and ;

}

i k jq m i k m k j p p p

q m i j m i j q s i j k

m s

Page 14: Dynamic Programming and Some VLSI CAD Applications

15125 10500 5375 3500 5000 0

11875 7125 2500 1000 0

9375 4375 750 0

7875 2625 0

15750 0

0

May 2012 Dynamic Programming 14

3 3 3 5 5

3 3 3 4

3 3 3

1 2

1

i=1 2 3 4 5 6

J=6

5

4

3

2

1

m[1..6,1..6]

i=1 2 3 4 5 6

J=6

5

4

3

2

1

s[1..6,1..6]

1 2 5

1 3 5

1 4 5

[2,2] [3,5] 0 2500 35 15 20 13000,

[2,5] min [2,3] [4,5] 2625 1000 35 5 20 7125, 7125

[2,4] [5,5] 4375 0 35 10 20 11375,

m m p p p

m m m p p p

m m p p p

1 2 3 4 5 6: 30 35, : 35 15, :15 5, : 5 10, :10 20, : 20 25 A A A A A A

Page 15: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 15

Procedure does not directly

perform multiplication.

MatrixChainOrder

This information is derived from [1.. ,1.. ] by

recurrsive construction of the split binary tree.

s n n

1..

1.. [1, ]

[1, ] 1..

Starting from [1, ] that yields , then calling

[1, [1, ]] and [ [1, ] 1, ], yielding

and , resp., etc.

n

s n

s n n

s n A

s s n s s n n A

A

Page 16: Dynamic Programming and Some VLSI CAD Applications

1

1

1

.. [ , ]

[ , ] 1..

( , , [1.. ,1.. ], , ) {

if ( ) {

( , , [1.. ,1.. ], , [ , ]);

( , , [1.. ,

n

n

n

i s i j

s i j j

A A s n n i j

i j

A

A A s n n i s i j

A

A A s n

MatrixChainMultiply

MatrixChainMultiply

MatrixChainMultiply

.. [ , ] [ , ] 1..

1.. ], [ , ] 1, );

return ;

}

else { return }

}i

i s i j s i j j

n s i j j

A A

A

May 2012 Dynamic Programming 16

Construction of optimal solution (backtracking).

Page 17: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 17

Elements of Dynamic Programming

• A problem exhibits optimal substructure if an optimal solution to the problem contains within it optimal solutions to sub problems.

• In a sequence of decisions the remaining ones must constitute optimal solutions regardless of past decisions. (principle of optimality).

• The space of sub problems must be small, namely, a recursive solution must solve same problem many times. Optimization problem has overlapping sub-problems.

Page 18: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 18

• Overlapping sub-problems called by recursive solution are memorized (encoded in a table), hence addressing their solution only once.

• Optimal solution is constructed by backtracking.

Page 19: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 19

Optimal Tree Covering

A problem occurring in mapping logic circuit into

new cell library. Given:

•Rooted binary tree T(V,E) called subject tree (cone of

logic circuit), whose leaves are inputs, root is an output and

internal nodes are logic gates with their I/O pins.

•A family of rooted pattern trees (logic cells of library),

each associated with a non-negative cost (area, power,

delay). Root is cell’s output and leaves are its inputs.

Page 20: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 20

A cover of the subject tree is a partitioning where

every part is matching an element of library and

every edge of the subject tree is covered exactly

once.

Find a cover of subject tree whose total sum

of costs is minimal.

Page 21: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 21

r

s t

u

t1 (2) t2 (3) t5 (5)t4 (4)t3 (3)

t2

t1 t1

t3

3+2+2+3=10

t4t1

t3

4+2+3=9

t2

t5

3+5=8

Page 22: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 22

NAND2 (11)

AOI21 (3)

NAND3 (3)

NAND2 (2)

INV (1)

a

b

c

d

g

e

f

j

h

i

INV (3)

NAND2 (5)

NAND2 (8) INV (9)

AOI21(6)

NAND2 (5)

NAND3 (3)

INV (1)

NAND2 (2)

INV (1)

NAND2 (2)

NAND3 (12)

Observation: pattern p rooted at the root of T(V,E) yields

minimal cost only if the cost at any of p’s leaves is minimal,

suggesting bottom-up matching algorithm.

Page 23: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 23

TreeCover ( ( , ), ) {

foreach ( ) {

if ( is a leaf) { cost =0 } else { cost 1 }

}

while (some with cost 1 exists) {

select whose childeren are all nonnegative cost;

T V E P

v V

v v v

v V v

v V

cost ;

set of all matching patterns at ;

matching leaves of an ;

cost min cost cost ;

} }

u L mm M v

v

M v v

L m u V m M v

v m u

Page 24: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 24

v

u , qu , q

, : driver to receiver delay. Root required time: min , .i i iid v u T q d v u

Optimal Buffer Insertion

buffer insertions

: max min , by buffer insertion at internal nodes.i iiq d v uProblem 1

buffer insertions

: max min , , s.t. power and area constraints.i iiq d v uProblem 2

?

?

?

?

Buffer reduces load delay but adds internal delay, power and area.

? ?

?

Page 25: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 25

Delay Model

- nodes along path from root to node

- nodes of sub-tree rooted at node

- resistance along common paths

- capacitance of sub-tree

jj k lkl

jj T kk

k k

T k k

R R

L C

, i ji j j jji j i

d v u R C R L

R3

C1

R2

R6

R5

R4

R7

C6

C5

C4

C7

R1

C2

C3

01

3

2

4

5

6

7

Page 26: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 26

Bottom-Up Solution

without buffer

1

2K K K K K K

K K K

T T R L R C

L L C

min ,K M N

K M N

T T T

L L L

RK

CK

K

(T’K , L’K)

RM

CM

M

sub-tree

(TM , LM)

RN

CN

N

sub-tree

(TN , LN)

with buffer

1

2K K buffer buffer K K buffer K K

K buffer K

T T D R L R C R C

L C C

(TK , LK)

Page 27: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 27

Outline of Algorithm

Compare , and , at a node. If and then ,

is dropped as it necessairly results non optimal solution. Candidate optimal

solutions are obtained at root, from which an optimal on

T L T L T T L L T L

e is chosen. Nodes

of buffer insertion are obtained by top-down backtracking.

L’K

T’K

LM

TM

LN

TN

+ =

Merging sub-tree solutions at a parent node takes linear time!

With b nodes, 2b buffer insertions exist. There’s a polynomial solution!

Page 28: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 28

Interconnect Signal Model

line-to-line coupling

line-to-line coupling

driver’s resistance

receiver’s load

line resistance

signal's activity, 0<= AF <=1

Using Elmore delay model, simple, inaccurate but with high fidelity

Page 29: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 29

Interconnect Bus Model

σ1

A

σi

σn

σn-1

Wi

Si

Si+1

Ri Ci

L

Page 30: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 30

Delay and Dynamic Power Minimization

, , , , - technology parameters, driver's resistance,

capacitive load and bus length .i i i i i

L

signal’s delay:

1 1, , 1 1 , 1i i i i i i i i i i i i i iD s w s w w w s s i n

1 1, , 1 1 , 1i i i i i i i i iP s w s w s s i n

signal’s dynamic power:

, - technology parameters, signal's activity, and bus length .i i L

Page 31: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 31

max1 11 1

, , , or , max , ,nsum

i i i i i i i ii i nD s w D s w s D s w D s w s

Minimize bus delay

11, , ,

n

i i i iiP s w P s w s

Minimize bus power

01 0

n n

ii iw s A

Subject to:

1 1,..., and ,...,i p i qs S S S w W W W

In 32nm node and beyond spaces and widths are very few discrete values

Continuous optimization and its well-known results are invalid. The sizing

problem is NP-complete. A pseudo polynomial resource allocation dynamic

programming solution is suitable.

Page 32: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 32

0 0 1 1: , , , ,..., , is a sequence of allocation decisions.n nw s w s w s

0 0

Observation: After , , 0 , are decided, optimal allocation

of rest 1 wires depends only on and .

i i

j j

j i ii i

w s i j

n j s A w s

0 0 0 0

0.. 0..0 0 0 0

: , ,..., , is and : , ,..., , is if:

1.

2.

3. and

j j j j

j j j j

j i i i i ji i i i

j j

w s w s w s w s

A s w s w A

s s

D D P P

dominant redundant

0.. 0.. 0..The treiplet , , , , , is a and it is

sufficient to maintain only states.

j j j j j jA s D A s P A s state

non redundant

Page 33: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 33

Dynamic programming comprises decision stages. Each stage expands all

non redundant states.

n

0.. 1 1 0.. 1 1 0.. 1 1

0.. 0.. 0..

1 1

A state , , , , , at stage 1 is obtained

from states , , , , , of stage by augmentations

with all permissible , ,..., ,..., .

j j j j j j

j j j j j j

q p

A s D A s P A s j

A s D A s P A s j

w s W W S S

A stage maintains only non redundant states.

Algorithm can be extended to arbitrary routing by construction of wire

visibilty graph and topological ordeing of graph's nodes.

Page 34: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 34

Floorplan Graph representation

Floorplan and Layout

B2B1

B3 B5

B4

B6

B12

B9

B8 B7

B10

B11

B2

B1

B10B5

B12B6

B3

B9

B8

B7

B11B4

Vertices - vertical lines. Arcs - rectangular areas where blocks are embedded.

Floorplan is represented by a planar graph.

A dual graph is implied.

Page 35: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 35

• Actual layout is obtained by embedding real blocks into floorplan

cells.

– Blocks’ adjacency relations are maintained

– Blocks are not perfectly matched, thus white area (waste) results

• Layout width and height are obtained by assigning blocks’

dimensions to corresponding arcs.

– Width and height are derived from longest paths

• Different block sizes yield different layout area, even if block sizes

are area invariant.

From Floorplan to Layout

Page 36: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 36

Optimal Slicing Floorplan

hh

vv vv

B2B1

B3 B5

B4

B6B11B3 B4 B5 B6 B8 B9 B10

B1 B2 B7

hhhh

B12

B12

B9

B8 B7

B10

B11

Slicing tree. Leaf blocks are associated with areas.

v

Top block’s area is divided by vertical and horizontal cut-lines

Page 37: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 37

Let block , 1 , have possible implementations , ,

1 , having fixed area .

In the most simplified case , 1 , have 2 implementations

corresponding to 2 orientations.

:

i i

i j j j

i i

i j j i

i

B i b x y

j n x y a

B i b

Problem Find among the 2 possible block orientations , 1 2 ,

the one of smallest area.

b b

i i

(L. Stockmeyer): Given slicing floorplan of blocks whose

slicing tree has depth , finding the orietnation that yields the smallest

area takes time and storage.

b

d

O bd O b

Theorem

Page 38: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 38

+ =

+ =

+ =

Merge horizontally two width-height sets (vertical cut-line)

v

parent left right

parent left right

max ,h h h

w w w

Page 39: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 39

h

Size of new width-height list equals sum of lengths of children lists, rather than their product.

1 1

parent

par

// horizontal cut-line

// lists are sorted in descend

VerticalMerging ( , , , ) {

1; 1;

while (( ) && ( )) {

in

max , ;

g order of width

ts

i i j ji j

i j

w h w h

i j

i s j t

w w w

h

ent ;

if ( ) { }

else if ( ) { }

else { ; }

//

}

}

i j

i j

i

i j

j

h h

w w i

w w j

i wj w

Page 40: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 40

Sketch of Proof

• Problem is solved by a bottom-up dynamic programming algorithm

working on corresponding slicing tree.

• Each node maintains a set of width-height pairs, none of which can

be ruled out until root of tree is reached. Size of sets is in the order

of node’s leaf count. Sets in leaves are just Bi’s two orientations.

• The sets of width-height pairs at each node is created by merging

the sets of left-son and right-son sub-trees in time linear in their

size.

• Width-height pair sets are maintained as a sorted list in one

dimension (hence sorted inversely in the other dimension).

• Final implementation is obtained by backtracking from the root.

Page 41: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 41

Automatic Cell Layout Generation

Transistor placement comprises:

1. Transistor P-N pairing

2. Pair ordering

3. Pair flipping – optimize cell area, node cap, potential cell abutment, cell’s internal routing

3 step process:

1. Transistor placement

2. Interconnect completion

3. Design rule adherence

aa Vcc

Vcc

bb Vss

Vss b

a

Vcc

Vss

Vcc

Vss

Cost=0

a

b

a

bV

ccV

ss

Cost=1

a Vcc

b

a

Vcc

b Vss

Vss

Cost=2

Page 42: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 42

• Most cells unfortunately contain more than 4 transistors.

• A flip configuration of a pair depends on the flip of its left and right neighbors.

• Seek the flip configuration yielding minimal sum of abutment cost.– With n pairs, there are 2n solutions to consider.

• Observation: An optimal flip of j+1 pairs subject to given right end configuration of pair j necessitates that the first j pairs have been optimally flipped.– Principle of optimality, optimal sub problem solutions.

• Observation: The optimal flip of rest n – j pairs is independent of the first j flips except the right end configuration of pair j.– This defines a state for which only the lowest cost flip of j pairs is of

interest.

• Dynamic Programming solution is in order. (Bar-Yehuda et. al.)

Page 43: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 43

abutment cost

State Augmentation

a

b

c

d

c

b

a

d

c

d

a

b

a

d

c

b

a

b

c

d

c

b

a

d

c

d

a

b

a

d

c

b

stage j stage j+1

Page 44: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 44

• Dynamic programming takes O(n) time.

• Can be extended to multi-row cell (double height, etc.).

• It can be combined in a DFS algorithm which considers

simultaneously paring, pair ordering and optimal flip, without any

complexity overhead (state augmentation takes O(1) time)

• Dynamic programming is solving in fact a shortest path algorithm

on the state transition graph.

• New litho rules in 32nm and smaller feature size offer many

optimization opportunities.

Page 45: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 45

Resource Allocation

1all allocations

1

The optimal resource allocation problem is therefore:

maximize ,

subject to: 0 , 1

n

i ii

n

i ii

i

p x

c x K

x B i n

units (integer) of a resource are used for manufacturing commodities.

The production of units (integer) of commodity consumes of the

resource (integer), where 0 0, and produces pro

i i i

i i i

K n

x i c x

c p x fit . units

at most can be allocated for each commodity.

B

Page 46: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 46

1

Allocation can be viewd as a sequenial decision making. Let commodities

1 through have already been produces, consuming 0 .

Define , as the maximal total profit that can be achieved by a

j

i iij c x K

f j y

llocating

unit for producing commodities 1 through . By definition , solves

the problem.

y j f n K

1

The production of units of comodity must statisfy .

Functional equations which can be solved recurrsively result in:

, ,

1, ,

max

max

x B

j jx B

x j c x y

p xf j y

p x f j y c x

1

1

j

j n

Page 47: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 47

• Sequential decision making process.

• Transition occurs from state to state.

• A state is a summary of prior history of the process sufficiently

detailed to enable evolution of current alternatives.

– Sequential decision process evolves from state to state.

– The pair (j,y) is a state in the resource allocation process.

– The elements encoded in a state are called state variables.

• Principle of optimality states that whatever the initial state is and

decisions were, the remaining decisions must constitute an optimal

policy.

Elements of Dynamic Programming

Page 48: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 48

Linear Case: Knapsack Problem

Resource is knapsack of volume .

A unit of commodity occupies volume , yielding profit .

We look for most profitable way to pack the sack.

i i

K

i c p

0 0

0all allocations

0

To allow partially empty sack we introduce commodity 0

with 1 and 0, resulting the problem:

maximize ,

subject to: , 0, integer, 0

n

i ii

n

i i i ii

c p

p x

x c K x x i n

Page 49: Dynamic Programming and Some VLSI CAD Applications

May 2012 Dynamic Programming 49

Linear Case: Knapsack Problem

|

0,1, , is the state and is maximum profit

obtainable from packing volume .

Hence max , 1, , .j

j jj c y

y K f y

y

f y p f y c y K

Let some items have been put into the sack and

volume remains.

Linearity implies that packing the rest is independent

of past.

y