cad for vlsi 1.pptx

  • View
    213

  • Download
    0

Embed Size (px)

Text of cad for vlsi 1.pptx

  • 8/17/2019 cad for vlsi 1.pptx

    1/284

    CAD for IC design

  • 8/17/2019 cad for vlsi 1.pptx

    2/284

    VLSI Design Problem:

    Optimization of design in several aspects Area Minimization* Speed* Power dissipation*

    Design time* Testability*

    Design Methodologies Approac followed to solve te !"SI design

    problem

  • 8/17/2019 cad for vlsi 1.pptx

    3/284

     To consider all parameters in one go d#ring !"SI design process we #se$

    Cost function$ meas#re of !"SI design cost in terms of di%erent parameters

     To design a !"SI circ#it at one go wile at te same time optimizing the cost functions comple&ity is simply too ig

     To #nderstand comple&ity  Two main concepts are elpf#l to deal wit tis comple&ity

    '( )ierarcy and ( Abstraction

    Hierarchy$ sows te str#ct#re of a design at di%erent levels bstraction: ides te lower level details

  • 8/17/2019 cad for vlsi 1.pptx

    4/284

    bstraction e!:

  • 8/17/2019 cad for vlsi 1.pptx

    5/284

    "he Design Domains

    "he beha#ioral domain($ Part of te design +or te wole, is seen as set of blac- bo&es

    $lac% bo!$ relations between o#tp#ts and inp#ts are given wito#t a reference to te implementation of tese relations(

    "he structural domain$ • Circ#it is seen as te composition of s#bcirc#its( • .ac of te s#bcirc#its as a description in te beavioral

    domain or a description in te str#ct#ral domain itself 

    "he physical &or layout ' domain  Te pysical domain gives information on ow te s#bparts tat

    can be seen in te str#ct#ral domain/ are located on te two0 dimensional plane(

  • 8/17/2019 cad for vlsi 1.pptx

    6/284

    Design Methods and "echnologies

    full(custom design: ma&imal freedom ability to determine te sape of every mas- layer for te

    prod#ction of die cip( Semicustom: • smaller searc space • limiting te freedom of te designer

    • sorter design time• semic#stom design implies te #se of gate arrays/ standard cells/ parameterizable modules 

    designing an integrated circuit is

    a se)uence of many actions most of wic can be done by computer tools

  • 8/17/2019 cad for vlsi 1.pptx

    7/284

    *ated arrays • cips tat ave all teir transistors preplaced in reg#lar patterns(

    • designer specify te wiring patterns • gate arrays as described above are mas% programmable

    •  Tere also e&ist so0called +eld(programmable gate arrays +1P2As, • Interconnections can be con3g#red by applying electrical signals

    on some inp#ts(

    Standard Cells • simple logic gates/ 4ip04ops/ etc( • Predesigned and ave been made available to te designer in a

    library • characterization of the cells: determination of teir timing

    beavior is done once by te library developer

    Module *enerators • generators e&ist for tose designs tat ave a reg#lar str#ct#re s#c

    as adders/ m#ltipliers/ and memories( • D#e to te reg#larity of te str#ct#re/ te mod#le can be described

    by one or two parameters(

  • 8/17/2019 cad for vlsi 1.pptx

    8/284

    !"SI design a#tomation tools$ Can be categorized in$

    '( Algoritmic and system design

    ( Str#ct#ral and logic design5( Transistor0level design 6( "ayo#t design 7( !eri3cation 8( Design management

  • 8/17/2019 cad for vlsi 1.pptx

    9/284

    lgorithmic and System Design: • mainly concerned wit te initial algorithm to be implemented in

    ardware and wor-s wit a p#rely beha#ioral description(

    • )ardware description lang#ages +)D"s, are #sed for te p#rpose(• A second application of formal description is te possibility of automatic synthesis

    • syntesizer reads te description and generates an e9#ivalent description of te design at a m#c lower level(

    • High(le#el synthesis: Te syntesis from te algoritmic beavioral level to str#ct#ral descriptions is called ig0level syntesis(

    • Silicon Compiler $ A silicon compiler is a software system tat ta-es a #ser:s speci3cations and a#tomatically generates an integrated

    circ#it +IC,( +initial syntesizer,

    • formal speci3cation does not always need to be in a te&t#al •  Tools available aving capability to con#ert the graphical

    information into a te!tual e9#ivalent +e&pressed in a lang#age li-e !)D", tat can be accepted as inp#t by a syntesis tool(

  • 8/17/2019 cad for vlsi 1.pptx

    10/284

    Hard,are(soft,are co(design • Design for a comple& system will consist of several cips/ some of

    wic are programmable( • Part of te speci3cation is realized in ardware and some of wic in

    software( +ardware0software co0design, •  partitioning of te initial speci3cation re9#ired +di;c#lt to

    a#tomate, •  tools e&ist tat s#pport te designer •  by providing information on te fre9#ency at wic eac part of

    te speci3cation is e&ec#ted(• te parts wit te igest fre9#encies are te most li-ely to be realized in ardware(

    •  Te result of co(design$ • is a pair of descriptions$

    • one of te ardware +e(g( in !)D", tat will contain programmableparts/ and • te oter of te software +e(g( in C,(

  • 8/17/2019 cad for vlsi 1.pptx

    11/284

    Code generation $ Mapping te ig0level descriptions of te software to te low0level

    instr#ctions of te programmable ardware $ CAD problem(

    Hard,are(soft,are co(simulation$ !eri3cation of te correctness of te res#lt of co0design #sing sim#lation(

  • 8/17/2019 cad for vlsi 1.pptx

    12/284

    • Structural and Logic Design • Sometimes te tools migt not be able to cope wit te desired

    beavio#r$ ine;cient syntesis • Designer provides lower level description $Str#ct#ral and "ogic

    Design • designer can #se a schematic editor program$ CAD tool • It allows te interacti#e speci+cation of te bloc-s composing

    a circ#it and teir interconnections by means of a grapical interface(

    • scematics constr#cted in tis way are hierarchical

    • -ole of simulation$ Once te circ#it scematics ave been capt#red by an editor/ it is a common practice to verify te circ#it by means of sim#lation

    • fault simulation$ cec-s weter a set of test vectors or test patterns +inp#t signals #sed for testing, will be able to detect fa#lts ca#sed by imperfections of te fabrication process

    • automatic test(pattern generation$ • te comp#ter searc for te best set of test vectors by #sing a

    tool $ ATP2(

  • 8/17/2019 cad for vlsi 1.pptx

    13/284

    Logic synthesis: 2eneration and optimization of a circ#it at te level of logic gates( tree di%erent types of problems$

    ./ Synthesis of t,o(le#el combinational logic$ •

  • 8/17/2019 cad for vlsi 1.pptx

    14/284

    "iming constraints: • designer so#ld be informed abo#t te ma!imum delay paths • sorter tese delays/ te faster te operation of te circ#it

    • One possibility of 3nding o#t abo#t tese delays is by means ofsimulation • Or by timing analysis tool: comp#te delays tro#g te circ#it

    wito#t performing any sim#lation

  • 8/17/2019 cad for vlsi 1.pptx

    15/284

    "ransistor(le#el Design   "ogic gates are composed of transistors Depending on te acc#racy re9#ired/ transistors can be sim#lated at di0erent le#els

    At te s,itch le#el / transistors are modeled as ideal bidirectional switces and te signals are essentially digital

    At te timing le#el / analog signals are considered/ b#t tetransistors ave simple models +e(g( piecewise linear f#nctions,

    At te circuit le#el / more acc#rate models of te transistors are #sed wic often involve nonlinear di%erential e9#ations for te c#rrents and

    voltages

    more accurate te model/ te more comp#ter time is necessary for sim#lation

  • 8/17/2019 cad for vlsi 1.pptx

    16/284

    Process +f#ll0c#stom Transistor0level design,$

    '( it is te c#stom to e&tract te circ#it from te layo#t data of

    transistor( ( Constr#ct te networ- of transistors/ resistors and

    capacitances( 5( Te e&tracted circ#it can ten be sim#lated at te circ#it or

    switc level(

  • 8/17/2019 cad for vlsi 1.pptx

    17/284

    Layout Design Design actions related to layo#t are very di#erse terefore/ di0erent layout tools/   If one as te layo#t of te s#bbloc-s of a design available/ togeter wit te list of interconnections ten

    '( 1irst/ a position in te plane is assigned to eac s#bbloc-/ trying to minimize te area to be occ#pied by interconnections &placement problem'(

    ( Te ne&t step is to generate te wiring patterns tat realizete correct interconnections +routing problem,(

    goal of placement and r