C2 Part 4: VLSI CAD Tools Problems and Algorithms

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C2 Part 4: VLSI CAD Tools Problems and Algorithms. Marcelo Johann. EAMTA 2006. Outline. THIRD PART Layout Compaction Logic Synthesis, BDDs Technology Mapping Simmulation vs Formal Verification Voltage Drop by Random Walks FOURTH PART High-Level Synthesis - PowerPoint PPT Presentation

Text of C2 Part 4: VLSI CAD Tools Problems and Algorithms

Apresentação do PowerPointC2 Part 4: VLSI CAD Tools
Problems and Algorithms
Outline
FOURTH PART
High-Level Synthesis
Function representations
Truth Tables
For n variables, 2n lines
Formulas
Not Canonical in general, canonical is large
BDDs
Average sized, powerful representation
BDDs
BDD - good ordering
x1 * x2 + x3 * x4 + x5 * x6 + x7 * x8
using a good variable ordering
EAMTA 2006 - Marcelo Johann - C21.*
BDD - bad ordering
x1 * x2 + x3 * x4 + x5 * x6 + x7 * x8
using a bad variable ordering
EAMTA 2006 - Marcelo Johann - C21.*
Random Walks
Random Walks
IR Drop
Random Walk
The Algorithm
Loop until reaching Supply
Make this node a new supply
Print the result
Accuracy
99% of the nodes have less then
Error Margin
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The University of Tokyo
Tokyo Institute of Technology
C2: VLSI CAD Tools