of 84 /84
DESCRIPTION REFERENCE DES BOM OPTION QTY PART NUMBER CRITICAL DRAWING ANGLES 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. DATE APPD ENG DATE APPD CK ECN ZONE REV DO NOT SCALE DRAWING X.XXX X.XX XX DIMENSIONS ARE IN MILLIMETERS THIRD ANGLE PROJECTION D SIZE APPLICABLE NOTED AS MATERIAL/FINISH NONE SCALE DESIGNER MFG APPD DESIGN CK RELEASE QA APPD ENG APPD DRAFTER METRIC OF SHT DRAWING NUMBER TITLE NOTICE OF PROPRIETARY PROPERTY I TO MAINTAIN THE DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT AGREES TO THE FOLLOWING PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY Apple Computer Inc. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 B C D A B C D A REV. DESCRIPTION OF CHANGE 09/19/2006 Schematic / PCB #’s SCHEM,MLB ABBREV=DRAWING TITLE=M59_MLB LAST_MODIFIED=Mon Sep 25 10:45:58 2006 1 1 Table of Contents N/A N/A Date (.csa) Sync Page Contents (MASTER) 42 44 (MASTER) FW PHY Power Supply Page Sync (.csa) Date Contents 051-7150 1 CRITICAL SCH SCHEM,MLB,M59 820-2054 CRITICAL PCB 1 PCBF,MLB,M59 051-7150 SCHEM,MLB 84 1 463525 A.0.0 A PRODUCTION RELEASE 9/19/2006 9/19/2006 (MASTER) 43 45 (MASTER) FireWire Port Power (MASTER) 44 46 (MASTER) FireWire Ports (MASTER) 45 49 (MASTER) Camera Connector (MASTER) 46 52 (MASTER) External USB Connector (MASTER) 47 55 (MASTER) Left I/O Board Connector (MASTER) 48 57 (MASTER) PCI-E Connections (MASTER) 49 58 (MASTER) SMC (MASTER) 50 59 (MASTER) SMC Support (MASTER) 51 60 (MASTER) LPC+ Debug Connector (MASTER) 52 61 (MASTER) Thermal Sensors (MASTER) 53 62 (MASTER) Current & Voltage Sensing (MASTER) 54 63 (MASTER) SPI BOOTROM (MASTER) 55 64 (MASTER) ALS Support (MASTER) 56 65 (MASTER) Fan Connectors (MASTER) 57 66 (MASTER) Sudden Motion Sensor (SMS) (MASTER) 58 67 (MASTER) TPM (MASTER) 59 75 (MASTER) IMVP6 CPU VCore Regulator (MASTER) 60 76 (MASTER) 5V / 1.5V Power Supply 05/07/2006 61 77 M59_MG 2.5V & 1.2V Regulators 05/07/2006 62 78 M59_MG 1.8V Supply 05/07/2006 63 79 M59_MG 3.3V / 1.05V Power Supplies 08/01/2006 64 80 M59_MG 3.3V G3Hot Supply & Power Control 05/07/2006 65 81 M59_MG Power Aliases (MASTER) 66 82 (MASTER) PBus-In,Batt. & 3G Pwr Connectors (MASTER) 67 84 (MASTER) ATI M56 PCI-E (MASTER) 68 85 (MASTER) GPU (M56) Core Supplies (MASTER) 69 86 (MASTER) ATI M56 Core Power (MASTER) 70 87 (MASTER) ATI M56 Frame Buffer I/F 07/25/2006 71 88 M59_MG GPU Straps (MASTER) 72 89 (MASTER) GDDR3 Frame Buffer A (MASTER) 73 90 (MASTER) GDDR3 Frame Buffer B (MASTER) 74 91 (MASTER) ATI M56 GPIO/DVO/Misc (MASTER) 75 93 (MASTER) ATI M56 Video Interfaces 07/25/2006 76 94 M59_MG Internal Display Connectors 07/25/2006 77 97 M59_MG External Display Connector (MASTER) 78 98 (MASTER) M59 Specific Connectors 08/01/2006 79 99 M59_MG LVDS Interface Pull-downs N/A 80 100 N/A Revision History (MASTER) 81 101 (MASTER) Napa Platform Constraints (MASTER) 82 102 (MASTER) More System Constraints (MASTER) 83 103 (MASTER) M59 Spacing & Physical Constraints (MASTER) 84 104 (MASTER) M59 Net Properties 2 2 System Block Diagram N/A N/A 3 3 Power Block Diagram N/A N/A 4 4 BOM Configuration N/A N/A 5 5 Functional / ICT Test N/A N/A 6 6 Signal Aliases/Misc Comps N/A N/A 7 7 CPU 1 OF 2-FSB (MASTER) (MASTER) 8 8 CPU 2 OF 2-PWR/GND (MASTER) (MASTER) 9 9 CPU Decoupling & VID (MASTER) (MASTER) 10 10 CPU MISC1-TEMP SENSOR (MASTER) (MASTER) 11 11 CPU ITP700FLEX DEBUG (MASTER) (MASTER) 12 12 NB CPU Interface (MASTER) (MASTER) 13 13 NB PEG / Video Interfaces (MASTER) (MASTER) 14 14 NB Misc Interfaces (MASTER) (MASTER) 15 15 NB DDR2 Interfaces (MASTER) (MASTER) 16 16 NB Power 1 (MASTER) (MASTER) 17 17 NB Power 2 (MASTER) (MASTER) 18 18 NB Grounds (MASTER) (MASTER) 19 19 NB (GM) Decoupling M59_MG 07/25/2006 20 20 NB Config Straps (MASTER) (MASTER) 21 21 SB: 1 OF 4 (MASTER) (MASTER) 22 22 SB: 2 of 4 (MASTER) (MASTER) 23 23 SB: 3 OF 4 M59_MG 07/25/2006 24 24 SB: 4 OF 4 (MASTER) (MASTER) 25 25 SB Decoupling (MASTER) (MASTER) 26 26 SB Misc (MASTER) (MASTER) 27 27 M1 SMBus Connections (MASTER) (MASTER) 28 28 DDR2 SO-DIMM Connector A (MASTER) (MASTER) 29 29 DDR2 SO-DIMM Connector B (MASTER) (MASTER) 30 30 Memory Active Termination (MASTER) (MASTER) 31 31 Memory Vtt Supply (MASTER) (MASTER) 32 32 DDR2 VRef (MASTER) (MASTER) 33 33 CLOCKS (MASTER) (MASTER) 34 34 Clock Termination M59_MG 05/07/2006 37 35 Mobile Clocking (MASTER) (MASTER) 38 36 PATA Connector (MASTER) (MASTER) 39 37 FireWire Link (TSB83AA22) (MASTER) (MASTER) 40 38 FireWire PHY (TSB83AA22) (MASTER) (MASTER) 41 39 ETHERNET CONTROLLER (MASTER) (MASTER) 42 40 Ethernet Connector (MASTER) (MASTER) 43 41 Yukon Power Control (MASTER) (MASTER) www.laptop-schematics.com

LB 820-2054

Embed Size (px)

Text of LB 820-2054

8

7

6

5

4

3REV

2ZONE ECN DESCRIPTION OF CHANGE

1CK APPD ENG APPD DATE9/19/2006

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

SCHEM,MLBDate (.csa) Date

DATEA 463525 PRODUCTION RELEASE9/19/2006

D(.csa)

D

PageTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Contents1

SyncN/A

PageTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Contents44

Sync(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

8

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

58

(MASTER)

CPU 2 OF 2-PWR/GND9

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

SMC59

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

CPU Decoupling & VID10

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

SMC Support60

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

CPU MISC1-TEMP SENSOR11

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

LPC+ Debug Connector61

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

CPU ITP700FLEX DEBUG12

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Thermal Sensors62

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

NB CPU Interface13

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Current & Voltage Sensing63

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

NB PEG / Video Interfaces14

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

SPI BOOTROM64

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

NB Misc Interfaces15

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

ALS Support65

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

NB DDR2 Interfaces16

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Fan Connectors66

(MASTER)(MASTER)

C

TABLE_TABLEOFCONTENTS_ITEM

NB Power 117

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Sudden Motion Sensor (SMS)67

(MASTER)(MASTER)

C

TABLE_TABLEOFCONTENTS_ITEM

NB Power 218

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

TPM75

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

NB Grounds19

(MASTER)07/25/2006TABLE_TABLEOFCONTENTS_ITEM

IMVP6 CPU VCore Regulator76

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

NB (GM) Decoupling20

M59_MG(MASTER)TABLE_TABLEOFCONTENTS_ITEM

5V / 1.5V Power Supply77

(MASTER)05/07/2006

TABLE_TABLEOFCONTENTS_ITEM

NB Config Straps21

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

2.5V & 1.2V Regulators78

M59_MG05/07/2006

TABLE_TABLEOFCONTENTS_ITEM

09/19/2006

SB: 1 OF 422

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

1.8V Supply79

M59_MG05/07/2006

TABLE_TABLEOFCONTENTS_ITEM

SB: 2 of 423

(MASTER)07/25/2006TABLE_TABLEOFCONTENTS_ITEM

3.3V / 1.05V Power Supplies80

M59_MG08/01/2006

TABLE_TABLEOFCONTENTS_ITEM

SB: 3 OF 424

M59_MG(MASTER)TABLE_TABLEOFCONTENTS_ITEM

3.3V G3Hot Supply & Power Control81

M59_MG05/07/2006

TABLE_TABLEOFCONTENTS_ITEM

SB: 4 OF 425

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Power Aliases82

M59_MG(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

SB Decoupling26

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

PBus-In,Batt. & 3G Pwr Connectors84

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

SB Misc27

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

ATI M56 PCI-E85

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

M1 SMBus Connections28

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

GPU (M56) Core Supplies86

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

DDR2 SO-DIMM Connector A29

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

ATI M56 Core Power87

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

DDR2 SO-DIMM Connector B30

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

ATI M56 Frame Buffer I/F88

(MASTER)07/25/2006

TABLE_TABLEOFCONTENTS_ITEM

Memory Active Termination31

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

GPU Straps89

M59_MG(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

Memory Vtt Supply32

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

GDDR3 Frame Buffer A90

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

DDR2 VRef33

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

GDDR3 Frame Buffer B91

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

B

CLOCKS34

(MASTER)05/07/2006TABLE_TABLEOFCONTENTS_ITEM

ATI M56 GPIO/DVO/Misc93

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

Clock Termination37

M59_MG(MASTER)TABLE_TABLEOFCONTENTS_ITEM

ATI M56 Video Interfaces94

B

(MASTER)07/25/2006

TABLE_TABLEOFCONTENTS_ITEM

Mobile Clocking38

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Internal Display Connectors97

M59_MG07/25/2006

TABLE_TABLEOFCONTENTS_ITEM

PATA Connector39

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

External Display Connector98

M59_MG(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

FireWire Link (TSB83AA22)40

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

M59 Specific Connectors99

(MASTER)08/01/2006

TABLE_TABLEOFCONTENTS_ITEM

FireWire PHY (TSB83AA22)41

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

LVDS Interface Pull-downs100

M59_MGN/A

TABLE_TABLEOFCONTENTS_ITEM

ETHERNET CONTROLLER42

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Revision History101

N/A(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

Ethernet Connector43

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

Napa Platform Constraints102

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

Yukon Power Control

(MASTER)TABLE_TABLEOFCONTENTS_ITEM

More System Constraints103

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

M59 Spacing & Physical Constraints104

(MASTER)(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

M59 Net Properties

(MASTER)

TABLE_TABLEOFCONTENTS_ITEM

DIMENSIONS ARE IN MILLIMETERS

XX

METRICDRAFTER DESIGN CK

Apple Computer Inc.NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

A

X.XX

A

X.XXX ENG APPD ANGLES QA APPD DO NOT SCALE DRAWING RELEASE SCALE NONE DRAWINGTITLE=M59_MLB ABBREV=DRAWINGLAST_MODIFIED=Mon Sep 25 10:45:58 2006

MFG APPD I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART DESIGNER TITLE

SCHEM,MLBSIZE DRAWING NUMBER REV.

THIRD ANGLE PROJECTION

MATERIAL/FINISH NOTED AS APPLICABLE

D

051-7150SHT

A.0.0 1OF

84

8

7

6

5

4

3

2

1

www.laptop-schematics.com

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Table of Contents2

N/AN/A

System Block Diagram3

N/AN/A

Power Block Diagram4

N/AN/ATABLE_TABLEOFCONTENTS_ITEM

BOM Configuration5

N/AN/ATABLE_TABLEOFCONTENTS_ITEM

Functional / ICT Test6

N/AN/ATABLE_TABLEOFCONTENTS_ITEM

Signal Aliases/Misc Comps7

N/A(MASTER)TABLE_TABLEOFCONTENTS_ITEM

CPU 1 OF 2-FSB

(MASTER)

42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

FW PHY Power Supply45

(MASTER)(MASTER)

Schematic / PCB #sPART NUMBER QTY1 1

FireWire Port Power46

(MASTER)(MASTER)

DESCRIPTIONSCHEM,MLB,M59 PCBF,MLB,M59

REFERENCE DESSCH PCB

CRITICALCRITICAL CRITICAL

BOM OPTION

FireWire Ports49

(MASTER)(MASTER)

051-7150 820-2054(MASTER) (MASTER)

Camera Connector52

(MASTER) (MASTER) (MASTER)(MASTER)

External USB Connector55

Left I/O Board Connector57

PCI-E Connections

(MASTER)

8

7

6GDDR3 Frame Buffer 128MB/256MB

5CPU THERMAL SENSOR

4Core Duo (Merom)479 BGA

3ITP700FLEX CPU Debug Connector P.11

2

1

D

Inverter Connector P.76LCD Panel

P.72-73 PWM

P.10 P.7-9

DATI M56PDual-Channel LVDSJ2800

FSB

DDR2 SO-DIMM A"Expansion Slot" Connector (Lower/Outer)

P.76,79 S-Video/CompositeDVI-I/DL Connector w/TV-Out Support

GPUPCIe x16 P.67-71,74-75 CH.A Dual-Channel TMDSLVDS Graphics MUX

P.28J2900

P.77 P.99RJ45 (Ethernet) Connector

1466UFCBGAYukon Gig-E Yukon Power

"Factory Slot" Connector (Upper/Inner)

& REGULATOR

P.29 ENET P.12-20

DDR2 VREFBUFFER

P.30-31

Controller

P.39 DMI x4

P.401394a/b (FireWire)

P.39 P.32 FWPort Power TSB83AA22 FireWire

C

Connectors

Controller

P.44

P.37-38PHY Power

PCIe x1 PCI

C ICH7-MPCIe x1 PCIe x1 Left I/O &

P.43Right USB 2.0 Connector

USB x2

P.43

P.46 SATA HDD/IR/SIL Connector P.78 609 BGA USB

SB

USB USB Azalia (HD-Audio)

Audio Board Connector

P.47 Camera Connector P.45 USB

P.21-26 USB x2

BGeyser KB/TP/BT Connector P.78

BSMBus

ODD Connector P.36CK410 Clock Controller

PATA

66MHZ 16BITS

LPC 33MHZ BootROM P.54SB SMBus

SPI

Power

TPMH8S/2116 P.58

LPC Debug Connector

Supplies P.57-64,69

P.33-34Temperature

P.27

P.51ALS

SMC SMBus

A

Sensors

SMBus x5

SMC

System Block DiagramSYNC_MASTER=N/A SYNC_DATE=N/A

P.55,78SMS

P.52Battery SMBus Connector

P.27Fan Connectors

NOTICE OF PROPRIETARY PROPERTY

A

P.57 PWM/Tach P.49-50Analog Sensors

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

P.66

P.56

P.53APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0

2

84

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7

6

5

4

3

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945GM NB

CH.B

DDR2 SO-DIMM B

DDR2 VTT

8J5500 LIO Flex Connector

7U8000 ENABLE 3.425 PPDCIN_G3H G3Hot 18.5V - 9V (LT3470) 3.425V

6

5

4Q7610 PP5V_S3

3

2

1

PP3V42_G3H 5.0V

D1.5V 5V J8200 ENABLES

SMC_PM_G2_ENABLE PM_SLP_S3_L U7600 PP5V_S5 5V/1.5V LIO Power Connector PPBUS_G3H S5/S0 12.6V - 9V (LTC3728) PGOOD NC SMC_PM_G2_ENABLE IMVP_VR_ON ENABLE IMVP_PWRGD_IN U7900 Q7945 PP3V3_S3 3.3V Q4300 PP3V3_S3AC 3.3V PP1V5_S0 1.5V PM_SLP_S3_LS5V ODD_PWR_EN_L (SB GPIO14) 5.0V PM_SLP_S4_LS5V Q7615 PP5V_S0 5.0V Q3820 PP5V_S0_IDE_ODD 5V

D

CU7530 ENABLES CPU VCore S0 (ISL9504) "IMVP6" PGOOD VR_PWRGOOD_DELAY ENABLE J5500 Inverter Connector PM_SLP_S4_L

3.3V PP3V3_S5 S5 3.3V (ISL6269B) PPVCORE_S0_CPU PGOOD 1.25V - 0.8V RSMRST_PWRGD PM_SLP_S3_L U7950 2.5V PP2V5_S3 S3 (TPS62510) PP2V5_D3C PGOOD 1.05V PP1V05_S0 S0 1.05V (ISL6269B) PGOOD IMVP_PWRGD_IN/ALL_SYS_PWRGD 1.8V PP1V8_S3 S3 1.8V (TPS51117) PGOOD NC (ISL6269B) PGOOD PM_SLP_S3_L NC U3100 ENABLE GPU VCore PPVCORE_D3C_GPU D3C 1.1V - 0.95V PP3V3_S0 3.3V PP3V3_D3C 3.3V Q7947 Q7948 U8500 =GPUVCORE_EN_L ENABLE 1.2V PP1V2_S3 S3 1.2V (LTC3412) PGOOD P1V2R2V5D3C_EN_LS5V NC 1.2V PP1V2_D3C NC PM_SLP_S3BATT U7750 P1V2R2V5D3C_EN_LS5V Q7770 2.5V 2.5V Q7721 PM_SLP_S3_LS5V_L ENABLE PM_SLP_S3BATT U7700 PP2V5_S0 2.5V PM_SLP_S4_LS5V PM_SLP_S3BATT Q7720

C

BENABLE

U7800

B

A

ENABLE Q7845 0.9V (Vtt) PP0V9_S0 S0 0.9V (TPS51100) 1.8V PP1V8_D3C

PM_SLP_S3_LS5V Q4500 Q4501 PPBUS_S5_FWPORT 12.6V - 9V

P3V3D3C_EN_L

Power Block DiagramSYNC_MASTER=N/A SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0

P1V8D3C_EN

FW_PWRCTRL_GATE1

FW_PWRCTRL_GATE2_1/2

3

84

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82.16Ghz BOMsBOM NUMBER630-7849

7BOM NAMEPCBA,2.16GHZ,128VRAM,M59,MBP15

6TABLE_BOMGROUP_HEAD

5

4

3

2

1

BOM OPTIONSTABLE_BOMGROUP_ITEM

EEE_WTE,M59_COMMON,CPU_2_16GHZ,VRAM_SAM128

2.33Ghz BOMsTABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAMEPCBA,2.33GHZ,256VRAM,M59,MBP15

BOM OPTIONSTABLE_BOMGROUP_ITEM

D

630-7851

EEE_WTG,M59_COMMON,CPU_2_33GHZ,VRAM_SAM256

DBOMOPTION GroupsTABLE_BOMGROUP_HEAD

Bar Code Label / EEE #sPART NUMBER826-4393 826-4393

BOM GROUP

BOM OPTIONSTABLE_BOMGROUP_ITEM

QTY1 1

DESCRIPTIONLBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM

REFERENCE DES[EEE:WTE] [EEE:WTG]

CRITICALCRITICAL CRITICAL

BOM OPTIONEEE_WTE

M59_COMMON M59_COMMON1

ALTERNATE,COMMON,M59_COMMON1,M59_COMMON2,M59_COMMON3TABLE_BOMGROUP_ITEM

BOOTROM_FINAL,ENET_LOWPWR_EN,ENETPWR_S3AC,GPU_BB_CTL,D3CPGOOD_3V3TABLE_BOMGROUP_ITEM

EEE_WTG

M59_COMMON2 M59_COMMON3 VRAM_INF128 VRAM_SAM128 VRAM_INF256 VRAM_SAM256 M59_TPM

ITP,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3TABLE_BOMGROUP_ITEM

MEMVTT_EN_PU,RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PUTABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

VRAM_128_SAMSUNGTABLE_BOMGROUP_ITEM

GPU_MEM_256M,GPU_MEM_NOT_SAM,VRAM_256_INFINEONTABLE_BOMGROUP_ITEM

GPU_MEM_256M,VRAM_256_SAMSUNGTABLE_BOMGROUP_ITEM

TPM

extra TPM options: SMC_TPM_GPIO2 SMC_TPM_GPIO1 SMC_TPM_PP

C

Module PartsPART NUMBER333S0354 333S0350 333S0358 333S0351 333S0376 333S0377 337S3391 337S3393 341S1922 341S1923 338S0274 341S1929 338S0269 338S0270 338S0368 341S1789

CDESCRIPTIONIC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

QTY4 4 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1

REFERENCE DESU8900,U8950,U9000,U9050

CRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

BOM OPTIONVRAM_128_SAMSUNG VRAM_256_SAMSUNG VRAM_128_HYNIX VRAM_256_HYNIX VRAM_128_INFINEON VRAM_256_INFINEON

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA

U8900,U8950,U9000,U9050

IC,MDC,B2,PRQ,2.16G,34W,667M,4M,479BGA IC,MDC,B2,PRQ,2.33G,34W,667M,4M,479BGA IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M59 IC,EFI,BOOTROM FINAL (LOCKED),M59

U0700 U0700 U6301 U6301 U5800 U5800 U1200 U4101 U8400 U6700 U4102 U2100 U7530 U3301

CPU_2_16GHZ CPU_2_33GHZ BOOTROM_DEVEL BOOTROM_FINAL SMC_BLANK SMC_PRGRM

IC,SMC,HS8/2116 IC,PRGRM,SMC (NEW),M59 IC,945GM,NORTHBRIDGEIC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

IC,ATI,M56L-LLP,GRPHXCRTL,LF 880BGA

IC, TPM, 28-PIN TSSOP IC,EEPROM,SERIAL IIC,8KBIT,SO8 IC,ICH7M,BGAIC,ISL9504,SYNC REG CTRL,QFN48

TPM

B

341S1797 343S0385 353S1461 359S0109

B

LOW POWER CLOCK SYNTHESIZER, 68PIN

Alternate PartsTABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER128S0060

BOM OPTION

REF DES

COMMENTS:TABLE_ALT_ITEM

128S0094

ALL

330uF,2V,9MOHM,D2TABLE_ALT_ITEM

128S0095

128S0060

ALL

330uF,2V,6MOHM,D2TABLE_ALT_ITEM

128S0081

128S0061

ALL

150uF,6.3V,25MOHM,C2TABLE_ALT_ITEM

376S0448

376S0445

ALL

Si7806ADN for FDM6296TABLE_ALT_ITEM

353S1465

353S1461

ALL

Screened ISL6262 for ISL9504TABLE_ALT_ITEM

152S0287

152S0435

ALL

Alternates for Coilcraft MSS5131TABLE_ALT_ITEM

BOM ConfigurationSYNC_MASTER=N/A SYNC_DATE=N/A

A

128S0093

128S0092

ALL

33uF,16V,D2

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

4

8

7

6

5

4

3

2

1

www.laptop-schematics.com

GPU_MEM_NOT_SAM,VRAM_128_INFINEON

8

7

6

5

4

3

2

1

Functional Test PointsPower Supply NO_TESTsNO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE EXPOSED_VIA IMVP6_RBIAS IMVP6_COMP P5VS5_RUNSS P1V5S0_RUNSS P1V2S3_RT P1V2S3_RUNSS P3V3S5_COMP P3V3S5_FSET P1V05S0_COMP P1V05S0_FSET P3V42G3H_FB GPUVCORE_COMP GPUVCORE_FSET GPUBBP_ADJ GPUBBN_FB GPUVCORE_FB GPUVCORE_FB_RC GPUVCORE_ISEN GPUVCORE_LG GPUVCORE_PHASE GPUVCORE_UG IMVP6_COMP_RC IMVP6_DFB IMVP6_FB IMVP6_OCSET IMVP6_VDIFF IMVP6_VDIFF_RC P1V05S0_BOOT P1V05S0_BOOT_R P1V05S0_COMP P1V05S0_COMP_R P1V05S0_FB P1V05S0_FB_RC P1V05S0_FSET P1V05S0_ISEN P1V05S0_LG P1V05S0_PHASE P1V05S0_UG P1V5S0_RUNSS P3V3S5_BOOT P3V3S5_BOOT_R P3V3S5_COMP P3V3S5_COMP_R P3V3S5_FB P3V3S5_FB_RC P3V3S5_FSET P3V3S5_ISEN P3V3S5_LG P3V3S5_UG CK410_XTAL_IN59C7 59B7

CPU FSB NO_TESTsNO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE EXPOSED_VIA FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTBN_L FSB_DSTBP_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L7C8 7D8 12C4 12D4 84D6 7D6 12C4 84D6 7C8 7D8 12C4 84C6 7D6 12C4 84D6 7D6 12C4 84D6 7B3 7B4 7C3 7C4 12B6 12C6 12D6 84D6 7D6 12B4 84D6 7B3 7B4 7C3 7C4 12B4 84D6 7D6 12B4 84D6 7B3 7B4 7C3 7C4 12B4 84D6 7B3 7B4 7C3 7C4 12B4 84D6 7D6 12B4 84D6 7D6 12B4 84D6 7D6 12B4 84D6 7D8 12A4 12B4 84D6

Fan ConnectorsFUNC_TEST TRUE TRUE TRUE TRUE TRUE =PP5V_S0_FAN_LT FAN_LT_PWM FAN_LT_TACH FAN_RT_PWM FAN_RT_TACH56C7 65A1

Battery Digital ConnectorFUNC_TEST TRUE TRUE TRUE TRUE SMC_BS_ALRT_L =SMBUS_BATT_SCL =SMBUS_BATT_SDA GND_BATT49C5 50B2 66B5 27C1 66B5 27C1 66B5 66B5

TRUE

60C5 64A6 5B7 60C4 64C6 61B6 41C4 61B7 5B7 63C6 5B7 63D6 5C7 63A7 5B7 63B7

56B6 56B6

D

D

56B3 56B3

TRUE TRUE TRUE

Left I/O Data Connector LPC+ Debug ConnectorFUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE =PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RST_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK_PORT80_LPC LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L SV_SET_UP51C4 65D3 51C4 65A1

FUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE =PP1V5_S0_LIO =PPDCIN_G3H_LIO =PP5V_S5_LIO =PP3V42_G3H_LIO PP5V_S0_AUDIO_PWR PP5V_S0_AUDIO GND_AUDIO_PWR GND_AUDIO ACZ_SDATAIN ACZ_SDATAOUT ACZ_BITCLK ACZ_RST_L EXCARD_OC_L LTUSB_OC_L LIO_BATT_ISENSE SMC_SYS_ISET SMC_BATT_ISET SMC_BATT_CHG_EN SMC_BC_ACOK SMC_ADAPTER_EN LIO_P3V3S0_EN_L LIO_DCIN_ISENSE LIO_P3V3S3_EN SMC_BATT_TRICKLE_EN_L SYS_ONEWIRE MINI_CLKREQ_L SMC_EXCARD_CP EXCARD_CLKREQ_L SMC_EXCARD_PWR_EN LIO_PLT_RESET_L ACZ_SYNC =USB2_LT_N =USB2_LT_P =USB2_EXCARD_N =USB2_EXCARD_P =PCIE_EXCARD_R2D_N =PCIE_EXCARD_R2D_P =PCIE_EXCARD_D2R_N =PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N =PCIE_MINI_R2D_N =PCIE_MINI_R2D_P =PCIE_MINI_D2R_N =PCIE_MINI_D2R_P PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N =SMBUS_LIO_SMC_SCL =SMBUS_LIO_SMC_SDA =SMBUS_LIO_SB_SCL =SMBUS_LIO_SB_SDA PCIE_WAKE_L47D6 65C6 47C6 65A8 47C6 65B1 47D6 65D3 47D4 47C4 47A4 47A4

64C3

68C7 68C7

21D4 49D7 51C4 58C6 21D4 49D7 51C4 58C6 21C5 49C7 51C4 58C6 23C8 49C5 51C4 58C6 22B3 49C7 51B4 49B5 50B2 51B4 26B1 51B4 49C1 51B4 49B5 50B2 51B4 49C1 51B4 46B5 49C7 50B2 50B3 51B4 21C4 50D3 51C5 34D6 51C5 21D4 49C7 51C5 58C6 21D4 49C7 51C5 58C6 23C8 49C7 51C5 58C6 23C5 49C5 50A2 51B5 58C6 49B5 50B2 51B5 49C5 50B2 51B5 49C3 50D6 51B5 49C1 51B5 46B5 49C7 50B2 50B3 51B5 23B6 23C3 51B5

68B7 68A3

21C7 47B6 84B4 21C7 47B6 84B4 21C7 47B6 84B4 21C7 47B3 84B4 6C3 47C6 50B3 6D3 47C6 47C6 53C3 47C6 49B5 47B6 49B5 47C6 49D7 50A2 47B6 49C5 50A2 43B7 47C6 49D5 50A2 47B6 64C6 47B6 53C5 47B6 64A6 47B6 49D7 50A2 47C6 49B7 50B2 34A3 47C6 47B6 49B7 50A2 34A3 47C6 47B6 49B7 26C1 47C6 21C7 47B6 84B4 6D3 47C3 6D3 47C3 6C3 47C3 6C3 47C3 47B3 48C6 47B3 48C6 47B3 48B6 47B3 48C6 34C3 47B3 34B3 47B3 47B3 48C6 47B3 48C6 47C3 48C6 47C3 48C6 34D4 47C3 34D4 47C3 27D1 47C3 27D1 47C3 27B6 47C3 27B6 47C3 23C8 39C6 47C3

68C3

68C5

68C5

68C5

68D5

59B8

59B6

59B7

C

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

59C6

C

59C7

59B8

63B5

63B5

5D7 63A7

Left ALS Connector63A7

FUNC_TEST63A7 63A3

5D7 63B7

TRUE TRUE TRUE TRUE

=PP3V3_S3_LTALS ALS_GAIN LTALS_OUT GND

65C3 78C5 6D5 49B5 78C6 55C7 78C6

63A5

63A5

Thermal Diode ConnectorsFUNC_TEST TRUE TRUE TRUE TRUE HSTHMSNS_DX_P HSTHMSNS_DX_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N52C5 52C5 52D5 52C5

63B5

63B5

5D7 60C4 64C6

63D4

63D4

B

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

5D7 63C6

Other Func Test PointsFUNC_TEST TRUE TRUE TRUE =PP1V05_S0_REG PM_SYSRST_L SMC_ONOFF_L53A4 63A2 65D8

B

63C6

63C6

63C2

23C5 26C5 49B7 49C5 50B2 50C6 78C2

5D7 63D6

63C4

63C4

Current Sense CalibrationFUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE ISENSE_CAL_EN =PP5V_S0_ISENSECAL =PP1V8_S3_REG =PP1V5_S0_REG PPVCORE_S0_GPU PPVCORE_S0_CPU49B7 53A8 53A8 65A1

Left I/O Power ConnectorFUNC_TEST TRUE TRUE =PPBUS_G3H_LIO_CONN GND65C3 66C4

63D4

33C6

Request for at least 10 GND test points NOTE: 10 additional GND test points are called out separately in these notes.

62C1 65B8 60C1 65C8

2 TPs per

65D1

GND TRUE 8 TPs, 2 with each of above TP pairs

Camera ConnectorEXPOSED_VIA property indicates that the net

RTC Battery ConnectorFUNC_TEST45C3 65B1 6C3 45C3 6D3 45B3

Functional / ICT TestSYNC_MASTER=N/A SYNC_DATE=N/A26D6

A

FUNC_TEST TRUE =PP5V_S3_CAMERA =USB2_CAMERA_N =USB2_CAMERA_P

should have a via with 10-mil soldermask opening for use as engineering probe point.

TRUE TRUE

PPVBATT_G3C_RTC GND

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

A

Misc EXPOSED_VIA NetsEXPOSED_VIA TRUE TRUE TRUE TRUE DMI_N2S_P DMI_N2S_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N14B4 22D2 14B4 22D2 21B6 34C3 21B6 34C3

Inverter ConnectorFUNC_TEST TRUE TRUE TRUE TRUE TRUE GND_CHASSIS_INVERTER PPBUS_S0_INVERTER GND_INVERTER INVERTER_PWM PP5V_INVERTER_SW6A8 76B5

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

76A5 76A5 76B5

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

5

8

7

6

5

4

3

2

1

www.laptop-schematics.com

68C7

8

7

6

5

4

346B5

2USB Port "A" (Debug Port) = Right USB 2.0 Port=USB2_RT_P =USB2_RT_N =RTUSB_OC_L USB2_RT_PMAKE_BASE=TRUE

1USB_A_P USB_A_N USB_A_OC_L

22C2

46B5

USB2_RT_NMAKE_BASE=TRUE

22C2

NC_CPU_A32_LMAKE_BASE=TRUE NO_TEST=TRUE

TP_CPU_A32_L TP_CPU_A33_L TP_CPU_A34_L TP_CPU_A35_L TP_CPU_A36_L TP_CPU_A37_L TP_CPU_A38_L TP_CPU_A39_L TP_CPU_APM0_L TP_CPU_APM1_L TP_CPU_EXTBREF TP_CPU_HFPLL TP_CPU_SPARE0 TP_CPU_SPARE1 TP_CPU_SPARE2 TP_CPU_SPARE4

7C8

NC_MEM_A_AMAKE_BASE=TRUE NO_TEST=TRUE

MEM_A_A MEM_B_A

28C3

TP_SMC_RSTGATE_LMAKE_BASE=TRUE78C6 49B5 5B2

SMC_RSTGATE_L =RTALS_GAIN

6B7 49D7

46C5

RTUSB_OC_LMAKE_BASE=TRUE

22C4 22D8

NC_CPU_A33_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

NC_MEM_B_AMAKE_BASE=TRUE NO_TEST=TRUE

ALS_GAINMAKE_BASE=TRUE

55C4

29C3

USB Port "B" = Trackpad (Geyser)78C3

NC_CPU_A34_LMAKE_BASE=TRUE NO_TEST=TRUE

=USB_TRACKPAD_P =USB_TRACKPAD_N UNUSED_USB_B_OC_LMAKE_BASE=TRUE

USB_TRACKPAD_PMAKE_BASE=TRUE

USB_B_P USB_B_N USB_B_OC_L

22C2

7B8

TP_NB_CFGMAKE_BASE=TRUE

NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG

14C6 78C3

USB_TRACKPAD_NMAKE_BASE=TRUE

22C2

D

NC_CPU_A35_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

TP_NB_CFGMAKE_BASE=TRUE

D

14C6

22C4 22D8

NC_CPU_A36_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

TP_NB_CFGMAKE_BASE=TRUE

14C6

NC_ENET_CTRL12MAKE_BASE=TRUE NO_TEST=TRUE

ENET_CTRL12 ENET_CTRL25

39C8

USB Port "C" = Left USB 2.0 Port47C3 5B1

NC_CPU_A37_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

TP_NB_CFGMAKE_BASE=TRUE

14C6

NC_ENET_CTRL25MAKE_BASE=TRUE NO_TEST=TRUE

=USB2_LT_P =USB2_LT_N LTUSB_OC_LMAKE_BASE=TRUE

USB2_LT_PMAKE_BASE=TRUE

USB_C_P USB_C_N USB_C_OC_L

22C2

39C8 47C3 5B1

NC_CPU_A38_LMAKE_BASE=TRUE NO_TEST=TRUE

USB2_LT_NMAKE_BASE=TRUE

22C2

7B8

TP_NB_CFGMAKE_BASE=TRUE

14C6 47C6 5C1

22C4 22D8

NC_CPU_A39_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

TP_NB_CFGMAKE_BASE=TRUE

14C6

Ethernet Power Management Support45B3 5A4

USB Port "D" = Camera=USB2_CAMERA_P =USB2_CAMERA_N UNUSED_USB_D_OC_LOUT MAKE_BASE=TRUE

NC_CPU_APM0_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

NOTE: NB_CFG require test access TP_NB_CFGMAKE_BASE=TRUE

USB2_CAMERA_PMAKE_BASE=TRUE

USB_D_P USB_D_N USB_D_OC_L

22C2

NC_CPU_APM1_LMAKE_BASE=TRUE NO_TEST=TRUE

7B8

NB_CFG

ENET_LOWPWR_EN14C6 45C3 5A4

USB2_CAMERA_NMAKE_BASE=TRUE

22C2

NC_CPU_EXTBREFMAKE_BASE=TRUE NO_TEST=TRUE

7B6

22D8 22C4

IN

SB_GPIO30

1

05% 1/16W MF-LF 402

2 39B8 ENET_LOWPWR_EN

22C4 22D8

NC_CPU_HFPLLMAKE_BASE=TRUE NO_TEST=TRUE

TP_SB_SUS_CLK7B8

SUS_CLK_SB

23C3

USB Port "E" = ExpressCard47C3 5B1

MAKE_BASE=TRUE

=USB2_EXCARD_P =USB2_EXCARD_N EXCARD_OC_LMAKE_BASE=TRUE

USB2_EXCARD_PMAKE_BASE=TRUE

USB_E_P USB_E_N USB_E_OC_L

22C2

NC_CPU_SPARE0MAKE_BASE=TRUE NO_TEST=TRUE

7B6

NC_SB_XOR_T5MAKE_BASE=TRUE NO_TEST=TRUE

TP_SB_XOR_T5 TP_SB_XOR_U5 TP_SB_XOR_V3 TP_SB_XOR_V4 TP_SB_XOR_W3

21C6

NOTE: BOM options "USB_G_OC_PU" and "ENET_LOWPWR_EN" are mutually-exclusive.

47C3 5B1

USB2_EXCARD_NMAKE_BASE=TRUE

22C2

NC_CPU_SPARE1MAKE_BASE=TRUE NO_TEST=TRUE

7B6

NC_SB_XOR_U5MAKE_BASE=TRUE NO_TEST=TRUE

50B3 47C6 5C1 21C6

22C4 22D8

NC_CPU_SPARE2MAKE_BASE=TRUE NO_TEST=TRUE

7B6

NC_SB_XOR_V3MAKE_BASE=TRUE NO_TEST=TRUE

USB Port "F" = IR Receiver21C6 78B4 21C6

NC_CPU_SPARE4MAKE_BASE=TRUE NO_TEST=TRUE

=USB_IR_P =USB_IR_N

USB_IR_PMAKE_BASE=TRUE

USB_F_P USB_F_N

22C2

7B6

NC_SB_XOR_V4MAKE_BASE=TRUE NO_TEST=TRUE

Inverter PWM Reset AliasM59_INVERTER_PLT_RST_L =INVERTER_PWM_PLT_RST_L

78B4

USB_IR_NMAKE_BASE=TRUE

22C2

C

NC_SB_XOR_W3MAKE_BASE=TRUE NO_TEST=TRUE

21C6

USB Port "G" = Bluetooth (M13L)26C1 76A8 78C2

CUSB_G_P USB_G_N22C2 22C2

=USB_BT_P =USB_BT_N

USB_BT_PMAKE_BASE=TRUE

78C2

USB_BT_NMAKE_BASE=TRUE

FireWire Aliases42C4

USB Port "H" = Reserved=PP3V3_FWPHY =PP3V3_FWPHY_CORE =PP3V3_FWLATEVG =PP3V3_FWLATEVG_ACTIVE =PP1V95_FWPHY =PP1V8_FWPHY_OSC =SMC_FWRSTGATE_L =FW_PCI_IDSEL =FW_PCI_GNT_L =FW_PCI_REQ_L22C2 6C1 38D7 44B8 42C4 44A8 43A7 22C2 6C1

=PP3V3_FWPHY_REG

PP3V3_FWPHYVOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

TP_USB_H_PMAKE_BASE=TRUE

TP_USB_H_P TP_USB_H_N

6C2 22C2

TP_USB_H_NMAKE_BASE=TRUE

6C2 22C2

42C1

=PP1V95_FWPHY_CORE_LDO

PP1V95_FWPHYVOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE49D7 6D4

38D5

38B2

SMC_RSTGATE_LMAKE_BASE=TRUE

37A8

37C6 22A7

PCI_ADMAKE_BASE=TRUE

37B7

22B6

PCI_GNT3_LMAKE_BASE=TRUE

37D3

Thermal Module HolesAdd 2 blind vias per hole per side to GND79B8

LVDS pulldown aliases=LVDS_PD_U_CLK_N =LVDS_PD_U_CLK_P =LVDS_PD_U_DATA_P =LVDS_PD_U_DATA_N =LVDS_PD_U_DATA_P =LVDS_PD_U_DATA_N =LVDS_PD_U_DATA_P =LVDS_PD_U_DATA_N =LVDS_PD_L_CLK_N =LVDS_PD_L_CLK_P =LVDS_PD_L_DATA_P =LVDS_PD_L_DATA_N =LVDS_PD_L_DATA_P =LVDS_PD_L_DATA_N =LVDS_PD_L_DATA_P =LVDS_PD_L_DATA_N LVDS_U_CLK_CONN_NMAKE_BASE=TRUE79B8 76B2 76D7 79C1

26D2 22B6

PCI_REQ3_LMAKE_BASE=TRUE

37D3

Top CPU TM Hole

Top GPU Right TM Hole79C8

Chassis GNDsGND_CHASSIS_RTUSB

LVDS_U_CLK_CONN_PMAKE_BASE=TRUE

76B2 76D7 79C1

LVDS_U_DATA_CONN_PMAKE_BASE=TRUE

76C2 76D7 79D1

B

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

=GND_CHASSIS_RTUSB =GND_CHASSIS_FW_PORT2L =GND_CHASSIS_FW_EMI_R

79C8 46B2 44A1 44A3 79B8

LVDS_U_DATA_CONN_NMAKE_BASE=TRUE

76C2 76D7 79D1

LVDS_U_DATA_CONN_PMAKE_BASE=TRUE

76C2 76D7 79C1

B

Left CPU TM Hole

Right CPU TM Hole

Bottom Left GPU TM Hole

79B8

LVDS_U_DATA_CONN_NMAKE_BASE=TRUE

76C2 76D7 79C1

79B8

LVDS_U_DATA_CONN_PMAKE_BASE=TRUE

76B2 76D7 79C1

GND_CHASSIS_DVI_TOPMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE 0.01UF

79B8

LVDS_U_DATA_CONN_NMAKE_BASE=TRUE

76C2 76D7 79D1

C0600

1

=GND_CHASSIS_DVI2 =GND_CHASSIS_DVI4

77A5 79C8 77A3 79C8

LVDS_L_CLK_CONN_NMAKE_BASE=TRUE

76C2 76D7 79C1

10% 50V 2 X7R 402

LVDS_L_CLK_CONN_PMAKE_BASE=TRUE

76C2 76D7 79C1

Frame holes=GND_CHASSIS_DVI1 =GND_CHASSIS_DVI3 =GND_CHASSIS_DVI5

79D8

LVDS_L_DATA_CONN_PMAKE_BASE=TRUE

76C2 76D7 79C1

GND_CHASSIS_DVI_BOTMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE77B5 77A2 77A2

ZT0615HOLE-VIA-P5RP251 GND_CHASSIS_RIGHT_FAN_HOLEMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

79D8

LVDS_L_DATA_CONN_NMAKE_BASE=TRUE

76C2 76D7 79C1

79D8

LVDS_L_DATA_CONN_PMAKE_BASE=TRUE

76C2 76D7 79C1

1

R06010

79C8

LVDS_L_DATA_CONN_NMAKE_BASE=TRUE

76C2 76D7 79C1

5% 1/16W MF-LF 2 402

ZT0614

HOLE-VIA-P5RP251 GND_CHASSIS_RIGHT_FAN_NOTCHMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

79C8

LVDS_L_DATA_CONN_PMAKE_BASE=TRUE

76C2 76D7 79C1

79C8

LVDS_L_DATA_CONN_NMAKE_BASE=TRUE

76C2 76D7 79C1

GND_CHASSIS_ENETMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

ZT0613=GND_CHASSIS_ENET =GND_CHASSIS_FW_PORT1 =GND_CHASSIS_FW_PORT2U40B2 44C1 44A1

HOLE-VIA-P5RP25

RAM door (Torx) holesZT0630HOLE-VIA-P5RP251 GND_CHASSIS_RAMDOOR_HOLE_0MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

1 GND_CHASSIS_DIMM_NOTCHMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

ZT0612

HOLE-VIA-P5RP251GND_CHASSIS_LIOFLEX_HOLEMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

Chassis connection to be made at the mounting hole east of the LVDS connector

Signal Aliases/Misc Comps1 1

ZT0602

A

HOLE-VIA-P5RP251

1

GND_CHASSIS_LVDS1MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

C06300.01UF

ZT0611

C06150.01UF

SYNC_MASTER=N/A

SYNC_DATE=N/A

HOLE-VIA-P5RP251GND_CHASSIS_BATTCONN_HOLEMIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

C06120.01UF1

C06020.01UF

10% 50V X7R 2 402

=GND_CHASSIS_LCD1 =GND_CHASSIS_LCD2 =GND_CHASSIS_LCD3 =GND_CHASSIS_LCD4

76D2 76D3 76C3 76B2

10% 50V 2 X7R 402

1

C06110.01UF

10% 50V 2 X7R 402

10% 2 50V X7R 402

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

A

C06140.01UF

ZT0631HOLE-VIA-P5RP251 GND_CHASSIS_RAMDOOR_HOLE_1MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

ZT0610HOLE-VIA-P5RP251GND_CHASSIS_LNDACARD_HOLE 1

C06310.01UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V 1

10% 50V 2 X7R 402 1

10% 50V 2 X7R 402

1

5A4

GND_CHASSIS_INVERTER =GND_CHASSIS_INVERTER =GND_CHASSIS_CAMERA76A6 45B5 45C5

C06100.01UF

C06130.01UF

SH0600OG-503040SHLD-SM-LF

2 3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

10% 2 50V X7R 402

SIZE

DRAWING NUMBER

REV.

10% 50V 2 X7R 402

10% 50V 2 X7R 402

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

6

8

7

6

5

4

3

2

1

www.laptop-schematics.com

R0600

884D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5

7OMIT

6U0700YONAH CPUBGA(1 OF 4)ADS* BNR* BPRI* DEFER* DRDY* DBSY* H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C784D6 12C4 5D5 84D6 12C4 5D5 84D6

5=PP1V05_S0_CPUIO IO IO IO IO IO IO7B5 7B6 7D5 8C7 9B7 11B3 11C5 65D6

4

3

2

1

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

ADDR GROUP0

D

84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12D4 5D5 84D6 12C4 5D5 84C6 12C4 5D5

FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L CPU_A20M_L CPU_FERR_L CPU_IGNNE_L CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

J4 A3* L4 A4* M3 A5* K5 A6* M1 A7* N2 A8* J1 A9* N3 A10* P5 A11* P2 A12* L1 A13* P4 A14* P1 A15* R1 A16* L2 ADSTB0* K3 REQ0* H2 REQ1* K2 REQ2* J3 REQ3* L5 REQ4* Y2 A17* U5 A18* R3 A19*

FSB_ADS_L FSB_BNR_L 12C4 FSB_BPRI_L FSB_DEFER_L 5D5 FSB_DRDY_L 5D5 FSB_DBSY_L FSB_BREQ0_L

1

R070254.9

84D6 12B4 84D6 12B4 84D6 12B4

1% 1/16W MF-LF 2 402

BR0*

84D6 12C4 5D5

CONTROL

IERR* INIT* LOCK* RESET* RS0* RS1* RS2* TRDY* HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* PROCHOT* THERMDA THERMDC

84C6

FSB_IERR_L 21C4 CPU_INIT_L84C6

IN IO IN IN IN IN IN IO IO

PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY

D

84D6 12B4 5D5

FSB_LOCK_L

84D6 12C4 11B5 84D6 12A4 84D6 12A4 84D6 84D6

84D6 12B4 5D5 84D6 12B4 5D5 84D6 12A4 5D5 84D6 12A4 5D5 84D6 12A4 5D5

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IN OUT IN IN IN IN IN6D7

FSB_CPURST_L FSB_RS_L FSB_RS_L 12A4 FSB_RS_L 12A4 FSB_TRDY_L FSB_HIT_L 5D5 FSB_HITM_L

=PP1V05_S0_CPU

7B5 7B6 7D5 8C7 9B7 11B3 11C5 65D6

84D6 12B4 5D5 84D6 12B4

1

84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5 84D6 12C4 5D5

IO IO IO

U070084D6 12D6 5D5

ADDR GROUP1

W6 A20* U4 A21* Y5 A22* U2 A23* R4 A24* T5 A25* T3 A26* W3 A27* W5 A28* Y4 A29* W2 A30* Y1 A31* V4 ADSTB1* A6 A20M* A5 FERR* C4 IGNNE* D5 STPCLK* C6 LINT0 B4 LINT1 A3 SMI* AA1 RSVD1 AA4 RSVD2 AB2 RSVD3 AA3 RSVD4 M4 RSVD5 N5 RSVD6 T2 RSVD7 V3 RSVD8 B2 RSVD9 C3 RSVD10 B25 RSVD11

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

IO IN IN OUT IN IN OUT

84D6 12D6 5D5 84D6 12D6 5D5

1

R070468

84D6 12D6 5D5 84D6 12D6 5D5 84D6 12D6 5D5 84D6 12D6 5D5 84D6 12D6 5D5 84D6 12D6 5D5

DATA GRP0

DATA GRP2

5% 1/16W MF-LF 2 402 CPU_PROCHOT_L TO SMC AND CPU VR TO INFORM CPU IS HOT

THERM

50D3 50C1

C

84D6 12C4 5D5 84C6 12C4 5D5

CPU_PROCHOT_L 10B6 CPU_THERMD_P 10B6 CPU_THERMD_N PM_THRMTRIP_L

OUT OUT OUT OUT

84D6 12D6 5D5 84D6 12D6 5D5 84D6 12D6 5D5 84D6 12D6 5D5 84D6 12C6 5D5 84D6 12C6 5D5

THERMTRIP*

50C1 21C2 14B6

84C6 21C4 21C2 84C6 21C4

84C6 21C4 84C6 21C4 84C6 21C4 84C6 21C4

BCLK0 BCLK1

A22 A21

FSB_CLK_CPU_P 34D3 FSB_CLK_CPU_N34D3

IN IN

PM_THRMTRIP# SHOULD CONNECT TO ICH7-M AND GMCH WITHOUT T-ING (NO STUB)

HCLK

84D6 12C6 5D5 84D6 12B4 5D5 84D6 12B4 5D5 84D6 12B4 5D5

FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTBN_L FSB_DSTBP_L FSB_DINV_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTBN_L FSB_DSTBP_L FSB_DINV_L

E22 D0* F24 D1* E26 D2* H22 D3* F23 D4* G25 D5* E25 D6* E23 D7* K24 D8* G24 D9* J24 D10* J23 D11* H26 D12* F26 D13* K22 D14* H25 D15* H23 DSTBN0* G22 DSTBP0* J26 DINV0* N22 D16* K25 D17* P26 D18* R23 D19* L25 D20* L22 D21* L23 D22* M23 D23* P25 D24* P22 D25* P23 D26* T24 D27* R24 D28* L26 D29* T25 D30* N24 D31* M24 DSTBN1* N25 DSTBP1* M26 DINV1* AD26 GTLREF A2 NC C26 TEST1 D25 TEST2 B22 BSEL0 B23 BSEL1 C21 BSEL2

YONAH CPUBGA(2 OF 4)

D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2* D48* D49* D50* D51* D52* D53*

AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE6

84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 84D6 12C6 84D6 12C6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B4 84D6 12B4 84D6 12B4

FSB_D_L FSB_D_L FSB_D_L FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_DSTBN_L 5D5 FSB_DSTBP_L 5D5 FSB_DINV_L FSB_D_L FSB_D_L FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_D_L 5D5 FSB_DSTBN_L 5D5 FSB_DSTBP_L 5D5 FSB_DINV_L

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

C

84D6 12C6 5D5 84D6 12C6 5D5

DATA GRP1

DATA GRP3

TP_CPU_A32_L 6D7 TP_CPU_A33_L 6D7 TP_CPU_A34_L 6D7 TP_CPU_A35_L 6D7 TP_CPU_A36_L 6D7 TP_CPU_A37_L 6D7 TP_CPU_A38_L 6D7 TP_CPU_A39_L 6D7 TP_CPU_APM0_L 6C7 TP_CPU_APM1_L6C7

RESERVED

RSVD12

T22

TP_CPU_EXTBREF TP_CPU_SPARE0 TP_CPU_SPARE1 TP_CPU_SPARE2 TP_CPU_SPARE3 TP_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6 TP_CPU_SPARE7

84D6 12C6 5D5 6C7 84D6 12C6 5D5 84D6 12C6 5D5

84D6 12B6 5D5 84D6 12B6 5D5 84D6 12B6 5D5 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B6 84D6 12B4 84D6 12B4 84D6 12B4

RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

D2 F6 D3 C1 AF1 D22 C23 C24

6C7 6C7 6C7

84D6 12C6 5D5 84D6 12C6 5D5

SPARE[7-0],HFPLL: ROUTE TO TP VIA AND PLACE GND VIA W/IN 1000 MILS

84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 5D5 84D6 12C6 5D5

D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0

6C7

LAYOUT NOTE: COMP0,2 CONNECT WITH TRACE LENGTH SHORTER COMP1,3 CONNECT WITH TRACE LENGTH SHORTER

ZO=27.4OHM, MAKE THAN 0.5". ZO=55OHM, MAKE THAN 0.5".

TP_CPU_HFPLL

R07161

65D6 11C5 11B3 9B7 8C7 7D5 7B6

=PP1V05_S0_CPU1

84D6 12C6 5D5 84D6 12C6 5D5

27.4 2402

R07051K

84D6 12C6 5D5 84D6 12B4 5D5 84D6 12B4 5D5 84D6 12B4 5D5

R07171

54.9 21%

BR072011B3 7C6

=PP1V05_S0_CPU

7B5 7D5 8C7 9B7 11B3 11C5 65D6

1% 1/16W MF-LF 2 40284C6

402

R07181

B

CPU_GTLREFLAYOUT NOTE: 0.5" MAX LENGTH

XDP_TMS

1

54.9 21% 402

1

R07062.0K

MISC

COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*

CPU_TEST1 CPU_TEST2

1% 1/16W MF-LF 2 40234C6 34B6 34B6

CPU_COMP 84C6 CPU_COMP 84C6 CPU_COMP 84C6 CPU_COMP84C6 59C7 21C4 84C6 84D6 84C6

27.4 2

R07191IN IN IN IN IN IN

54.9 21% 402

R072111B3 7C6

OUT OUT OUT

XDP_TDI

1

54.9 21% 402

CPU_BSEL CPU_BSEL CPU_BSEL NOSTUFF

R0730 R072211B3 7C6

CPU_DPRSTP_L 21C4 CPU_DPSLP_L 12B4 FSB_DPWR_L 21C4 CPU_PWRGD 12A4 FSB_SLPCPU_L 59C7 CPU_PSI_L

1

0

2

XDP_TCK

1

54.9 21% 402

402 1

NOSTUFF1

R071251

R07071K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

CPU 1 OF 2-FSB

A

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

7

8

7

6

5

4

3

2

1

www.laptop-schematics.com

XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 84C6 11B3 XDP_BPM_L 11B3 7A8 XDP_TCK 11B3 7B8 XDP_TDI 11B5 XDP_TDO 11B3 7B8 XDP_TMS 11B3 XDP_TRST_L 26C6 11B4 XDP_DBRESET_L84C6 11B3

R070354.9OMIT

XDP/ITP SIGNALS

IO IO

1% 1/16W MF-LF 2 402

8

7

6

5

4OMITA4 VSS_1 A8 VSS_2 A11 VSS_3

3U0700 VSS_82 VSS_83YONAH CPUBGA(4 OF 4)P6 P21 VSS_84 P24 VSS_85 R2 VSS_86 R5 VSS_87 R22 VSS_88 R25 VSS_89 T1 VSS_90 T4 VSS_91 T23 VSS_92 T26 VSS_93 U3 VSS_94 U6 VSS_95 U21 VSS_96 U24 VSS_97 V2 VSS_98 V5 VSS_99 V22 VSS_100 V25 VSS_101 W1 VSS_102 W4 VSS_103 W23 VSS_104 W26 VSS_105 Y3 VSS_106 Y6 VSS_107 Y21 VSS_108 Y24 VSS_109 AA2 VSS_110 AA5 VSS_111 AA8 VSS_112 AA11 VSS_113 AA14 VSS_114 AA16 VSS_115 AA19 VSS_116 AA22 VSS_117 AA25 VSS_118 AB1 VSS_119 AB4 VSS_120 AB8 VSS_121 AB11 VSS_122 AB13 VSS_123 AB16 VSS_124 AB19 VSS_125 AB23 VSS_126 AB26 VSS_127 AC3 VSS_128 AC6 VSS_129 AC8 VSS_130 AC11 VSS_131 AC14 VSS_132 AC16 VSS_133 AC19 VSS_134 AC21 VSS_135 AC24 VSS_136 AD2 VSS_137 AD5 VSS_138 AD8 VSS_139 AD11 VSS_140 AD13 VSS_141 AD16 VSS_142 AD19 VSS_143 AD22 VSS_144 AD25 VSS_145 AE1 VSS_146 AE4 VSS_147 AE8 VSS_148 AE11 VSS_149 AE14 VSS_150 AE16 VSS_151 AE19 VSS_152 AE23 VSS_153 AE26 VSS_154 AF3 VSS_155 AF6 VSS_156 AF8 VSS_157 AF11 VSS_158 AF13 VSS_159 AF16 VSS_160 AF19 VSS_161 AF21 VSS_162 AF24

2

1

=PPVCORE_S0_CPUOMITA7 VCC_1 A9 VCC_2 A10 VCC_3

8B5 9D7 53A6 53D7 65D1

(CPU CORE POWER)

U0700YONAH CPUBGA(3 OF 4)

VCC_68 AB20 VCC_69 AB7 VCC_70 AC7 VCC_71 AC9 VCC_72 AC12 VCC_73 AC13 VCC_74 AC15 VCC_75 AC17 VCC_76 AC18 VCC_77 AD7 VCC_78 AD9 VCC_79 AD10 VCC_80 AD12 VCC_81 AD14 VCC_82 AD15 VCC_83 AD17 VCC_84 AD18 VCC_85 AE9 VCC_86 AE10 VCC_87 AE12 VCC_88 AE13 VCC_89 AE15 VCC_90 AE17 VCC_91 AE18 VCC_92 AE20 VCC_93 AF9 VCC_94 AF10 VCC_95 AF12 VCC_96 AF14 VCC_97 AF15 VCC_98 AF17

A14 VSS_4 A16 VSS_5 A19 VSS_6 A23 VSS_7 A26 VSS_8 B6 VSS_9 B8 VSS_10 B11 VSS_11 B13 VSS_12 B16 VSS_13 B19 VSS_14 B21 VSS_15 B24 VSS_16 C5 VSS_17 C8 VSS_18 C11 VSS_19 C14 VSS_20 C16 VSS_21 C19 VSS_22 C2 VSS_23 C22 VSS_24 C25 VSS_25 D1 VSS_26 D4 VSS_27 D8 VSS_28 D11 VSS_29 D13 VSS_30 D16 VSS_31 D19 VSS_32 D23 VSS_33 D26 VSS_34 E3 VSS_35 E6 VSS_36 E8 VSS_37 E11 VSS_38 E14 VSS_39 E16 VSS_40 E19 VSS_41 E21 VSS_42 E24 VSS_43 F5 VSS_44 F8 VSS_45 F11 VSS_46 F13 VSS_47 F16 VSS_48 F19 VSS_49 F2 VSS_50 F22 VSS_51 F25 VSS_52 G4 VSS_53 G1 VSS_54 G23 VSS_55

D

A12 VCC_4 A13 VCC_5 A15 VCC_6 A17 VCC_7 A18 VCC_8 A20 VCC_9 B7 VCC_10 B9 VCC_11 B10 VCC_12 B12 VCC_13 B14 VCC_14 B15 VCC_15 B17 VCC_16 B18 VCC_17 B20 VCC_18 C9 VCC_19 C10 VCC_20 C12 VCC_21 C13 VCC_22 C15 VCC_23 C17 VCC_24 C18 VCC_25 D9 VCC_26 D10 VCC_27 D12 VCC_28 D14 VCC_29 D15 VCC_30 D17 VCC_31 D18 VCC_32 E7 VCC_33 E9 VCC_34 E10 VCC_35 E12 VCC_36 E13 VCC_37 E15 VCC_38 E17 VCC_39 E18 VCC_40 E20 VCC_41 F7 VCC_42 F9 VCC_43 F10 VCC_44 F12 VCC_45 F14 VCC_46 F15 VCC_47 F17 VCC_48 F18 VCC_49 F20 VCC_50 AA7 VCC_51 AA9 VCC_52 AA10 VCC_53 AA12 VCC_54 AA13 VCC_55 AA15 VCC_56 AA17 VCC_57 AA18 VCC_58 AA20 VCC_59 AB9 VCC_60 AC10 VCC_61 AB10 VCC_62 AB12 VCC_63 AB14 VCC_64 AB15 VCC_65 AB17 VCC_66 AB18 VCC_67

D

C

VCC_99 AF18 VCC_100 AF20 VCCP_1 V6 VCCP_2 G21 VCCP_3 J6 VCCP_4 K6 VCCP_5 M6 VCCP_6 J21 VCCP_7 K21 VCCP_8 M21 VCCP_9 N21 VCCP_10 N6 VCCP_11 R21 VCCP_12 R6 VCCP_13 T21 VCCP_14 T6 VCCP_15 V21 VCCP_16 W21

C

=PP1V05_S0_CPU

7B5 7B6 7D5 9B7 11B3 11C5 65D6

(CPU IO POWER 1.05V)

VCCA=1.5 ONLYVCCA B26

=PP1V5_S0_CPU CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VIDOUT OUT OUT OUT OUT OUT OUT

9B7 65C6

G26 VSS_56 H3 VSS_57 H6 VSS_58 H21 VSS_59 H24 VSS_60 J2 VSS_61 J5 VSS_62 J22 VSS_63 J25 VSS_64 K1 VSS_65 K4 VSS_66 K23 VSS_67 K26 VSS_68 L3 VSS_6959B1 84B6

(CPU INTERNAL PLL POWER 1.5V)VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE29C2 84B6 9C2 84B6 9C2 84B6 9C2 84B6 9C2 84B6 9C2 84B6 9C2 84B6

B

VID FOR CPU POWER SUPPLY IF NO USE, NEED PULL-UP OR PULL-DOWN

=PPVCORE_S0_CPU1

8D7 9D7 53A6 53D7 65D1

R08021001% 1/16W MF-LF

B

2 402

VCCSENSE AF7 VSSSENSE AE7

CPU_VCCSENSE_P CPU_VCCSENSE_N

OUT

OUT

59A1 84B6

1 LAYOUT NOTE: CONNECT R0803 TO TP_VSSSENSE WITH NO STUB. LAYOUT NOTE: VCCSENSE AND VSSSENSE LINES SHOULD BE OF EQUAL LENGTH

R0803100

1% 1/16W MF-LF 2 402

LAYOUT NOTE: CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

LAYOUT NOTE: PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENCTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE AT THE LOCATION WHERE THE TWO 54.9 OHM RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE

L6 VSS_70 L21 VSS_71 L24 VSS_72 M2 VSS_73 M5 VSS_74 M22 VSS_75 M25 VSS_76 N1 VSS_77 N4 VSS_78 N23 VSS_79 N26 VSS_80 P3 VSS_81

CPU 2 OF 2-PWR/GND

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

8

8

7

6

5

4

3

2

1

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8

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5

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3

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1

DCPU VCORE HF AND BULK DECOUPLING

D

65D1 53D7 53A6 8D7 8B5

=PPVCORE_S0_CPU

4x 330uF. 20x 22uF 08051

C090022UF20% 6.3V CERM 805

1

C090122UF20% 6.3V CERM 805

1

C090222UF20% 6.3V CERM 805

1

C090322UF20% 6.3V CERM 805

1

C090422UF20% 6.3V CERM 805

1

C090522UF20% 6.3V CERM 805

1

C090622UF20% 6.3V CERM 805

1

C090722UF20% 6.3V CERM 805

1

C090822UF20% 6.3V CERM 805

1

C090922UF20% 6.3V CERM 805

CPU VCORE VID ConnectionsResistors to allow for override of CPU VID Will probably be removed before production

2

2

2

2

2

2

2

2

2

2

RP099005%1

C091022UF20% 6.3V CERM 805

1

C091122UF20% 6.3V CERM 805

1

C091222UF20% 6.3V CERM 805

1

C091322UF20% 6.3V CERM 805

1

C091422UF20% 6.3V CERM 805

1

C091522UF20% 6.3V CERM 805

1

C091622UF20% 6.3V CERM 805

1

C091722UF20% 6.3V CERM 805

1

C091822UF20% 6.3V CERM 805

1

C091922UF20% 6.3V CERM 805

84B6 8B7 84B6 8B7 84B6 8B7 84B6 8B7

2

2

2

2

2

2

2

2

2

2

CPU_VID CPU_VID CPU_VID CPU_VID

1 2 3 4 1/16W SM-LF

8 7 6 5

IMVP6_VID IMVP6_VID IMVP6_VID IMVP6_VID

59C7 59C7 59C7 59C7

CRITICAL1

CRITICAL1

CRITICAL1

CRITICAL1

C0950330UF20% POLY D2T

C0952330UF20% POLY D2T

C0953330UF20% POLY D2T

C0954330UF20% POLY D2T

RP099105%84B6 8B7 84B6 8B7 84B6 8B7

C

3

2 2.5V

3 2 2.5V

3 2 2.5V

3

2 2.5V

CPU_VID CPU_VID CPU_VID NC

1 2 3 4 1/16W SM-LF

8 7 6 5

IMVP6_VID IMVP6_VID IMVP6_VID NC

59C7 59C7 59C7

C

VCCA (CPU AVdd) Decoupling65C6 8B7

=PP1V5_S0_CPU

1x 10uF, 1x 0.01uFC098010uF20% 6.3V X5R 603 2 2 1 1

C09810.01UF20% 16V CERM 402

B

B

VCCP (CPU I/O) Decoupling65D6 11C5 11B3 8C7 7D5 7B6 7B5

=PP1V05_S0_CPU

1x 470uF, 6x 0.1uF 0402C0935470uF20% 2.5V TANT D2T2 3 1

1

C09360.1UF20% 10V CERM 402

1

C09370.1UF20% 10V CERM 402

1

C09380.1UF20% 10V CERM 402

1

C09390.1UF20% 10V CERM 402

1

C09400.1UF20% 10V CERM 402

1

C09410.1UF20% 10V CERM 402

2

2

2

2

2

2

CRITICAL

NOTE: This cap is shared between CPU and NB

CPU Decoupling & VID

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

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D

D

CPU ZONE THERMAL SENSOR65B3 =PP3V3_S0_THRM_SNR

C

C1002LAYOUT NOTE: ADD GND GUARD TRACE FOR CPU_THERMD_P AND CPU_THERMD_N LAYOUT NOTE: ROUTE CPU_THERMD_P AND CPU_THERMD_N ON SAME LAYER. 10 MIL TRACE 10 MIL SPACING

1

0.1UF10% 16V X5R 402

CR1006110K5% 1/16W MF-LF 402 2

2

1

R100510K5% 1/16W MF-LF

2 402

1

VDD

R1001OUT7C6

CPU_THERMD_P

1

4991% 1/16W MF-LF 402

2

THRM_CPU_DX_P THRM_CPU_DX_N1

2 D+ 3 D-

U1001TMP401 MSOPCRITICAL GND 5

ALERT*/ 6 THRM_ALERT_L THM2* THM* 4 THRM_ALERT SCLK 8 SDATA 7

27D1

SMB_THRM_CLK

IO

(TO CPU INTERNAL THERMAL DIODE)

(TC0D)7C6

C10010.001UF10% 50V CERM 402

27D1

SMB_THRM_DATA

IO

R1002IN

CPU_THERMD_N

1

4991% 1/16W MF-LF 402

2

2

PLACE U1001 NEAR THE U1200

B

B

CPU MISC1-TEMP SENSOR

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

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D

D

CPU ITP700FLEX DEBUG SUPPORTC=PP1V05_S0_CPUITP1

Note: This connection to 1V5_S0 is to steal this mounting pad to add to the 1.5V S0 shape and to provide better feeding of the 1.5V NB rail through its current sense resistor65C6

C

=PP1V5_S0_ITPMOUNTITPCONN

CRITICAL

65D6 11B3 9B7 8C7 7D5 7B6 7B5

R1101 1R110354.9 54.91% 1/16W MF-LF 2 4027C6 7B8 7C6 7B8 7C6

52435-2872F-RT-SM 29

J1101

1% 1/16W MF-LF 2 402

OUT OUT OUT

XDP_TDI XDP_TMS

1 2 3

XDP_TRST_LXDP_TCK ITP_TDO(TCK) NC NC

4 5 6 7 8 9 10

ITP11B3 7C6 7A8

R11027C6

OUT

IN

XDP_TDOITP

22.6 2 11% 1/16W MF-LF 402

84C6 34D3

(FROM CK410M HOST 133/167MHZ)84C6 34D3

IN IN

CPU_XDP_CLK_N CPU_XDP_CLK_P

R110084D6 12C4 7D6

IN

FSB_CPURST_L

1

22.6 21% 1/16W MF-LF 402

11B3 7C6 7A8

OUT84C6

XDP_TCKITPRESET_L

(FBO)

11 12 13 14

84C6 7C6

IO

XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_LNC

84C6 7C6

IO

15 16

B

65D3 26C5 23D1

=PP3V3_S5_SB_PM84C6 7C6

IO

17 18

B

1

R1104240

84C6 7C6

IO

19 20

5% 1/16W MF-LF 2 402

84C6 7C6

IO

21 22

84C6 7C6

IO

23 24 25

(AND WITH RESET BUTTON)

OUT

26C6 7C6

XDP_DBRESET_L65D6 11C5 9B7 8C7 7D5 7B6 7B5

=PP1V05_S0_CPU1

26 27

(DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM. (DEBUG PORT ACTIVE) (DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC (DEBUG PORT RESET)

C11000.1UF

28

10% 2 16V X5R 402

30

518S03201

R1106680

ITP TCK SIGNAL LAYOUT NOTE: ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO CPUS TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX CONNECTORS FBO PIN.

5% 1/16W MF-LF 2 402

CPU ITP700FLEX DEBUG

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

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84D6 7C4 5D5

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

D

84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7C4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5

G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8

D1284D6

IO IO IO IO IO IO IO IO IO IO IO IO IO IO1

A1184D6

C1184D6

A1284D6

A1384D6

E1384D6

G1384D6

F1284D6

B1284D6

B1484D6

C1284D6

A1484D6

C1484D6

=PP1V05_S0_FSB_NB

C

12A7 12B7 19D7 34B8 34C6 34C8 65D6

84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7B4 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 84D6 7C3 5D5 65D6 34C8 34C6 34B8 19D7 12C2 12A7

D14

C

R12101001% 1/16W MF-LF 402

HADS* HADSTB0* HADSTB1* HAVREF HBNR* HBPRI* HBREQ0* HCPURST* HDBSY* HDEFER* HDPWR* HDRDY* HDVREF HDINV0* HDINV1* HDINV2* HDINV3* HDSTBN0* HDSTBN1* HDSTBN2* HDSTBN3* HDSTBP0* HDSTBP1* HDSTBP2* HDTSBP3* HHIT* HHITM* HLOCK* HREQ0* HREQ1* HREQ2* HREQ3* HREQ4* HRS0* HRS1* HRS2* HSLPCPU* HTRDY*

E8 B9 C13 J13 C6 F6 C7 B7 A7 C384D6

84D6 7D6 5D5 84C6 7D8 5D5 84C6 7C8 5D5

J9 7B3 H8 K13

FSB_ADS_L FSB_ADSTB_L FSB_ADSTB_L NB_FSB_VREF FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L

IO IO2

IO

IO1

OUT IO OUT IO OUT IO IO

C12110.1uF10% 16V X5R 402

1

R12112001% 1/16W MF-LF 402

2 2

J7 W8 U3 AB10 K4 T7 Y5 AC4 K3 T6 AA5 AC5

84D6 7C4 5D5 84D6 7B4 5D5 84D6 7C3 5D5 84D6

FSB_DINV_L FSB_DINV_L FSB_DINV_L 7B3 5D5 FSB_DINV_L FSB_DSTBN_L FSB_DSTBN_L FSB_DSTBN_L 7B3 5D5 FSB_DSTBN_L FSB_DSTBP_L FSB_DSTBP_L FSB_DSTBP_L 7B3 5D5 FSB_DSTBP_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L

IO IO IO IO IO IO IO IO IO IO IO IO

=PP1V05_S0_FSB_NB

84D6 7C3 5D5 84D6 7B3 5D5 84D6 7B3 5D5

84D6 7C4 5D5 84D6 7B4 5D5 84D6 7C3 5D5 84D6

R1220 154.9

1

R12252211% 1/16W MF-LF 402

84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5

B

1% 1/16W MF-LF 402

2

2

84D6 7C4 5D5 84D6 7B4 5D5 84D6 7C3 5D5 84D6

B

D3 D4 B3

R122124.91% 1/16W MF-LF 402

1

1

84D6 7B3 5D5

R12261001% 1/16W MF-LF 402

1

C12260.1uF10% 16V X5R 402

84D6 7D6 5D5 84D6 7D6 5D5 84D6 7D6 5D5

IO IO IO

84D6 7B3 5D5 84D6 7B3 5D5 84D6 7B3 5D5

D8 G8 B8

2

2

2

84D6 7D8 5D5 84D6 7D8 5D5 84D6 84D6

NB_FSB_XRCOMP NB_FSB_XSCOMP NB_FSB_XSWING NB_FSB_YRCOMP NB_FSB_YSCOMP NB_FSB_YSWING

E1 E2 E4

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING HCLKIN HCLKIN*

F884D6

A8

FSB_REQ_L FSB_REQ_L 7D8 5D5 FSB_REQ_L 7D8 5D5 FSB_REQ_L 7D8 5D5 FSB_REQ_L FSB_RS_L FSB_RS_L FSB_RS_L7A3

IO IO IO IO IO

B4 E6 D6

Y1 U1 W1 AG2 AG1

OUT OUT OUT

65D6 34C8 34C6 34B8 19D7 12C2 12B7

=PP1V05_S0_FSB_NB

R123054.91% 1/16W MF-LF 402

1

1

34D3

R12352211% 1/16W MF-LF 402

IN IN

34D3

FSB_CLK_NB_P FSB_CLK_NB_N

E3 E7

FSB_SLPCPU_L FSB_TRDY_L

OUT OUT

2

2

NB CPU Interface

AR123124.91% 1/16W MF-LF 402 1 1

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

R12361001% 1/16W MF-LF 402

NOTICE OF PROPRIETARY PROPERTY1

A

C12360.1uF10% 16V X5R 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

2

2

2

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

12

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www.laptop-schematics.com

FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L

F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11

HD0* HD1* HD2* HD3* HD4* HD5* HD6* HD7* HD8* HD9* HD10* HD11* HD12* HD13* HD14* HD15* HD16* HD17* HD18* HD19* HD20* HD21* HD22* HD23* HD24* HD25* HD26* HD27* HD28* HD29* HD30* HD31* HD32* HD33* HD34* HD35* HD36* HD37* HD38* HD39* HD40* HD41* HD42* HD43* HD44* HD45* HD46* HD47* HD48* HD49* HD50* HD51* HD52* HD53* HD54* HD55* HD56* HD57* HD58* HD59* HD60* HD61* HD62* HD63*

OMIT

U1200945GM NBBGA

(1 OF 10)

HA3* HA4* HA5* HA6* HA7* HA8* HA9* HA10* HA11* HA12* HA13* HA14* HA15* HA16* HA17* HA18* HA19* HA20* HA21* HA22* HA23* HA24* HA25* HA26* HA27* HA28* HA29* HA30* HA31*

H9 C9 E11 G11 F11 G12

84D6 7D8 5D5 84D6 7D8 5D5 84D6 7D8 5D5 84D6 7D8 5D5 84D6 7D8 5D5 84D6 84D6

F984D6

H1184D6

J1284D6

G1484D6

D984D6

J1484D6

H1384D6

J1584D6

F1484D6

FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7D8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L 7C8 5D5 FSB_A_L

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

D

HOST

8

7

6

5

4

3

2

1

=PP1V5_S0_NB_PCIE1

19D7 65C6

R131024.91% 1/16W MF-LF 402

OMIT

U1200LVDS Disable79A4

D

OUT OUT OUT OUT IO IO IO

Can leave all signals NC if LVDS is not implemented Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used VCCD_LVDS must remain powered with proper decoupling. Otherwise, tie VCCD_LVDS to GND also.

79A4 19D3 19D3 79A7 79A7 19D3

79A4 19D3 19D3

OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

LVDS_BKLTCTL LVDS_BKLTEN LVDS_CLKCTLA LVDS_CLKCTLB LVDS_DDC_CLK LVDS_DDC_DATA LVDS_IBG TP_LVDS_VBG LVDS_VDDEN LVDS_VREFH LVDS_VREFL LVDS_A_CLK_N LVDS_A_CLK_P LVDS_B_CLK_N LVDS_B_CLK_P LVDS_A_DATA_N LVDS_A_DATA_N LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_P LVDS_A_DATA_P LVDS_B_DATA_N LVDS_B_DATA_N LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_P LVDS_B_DATA_P

D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 A33 A32 E27 E26 C37 B35 A37 B37 B34 A36 G30 D30 F29 F30 D29 F28

L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LA_CLK* LA_CLK LB_CLK* LB_CLK LA_DATA0* LA_DATA1* LA_DATA2* LA_DATA0 LA_DATA1 LA_DATA2 LB_DATA0* LB_DATA1* LB_DATA2* LB_DATA0 LB_DATA1 LB_DATA2

945GM NBBGA

2

EXP_A_COMPI EXP_A_COMPO EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8 EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13 EXP_A_RXN14 EXP_A_RXN15 EXP_A_RXP0 EXP_A_RXP1 EXP_A_RXP2 EXP_A_RXP3 EXP_A_RXP4 EXP_A_RXP5 EXP_A_RXP6 EXP_A_RXP7 EXP_A_RXP8 EXP_A_RXP9 EXP_A_RXP10 EXP_A_RXP11 EXP_A_RXP12 EXP_A_RXP13 EXP_A_RXP14 EXP_A_RXP15 EXP_A_TXN0 EXP_A_TXN1 EXP_A_TXN2 EXP_A_TXN3 EXP_A_TXN4 EXP_A_TXN5 EXP_A_TXN6 EXP_A_TXN7 EXP_A_TXN8 EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12 EXP_A_TXN13 EXP_A_TXN14 EXP_A_TXN15 EXP_A_TXP0

D40 D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40

PEG_COMP SDVO Alternate Function PEG_D2R_N 67D1 PEG_D2R_N 67D1 PEG_D2R_N 67D1 PEG_D2R_N 67C1 PEG_D2R_N 67C1 PEG_D2R_N 67C1 PEG_D2R_N 67C1 PEG_D2R_N 67C1 PEG_D2R_N 67C1 PEG_D2R_N 67B1 PEG_D2R_N 67B1 PEG_D2R_N 67B1 PEG_D2R_N 67B1 PEG_D2R_N 67B1 PEG_D2R_N 67B1 PEG_D2R_N67D1

D

(3 OF 10)

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SDVO_TVCLKIN# SDVO_INT# SDVO_FLDSTALL#

79D3 79D3 79C3 79C3

79D3 79D3 79D3

79D3 79D3 79D3

79D3 79C3 79D3

79D3

PCI-EXPRESS GRAPHICS

CTV-Out Signal Usage: Composite: DACA only S-Video: DACB & DACC only Component: DACA, DACB & DACC Unused DAC outputs must remain powered, but can omit filtering components. Unused DAC outputs should connect to GND through 75-ohm resistors. TV-Out Disable

79C3 79C3

19D5 19D5 19D5

OUT OUT OUT OUT OUT OUT OUT

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

A16 C18 A19 J20 B16 B18 B19

TV_DACA_OUT TV_DACB_OUT

19D5 19D5 19C5 19C5

TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

TV

TV_DACC_OUT

PEG_D2R_P 67D1 PEG_D2R_P 67D1 PEG_D2R_P 67D1 PEG_D2R_P 67D1 PEG_D2R_P 67C1 PEG_D2R_P 67C1 PEG_D2R_P 67C1 PEG_D2R_P 67C1 PEG_D2R_P 67C1 PEG_D2R_P 67C1 PEG_D2R_P 67B1 PEG_D2R_P 67B1 PEG_D2R_P 67B1 PEG_D2R_P 67B1 PEG_D2R_P 67B1 PEG_D2R_P67D1

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

C

19D5

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail. Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND. CRT Disable

OUT OUT OUT OUT OUT OUT IO IO OUT OUT OUT

19D5 19D5 19D5 19D5 19D5

A21 B21 C26 C25 G23 J22 H23

CRT_RED CRT_RED* CRT_DDC_CLK CRT_DDC_DATA HSYNC CRT_IREF CRT_VSYNC

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

19D5 19D5 19D5 19D5 19D5

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC_R CRT_IREF CRT_VSYNC_R

VGA

CRT_BLUE CRT_BLUE_L CRT_GREEN CRT_GREEN_L CRT_RED CRT_RED_L

E23 D23 C22 B22

CRT_BLUE CRT_BLUE* CRT_GREEN CRT_GREEN*

PEG_R2D_C_N 67D5 PEG_R2D_C_N 67D5 PEG_R2D_C_N 67D5 PEG_R2D_C_N 67C5 PEG_R2D_C_N 67C5 PEG_R2D_C_N 67C5 PEG_R2D_C_N 67C5 PEG_R2D_C_N 67C5 PEG_R2D_C_N 67C5 PEG_R2D_C_N 67B5 PEG_R2D_C_N 67B5 PEG_R2D_C_N 67B5 PEG_R2D_C_N 67B5 PEG_R2D_C_N 67B5 PEG_R2D_C_N 67B5 PEG_R2D_C_N67D5

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN

B

EXP_A_TXP1 EXP_A_TXP2 EXP_A_TXP3 EXP_A_TXP4 EXP_A_TXP5 EXP_A_TXP6 EXP_A_TXP7 EXP_A_TXP8 EXP_A_TXP9 EXP_A_TXP10 EXP_A_TXP11 EXP_A_TXP12 EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15

PEG_R2D_C_P 67D5 PEG_R2D_C_P 67D5 PEG_R2D_C_P 67D5 PEG_R2D_C_P 67D5 PEG_R2D_C_P 67C5 PEG_R2D_C_P 67C5 PEG_R2D_C_P 67C5 PEG_R2D_C_P 67C5 PEG_R2D_C_P 67C5 PEG_R2D_C_P 67B5 PEG_R2D_C_P 67B5 PEG_R2D_C_P 67B5 PEG_R2D_C_P 67B5 PEG_R2D_C_P 67B5 PEG_R2D_C_P 67B5 PEG_R2D_C_P67D5

SDVOB_RED SDVOB_GREEN SDVOB_BLUE SDVOB_CLKP SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP

B

NB PEG / Video Interfaces

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

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LVDS

8

7

6

5

4

3

2

1

65B3 20B4 20A4 19C7 14C7

=PP3V3_S0_NB

R1440 110K

1

R144110K5% 1/16W MF-LF 402

D

5% 1/16W MF-LF 402

OMIT

2

2

U1200NC NC NC NC NC NC TP_NB_XOR_FSB2_H7 TP_NB_TESTIN_L NB_TV_DCONSEL0 NB_TV_DCONSEL1 NC19D3 19D3 19D3 19D3

DSM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK0* SM_CK1*AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41 AF33 AG33 A27 A26 C40 D41 AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41

A34 D28 D27 K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26 G28 F25 H26

RSVD13 RSVD14 RSVD15 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

SM_CKE3 SM_CS0* SM_CS1* SM_CS2* SM_CS3* SMOCDCOMP0 SMOCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2

OUT OUT OUT OUT OUT

30D6 28B3 30D6 28B6

34C7 34B7 34B7 6D6 6D6 20C7 6D6 20C7 6D6

IN IN IN IN IN IN IN IN IN IN IN IN

C

20B7 6D6 6D6

6C6 IN 6C6 6D6 65B3 20B4 20A4 19C7 14D6

IN IN IN IN IN IN IN IN OUT

=PP3V3_S0_NB

6D6 20C5 6D6

R1420 110K5% 1/16W MF-LF 402 250D5 49B7 84C6 59C8 23C3

20B5 20B5 20A5

NB_BSEL NB_BSEL NB_BSEL NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG PM_BMBUSY_L

MEM_CS_L MEM_CS_L 30D6 29B3 MEM_CS_L 30D6 29B6 MEM_CS_L NC NC30C6 28B3 30C6 28B6 30C6 29B3

IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD

=PP1V8_S3_MEM_NB MEM_ODT MEM_ODT MEM_ODT 30C6 29B6 MEM_ODT MEM_RCOMP_L MEM_RCOMP32B3 32B3

16B6 19D7 65B6

1 OUT OUT OUT OUT 2

R141080.61% 1/16W MF-LF 402

SM_ODT3 SMRCOMP* SMRCOMP SMVREF0 SMVREF1 G_CLKIN*

CIN IN

MEM_VREF_NB_0 MEM_VREF_NB_1

CLK

G_CLKIN D_REFCLKIN* D_REFCLKIN D_REFSSCLKIN* D_REFSSCLKIN DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2

NB_CLK100M_GCLKIN_N 34C4 NB_CLK100M_GCLKIN_P 34B4 34B2 NB_CLK_DREFCLKIN_N 34B4 34B2 NB_CLK_DREFCLKIN_P 34B4 NB_CLK_DREFSSCLKIN_N 34B4 NB_CLK_DREFSSCLKIN_P34C4

IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT

C14150.1uF20% 10V CERM 402

1

1

C14160.1uF20% 10V CERM 402

1

R141180.6

2

2

1% 1/16W MF-LF 2 402

23C5

PM_BM_BUSY* PM_EXTTS0* PM_EXTTS1* PW_THRMTRIP* PWROK RSTIN*

IN IN

50C1 21C2 7C6

R143026C1

OUT IN

59C7 26B5

IN

NB_RST_IN_L

1

1005% 1/16W MF-LF 402

2

PM_THRMTRIP_L VR_PWRGOOD_DELAY NB_RST_IN_L_R SDVO_CTRLCLK SDVO_CTRLDATA NB_SB_SYNC_L CLK_NB_OE_L NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

G6 AH33 AH34 H28 H27 K28 H32 D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3

PM

PM_EXTTS_L PM_DPRSLPVR

DMI_S2N_N 22D2 DMI_S2N_N 22D2 DMI_S2N_N 22D2 DMI_S2N_N22D2

IO IO OUT OUT

MISC DMI

19D3 19D3 22A6 33B4

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC* CLK_REQ* NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18

DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_S2N_P DMI_S2N_P 22D2 DMI_S2N_P 22D2 DMI_S2N_P22D2 22D2

DMI_N2S_N DMI_N2S_N 22D2 DMI_N2S_N 22D2 DMI_N2S_N DMI_N2S_P DMI_N2S_P 22D2 DMI_N2S_P 22D2 DMI_N2S_P

B

B

NB Misc Interfaces

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

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TP_NB_XOR_LVDS_A35 TP_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D27

A35

RSVD12

DDR MUXING

(D_PLLMON1#) (D_PLLMON1) (H_EDRDY#) (H_PCREQ#) (H_PLLMON1#) (H_PLLMON1) (H_PROCHOT#) (TESTIN#) (TV_DCONSEL0) (TV_DCONSEL1) (VSS_MCHDETECT) (LA_DATAN3) (LA_DATAP3) (LB_DATAN3) (LB_DATAP3)

T32 R32 F3 F7 AG11 AF11 H7 J19 K30 J29 A41

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6

945GM NBBGA

(2 OF 10)

MEM_CLK_P 28A3 MEM_CLK_P 29A3 MEM_CLK_P 29D3 MEM_CLK_P28D3

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

RSVD

RSVD7 RSVD8 RSVD9 RSVD10 RSVD11

SM_CK2* SM_CK3* SM_CKE0 SM_CKE1 SM_CKE2

MEM_CLK_N 28A3 MEM_CLK_N 29A3 MEM_CLK_N 29D3 MEM_CLK_N28D3 30D6 28C6 30D6 28C3

MEM_CKE MEM_CKE 30D6 29C6 MEM_CKE 30D6 29C3 MEM_CKE

NC

CFG

8

7

6

5

4

3

2

1

D28D3 28D3 28D3 28D3 28D6 28D6 28D6 28D6 28D3 28D3 28D6 28D6 28D3 28D6 28D6 28D3 28C6 28C3 28C6 28C6 28C6 28C3 28C3

OMIT

OMIT

DSB_BS0 SB_BS1 SB_BS2 SB_CAS* SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN430A6 29B6 30A6 29B3 30A6 29C6 30A6 29B6

U1200IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

U1200SA_BS0 SA_BS1 SA_BS2 SA_CAS* SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH430B6 28B6 30B6 28B3 30B6 28C6 30B6 28B6

C

28C3 28C3 28C6 28C3 28C6 28C6 28C3 28C6 28C3 28B3 28B6 28B3 28B6 28B3 28B6 28B3 28B6 28A3 28A6 28A3 28A6 28A3 28A6 28A6 28A3 28A6

B

28A3 28A6 28A6 28A3 28A6 28A3 28A3 28A3 28B3 28A6 28B6 28B6 28A6 28A3 28B3

MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

945GM NBBGA

MEM_A_BS MEM_A_BS MEM_A_BS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

29D3 29D6 29D6 29D3 29D6 29D3 29D3 29D6 29D3 29D3 29D6 29D3 29D3 29D6

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

(4 OF 10) MEM_A_CAS_L 28D3 MEM_A_DM 28D3 MEM_A_DM 28C3 MEM_A_DM 28C6 MEM_A_DM 28B3 MEM_A_DM 28A3 MEM_A_DM 28A6 MEM_A_DM 28A6 MEM_A_DM MEM_A_DQS_P 28D6 MEM_A_DQS_P 28C6 MEM_A_DQS_P 28C3 MEM_A_DQS_P 28B6 MEM_A_DQS_P 28A6 MEM_A_DQS_P 28A3 MEM_A_DQS_P 28A3 MEM_A_DQS_P 28D6 MEM_A_DQS_N 28D6 MEM_A_DQS_N 28C6 MEM_A_DQS_N 28C3 MEM_A_DQS_N 28B6 MEM_A_DQS_N 28A6 MEM_A_DQS_N 28A3 MEM_A_DQS_N 28B3 MEM_A_DQS_N28D6 30C6 28B3

AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

29D6 29D6 29C3 29C3 29C3 29C6 29C6 29C6 29C3 29C6 29C6 29C6 29C3 29C6 29C3 29C6 29C3

DDR SYSTEM MEMORY A

AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3

SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0* SA_DQS1* SA_DQS2* SA_DQS3* SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7* SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_RAS* SA_RCVENIN* SA_RCVENOUT* SA_WE*

DDR SYSTEM MEMORY B

SA_DQS4

AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12

MEM_A_A 30C6 28B6 MEM_A_A 30C6 28B3 MEM_A_A 30C6 28B6 MEM_A_A 30C6 28B3 MEM_A_A 30C6 28B6 MEM_A_A 30C6 28C3 MEM_A_A 30C6 28C3 MEM_A_A 30C6 28C6 MEM_A_A 30C6 28C6 MEM_A_A 30C6 28B6 MEM_A_A 30C6 28C3 MEM_A_A 30C6 28C6 MEM_A_A 30C6 28B3 MEM_A_A30B6 28B3

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

29C3 29B3 29B6 29B6 29B6 29B6 29B3 29B3 29B3 29B6 29B6 29A6 29A6 29B3 29B3

AW14 AK23 AK24 AY14

MEM_A_RAS_L

OUT

29A3 29A3

NC NC30B6 28B6

MEM_A_WE_L

29A3

OUT

29A6 29A3 29A6 29A6 29A3 29A6 29A3 29A3 29A3 29A3 29A6 29A6 29A6 29A6 29A3

MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ

AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

945GM NBBGA

MEM_B_BS MEM_B_BS MEM_B_BS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

(5 OF 10) MEM_B_CAS_L 29D3 MEM_B_DM 29D3 MEM_B_DM 29C3 MEM_B_DM 29C6 MEM_B_DM 29B3 MEM_B_DM 29A6 MEM_B_DM 29A6 MEM_B_DM 29A3 MEM_B_DM MEM_B_DQS_P 29D6 MEM_B_DQS_P 29C6 MEM_B_DQS_P 29C3 MEM_B_DQS_P 29B6 MEM_B_DQS_P 29A3 MEM_B_DQS_P 29A3 MEM_B_DQS_P 29A6 MEM_B_DQS_P 29D6 MEM_B_DQS_N 29D6 MEM_B_DQS_N 29C6 MEM_B_DQS_N 29C3 MEM_B_DQS_N 29B6 MEM_B_DQS_N 29B3 MEM_B_DQS_N 29A3 MEM_B_DQS_N 29A6 MEM_B_DQS_N29D6 30B6 29B3

AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS0* SB_DQS1* SB_DQS2* SB_DQS3* SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7* SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_RAS* SB_RCVENIN* SB_RCVENOUT* SB_WE*

C

AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23

MEM_B_A 30B6 29B6 MEM_B_A 30B6 29B3 MEM_B_A 30B6 29B6 MEM_B_A 30B6 29B3 MEM_B_A 30B6 29B6 MEM_B_A 30B6 29C3 MEM_B_A 30B6 29C3 MEM_B_A 30B6 29C6 MEM_B_A 30B6 29C6 MEM_B_A 30B6 29B6 MEM_B_A 30B6 29C3 MEM_B_A 30B6 29C6 MEM_B_A 30B6 29B3 MEM_B_A30A6 29B3

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

AU23 AK16 AK18 AR27

MEM_B_RAS_L

OUT

NC NC30A6 29B6

MEM_B_WE_L

OUT

B

NB DDR2 Interfaces

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

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2NCTF balls are Not Critical To FunctionThese connections can break without impacting part performance. OMITAD27 AC27 AB27 AA27 Y27 W27

1

65D6 19D7 19D2 19C8 16C8

=PPVCORE_S0_NB

VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72

U1200945GM NBBGA

VSS_NCTF0 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12

AE27 AE26 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AC17 Y17 U17

(7 OF 10)

U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25

NCTF

D

V27

D

=PP1V5_S0_NB_VCCAUXVCCAUX_NCTF0 VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VCCAUX_NCTF39 VCCAUX_NCTF40 VCCAUX_NCTF41 VCCAUX_NCTF42 VCCAUX_NCTF43 VCCAUX_NCTF44 VCCAUX_NCTF45 VCCAUX_NCTF46 VCCAUX_NCTF47 VCCAUX_NCTF48 VCCAUX_NCTF49 VCCAUX_NCTF50 VCCAUX_NCTF51 VCCAUX_NCTF52 VCCAUX_NCTF53 VCCAUX_NCTF54 VCCAUX_NCTF55 VCCAUX_NCTF56 VCCAUX_NCTF57AG27 AF27 AG26 AF26 AG25 AF25 AG24 AF24 AG23 AF23 AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18 AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17 T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15

17B6 19C4 19D7 65B6

=PPVCORE_S0_NB 1.05V or 1.5VAA33 AA32

16D3 19C8 19D2 19D7

1.05V, Internal Graphics: 3500mA Max 1.05V, External Graphics: 1500mA Max 65D6 1.5V, Internal Graphics: 5500mA Max

AB25 AA25 Y25 W25 V25

U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24

U1200

945GM NB

BGA

OMIT

VCC_SM100 VCC_SM101

VCC_SM102

VCC_SM103 VCC_SM104

VCC_SM105

VCC_SM106 VCC_SM107

VCC_SM10 VCC_SM11

VCC_SM12 VCC_SM13

VCC_SM14

VCC_SM15 VCC_SM16

VCC_SM17

VCC_SM18 VCC_SM19

VCC_SM20

VCC_SM21 VCC_SM22

VCC_SM23 VCC_SM24

VCC_SM25

VCC_SM26 VCC_SM27

VCC_SM28

VCC_SM29 VCC_SM30

VCC_SM31

VCC_SM32 VCC_SM33

VCC_SM34 VCC_SM35

VCC_SM36

VCC_SM37 VCC_SM38

VCC_SM39

VCC_SM40 VCC_SM41

VCC_SM42

VCC_SM43 VCC_SM44

VCC_SM45 VCC_SM46

VCC_SM47

VCC_SM48 VCC_SM49

VCC_SM50

VCC_SM51 VCC_SM52

VCC_SM53

VCC_SM54 VCC_SM55

VCC_SM56 VCC_SM57

VCC_SM58

VCC_SM59 VCC_SM60

VCC_SM61

VCC_SM62 VCC_SM63

VCC_SM64

VCC_SM65 VCC_SM66

VCC_SM67 VCC_SM68

VCC_SM69

VCC_SM70 VCC_SM71

VCC_SM72

VCC_SM73 VCC_SM74

VCC_SM75

VCC_SM76 VCC_SM77

VCC_SM78 VCC_SM79

VCC_SM80

VCC_SM81 VCC_SM82

VCC_SM83

VCC_SM84 VCC_SM85

VCC_SM86

VCC_SM87 VCC_SM88

VCC_SM89 VCC_SM90

VCC_SM91

VCC_SM92 VCC_SM93

VCC_SM94

VCC_SM95 VCC_SM96

VCC_SM97

VCC_SM98 VCC_SM99

VCC_SM0

VCC_SM1 VCC_SM2

VCC_SM3

VCC_SM4 VCC_SM5

VCC_SM6

VCC_SM7 VCC_SM8

VCC_SM9

BA8

AY8

AW8

AV8

AT8

AR8

AP8

BA6

AY6

AW6

AV6

AT6

AR6

AP6

AN6

AL6

AK6

AJ6

AV1

AU41

AT41

AM41

AU40

BA34

AY34

AW34

AV34

AU34

AT34

AR34

BA30

AY30

AW30

AV30

AU30

AT30

AR30

AP30

AN30

AM30

AM29

AL29

AK29

AJ29

AH29

AJ28

AH28

AJ27

AH27

BA26

AY26

AW26

AV26

AU26

AT26

AR26

AJ26

AH26

AJ25

AH25

AJ24

AH24

BA23

AJ23

BA22

AY22

AW22

AV22

AU22

AT22

AR22

AP22

AK22

AJ22

AK21

AK20

BA19

AY19

AW19

AV19

AU19

AT19

AR19

AP19

AK19

AJ19

AJ18

AJ17

AH17

AJ16

AH16

BA15

AY15

AW15

AV15

AU15

AT15

AR15

AJ15

AJ14

AJ13

AH13

AK12

AJ12

AH12

AG12

AK11

AJ1

NB_VCCSM_LF4 NB_VCCSM_LF5

C16140.47UF10% 6.3V CERM-X5R 402

1

2

B

A

8

VCC

C

Speed 400MTs 533MTs 667MTs

1.8V Max Current 1 Channel 2 Channel 1300mA 2400mA 1500mA 2800mA 1700mA 3200mA

C

V24 U24 T24 R24 AD23 V23 U23 T23 R23

1

C16150.47UF10% 6.3V CERM-X5R 402

65B6 19D7 14C2

=PP1V8_S3_MEM_NB

NB_VCCSM_LF2 NB_VCCSM_LF11 1

AD22 V22 U22

2 1

C16130.47UF10% 6.3V CERM-X5R 402

Layout Note: Place near pin BA23

C162010uF20% 6.3V X5R 603

C162110uF20% 6.3V X5R 603

1

C16100.47UF10% 6.3V CERM-X5R 402

C16120.47UF10% 6.3V CERM-X5R 402

1

1

C16110.47UF10% 6.3V CERM-X5R 402

T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18

2

2

2

2

2

2

Layout Note: Place near pin BA15 Layout Note: Place in cavity

B

NB Power 1SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7150SHT OF

A.0.0 84

16

7

6

5

4

3

2

1

www.laptop-schematics.com

AA31

AA30

AA29

AB28

AA28

AB23

AA23

AC22

AB22

AC21

AA21

AC20

AB20

AB19

AA19

W33

P33

N33

L33

J33

Y32

W32

V32

P32

N32

M32

L32

J32

W31

V31

T31

R31

P31

N31

M31

Y30

W30

V30

U30

T30

R30

P30

N30

M30

L30

Y29

W29

V29

U29

R29

P29

M29

L29

Y28

V28

U28

T28

R28

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

L26

N25

M25

L25

P24

N24

M24

Y23

P23

N23

M23

L23

Y22

W22

P22

N22

M22

L22

W21

N21

M21

L21

Y20

W20

P20

N20

M20

L20

Y19

N19

M19

L19