A Comparative Study of Delay Analysis for Carbon Nanotube and Copper based VLSI

Interconnect Models

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERINGTHAPAR UNIVERSITY, PATIALA

ByHARPREET SINGH BHATIA

Under the supervision ofMR. MAYANK K. RAI

Assistant Professor, ECED

Outline

• Introduction• Interconnect Models• Factors affecting interconnect performance• CNT v/s Copper• Analytical Delay Estimation • SPICE simulation- CNT v/s Copper• Conclusion

• Interconnects – these are wires connecting transistors.• As technology scales down :

[1]

•Density of interconnect >> Density of gates; •Interconnects constitute the main source of Delay.

Types• Local/short• Intermediate / semiglobal• Global

Local Global

Effect of SCALING

RC delay:

Local delay:

Global:

Introduction

RC.L = (RL)(CL) = t 2int

RC.L = L)(C)(R. = t 22

2int

SS

.RC.L = L)(C)(R. = t 222int SS

Interconnect Models

RC modelRLC Model

Xox

L

h

W

Parasitic Inductance h.w

L≈ nH/cm

Parasitic Resistance R = ρ.L

R≈ kΩ/cm

h.w

Parasitic CapacitanceCpp = ε.w.l

C= Cpp +Cfringe

C≈ pF/cm

Xox

f ( ) L

LM ≈

Factors affecting Interconnect Performance

• Repeater design

• Dielectric

• Pitch

• Length

• Aspect Ratio

oxX A C

0k

3n W/L n, W/L loaddriver

hls

εdielectricpp C

Pitch = w + s

But,wl

SRR

wh AR

AR.C l

→→

Limitations of Copper

• Surface Scattering

• Grain Boundary effect

• Barrier Width

Polycrystalline are composed of many crystallites/ grains. e- s scatter at Grain-boundaries.

Increase in ρo- from 1.9μΩ-cm to 4.9μΩ-cm @ 45nm [25]

MFP of e- in Cu = 40 - 100 nm

Carbon Nanotube (CNT)Future interconnect material?

• Graphene sheet rolled into a tube. Formation eliminates dangling bonds • Single Wall CNT (SWCNT) and Multiple Wall CNT (MWCNT)

Advantages CNT CuMean free path (nm) @ room

temp >1000 40

Max current density (A/cm2) >1x1010 ~1x106

Thermal conductivity (W/mK) 5800 385

Problems1. High resistance ~6.45kΩ

2. Contact resistance~100Ω Therefore, the NEED FOR

CNT BUNDLE

3. Lack of control on chirality

Kinetic InductanceLK = h/4e2vF

•Only for L< λCNT •Not observed upto 10GHz freq

CNT ModelFor L< λCNT or MFP:

Fundamental ResistanceRF = h/4e2 = 6.45 KΩSince each nanotube has four conducting channels in parallel (N=4)

Ground-Plate CapacitanceCE = 2πε

ln(y/d)

Quantum CapacitanceCQ = 2e2

Quantum electrostatic energy stored in the nanotube when it carries current.4 CQ for 4 channels

hvF

Magnetic InductanceLM = μ ln(y/d)

2π

[16]

→

CNT v/s Cu

small l small R

For L<Lo =6.45 KΩ

LOCAL INTERCONNECTS

GLOBAL INTERCONNECTS

Aρ.l RCu

02CNT L

L4eh R

2CNT 4e

h R

For Copper: large l large

grows more slowly than Copper because Rcontact is a constant resistance

RCNT

CuR

Analytical Delay Estimation

1. Driver Interconnect Model (DIL)

2. Modified Nodal Analysis (MNA) and Moment Matching

3. Unified Time Delay Model

1. Driver Interconnect Model (DIL)

• Region 1 : During this region, the nMOS is cut off.

• Region 2 : During this region, the nMOS operates in saturation

• Region 3 : During this region and nMOS is still in saturation

• Region 4 : During this region, and nMOS transistor operates in linear region.

RLC interconnect driven a CMOS driver

uses α-power law MOS model →

0 i i Ld

0 i i i Ldn

τ VV DD in

t

DD in VV

[20]

DIL Results

0 0.3

0.600000000000001

0.812000000000001 1.1 1.4

1.70000000000001 20

0.2

0.4

0.6

0.8

1

1.2

spice

time (ns)

Volta

ge (

V)

0 0.4

0.712000000000001 1.1 1.5 1.9 2.3 2.70

0.2

0.4

0.6

0.8

1

1.2

spice

time (ns)

Volta

ge (V

)

COPPER CNT

2. Modified Nodal Analysis (MNA)

Performing the inversion on matrix is complicated. Reduction is done by Matrix Approximation (PVL and Arnoldi approximation)

(t) +(t)- =(t) uPxGxM

(t)(t) xQy

BA1QuyH )+( =

)()(=)( 1-s

sss

L

CM

00

=

(t)(t)

=(t)L

c

iv

x

REEY

G T-=where,

Using Laplace transform we solve the equations in s-Domain

MGA -1 PGB 1where,

Solving the above circuit through MNA, we obtain these two equations:

)+( A1 s

Moment Matching

Maclaurin expansion of the transfer function (Taylor’s expansion around s=0)

The coefficients of this expansion are known as central moments

Focusing on the first moment

If y(t) is a step function, then this voltage-time area is equal to its 50% delay

→

Moment Matching example

+

-

Vs1V

Cmos2.1fF

=L1L2

=C1C2C1

0.0053pF

L1884.5pH

Rmos6.631k =R1

R2R11037.82k

Using Moment Matching of Maclaurin Series, we calculate the first moment m(1) =16.56 ns.

i.e. 50 % delay = 16.56 ns.

SPICE Simulation Results show this to be 13.59 ns. (error of 21.86 %.)

Using MNA and PVL approximation, we calculate the transfer function H(s) upto 3 terms:

2-16-8 )10×(2.743+) 10× (1.656-1=)( sssH

3. Unified Time Delay Model

Unified Time Delay for distributed RLC lines

Unified Time Delay for repeater insertion

, tt=t d,rcd,rlcd )(max

])360650(6930[])69303770,[max( 2 Z.+ R.rL+ .C. + cL R.+ rcL.t=t ctrLtrfd

, tt=t repd,rcrepd,rlcd )(max __

] )360650(6930[])69303770,[max(2

hkZ.+ kR.hrL+ .C. +h cLR .+

krcL .t=t ccC

cfd

Meindl et al. (2001 [6-9]) presented simplified delay expressions in a series of four papers.

Unified Time Delay Results

2 4 6 8 10 12 14 160

0.1

0.2

0.3

0.4

0.5

0.6

Analytical DelayExp. Delay

Repeaters

Dela

y (n

s)

2 4 6 8 10 12 14 160

1

2

3

4

5

6

7

8

Analytical DelayExp. Delay

Repeaters

Dela

y (n

s)

Delay for CNT bundle (for (W/L)driver= 80)

Delay for Cu interconnect (for (W/L)driver= 80)

Comparison Of The Analytical Models

S.no. Analytical ModelPercentage error (%)

CNT interconnect Copper interconnect

1.Driver Interconnect Load

(DIL) 6.63% 10.04%

2. MNA & moment matching 20.86% 21.86%

3. Unified Time Delay Model 127% 86.30%

CU v/s CNT (SPICE Simulation)

Simulation parametersCopper CNT

technology 45 nm 45 nm VDD 1V 1Vlength (L) of interconnect 1000 um (global) 1000 um (global)width (w) of interconnect 102.5 nm 102.5 nmspacing (s) between interconnects 102.5 nm 102.5 nmthickness (h) of global interconnect 235.75 nm 235.75 nmresistivity (relative) 2.45 Ω-cm -oxide thickness (tOX) 215.25 nm 215.25 nmεOX (relative) 2.45 2.45Load capacitance 50fF 50fFfrequency 0.1 GHz 0.1 GHz

Cu v/s CNT (SPICE)Variation Of Repeater Size / Number

2 4 6 8 10 12 14 160.600000000000001

0.700000000000001

0.800000000000001

0.900000000000001

1

1.1

1.2

1.3

Repeaters

Dela

y (n

s)

Repeater driver widths W/L(n)

Cu v/s CNT (SPICE)Variation Of Pitch

2 4 6 8 10 12 14 160

0.20.40.60.8

11.21.4

1.5:0.501:010.5:1.5

Repeaters

Dela

y (n

s)

Copper CNT

technology 45 nm 45 nm

frequency 0.1 GHz 0.1 GHz

(W/L)driver 110 110

Conclusion• In the 45 nm node, CNT bundle interconnects show significant

improvement in delay performance as compared to copper interconnects for the following cases-– CNT offers a better reduction in delay when the pitch ratio is

1:1.– CNT gives a better delay reduction than copper when repeater

driver transistor W/L ratio above 80 (29.4 % to 36.43 %).

• When estimating the delay analytically, a tradeoff needs to be made between the computational efficiency and accuracy. – Unified Time Delay Model has simplified expressions but

higher inaccuracies.– Driver Interconnect Model (DIL) is very accurate, but requires

higher computational efficiency.

References1. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, Reading, MA, 1990

2. Bakoglu, H.B. and Meindl, J.D. “Optimal interconnection circuits for VLSI”, IEEE Transactions on Electron Devices, (1985),

Vol. ED-32 No. 5, pp. 903-9.

3. P. Kapur, J.P. Vittie and K. C. Saraswat, “Technology and Reliability Constrainted Future Copper Interconnects-Part I” IEEE

Transactions on Electron Devices, (2002)

4. El-Moursy, M.A. and Friedman, E.G. “Optimum wire sizing of RLC interconnect with repeaters”, Integration, the VLSI

journal (2004)

5. Bakoglu, H.B. and Meindl, J.D. “Optimal interconnection circuits for VLSI”, IEEE Transactions on Electron Devices, (1985)

6. Davis, J.A., Meindl, J.D., Compact distributed RLC interconnect models—Part I: single line transient, time delay and

overshoot expressions, IEEE Trans. Electron Dev. 47 (2000) 2068–2077.

7. J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—Part II: coupled line transient expressions and

peak crosstalk in multilevel interconnect networks, IEEE Trans. Electron Dev. 47 (2000) 2078–2087.

8. R. Venkatesan, J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—Part III: transients in single and

coupled lines with capacitive load termination, IEEE Trans. Electron Dev. 50 (2003) 1081–1093.

9. R. Venkatesan, J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—Part IV: unified models for time

delay, crosstalk, and repeater insertion, IEEE Trans. Electron Dev. 50 (2003) 1094–1102.

10. Chandel, R., Sarkar, S. and Agarwal, R.P. “Repeater insertion in global interconnects in VLSI circuits” (2005).

14. F. Kreupl, et al., “Carbon Nanotubes in Interconnect Applications,” Microelectronic Engineering, 64 (2002)

15. Sakurai, T. and Newton, A.R. “Alpha power law MOSFET model and its applications to CMOS inverter delay and other

formulas”, IEEE Journal of Solid State Circuits, (1990)

16. P J Burke, Luttinger Liquid Theory as a Model of the Gigahertz Electrical Properties of Carbon nanotubes ; IEEE

Transactions on Nanotechnology, Vol 1, no 3, 2002.

17. C. Ho, , A.E. Ruehli, P. A. Brennan, The Modified Nodal Approach to Network Analysis, IEEE Transactions on Circuits

and Systems, 1975

18. A.B. Kahng, S. Muddu, Efficient gate delay modeling for large interconnect loads, IEEE Multi-Chip Module Conf. (1996)

19. Y. I. Ismail and E. G. Friedman, “Sensitivity of Interconnect Delay to On-Chip Inductance”, ISCAS (2000)

20. B.K. Kaushik et al., S. Sarkar, R.P. Agarwal, Waveform analysis and delay prediction for a CMOS gate driving RLC

interconnect load, INTEGRATION, the VLSI journal 40, 2007, pp. 394–405.

21. Shyh-Chyi Wong, Winbond TSM, “Estimation of Wire Parameters” IEEE, Proc. Feb 2000.

22. C. Thiruvenkatesan, J. Raja, “Studies on the Application of Carbon Nanotube as Interconnects for Nanometric VLSI

Circuits”, ICETET-09, (2009)

25. W. Steinhogl, et al., “Size-dependent Resistivity of Metallic Wires in the Mesoscopic Range,” , (2002).

References

THANK YOU

APPENDIX: α-power law MOS model

region saturation: VV ; )V - (V k=I

regionlinear :V< V ;.V )V - (V k=I

region cutoff: VV ; 0=I

sat)(DS-DST0GSSD

sat)(DS-DS DS /2)(

T0GS1D

T0GSD

←

channel length is decreased

lateral electric field EY increases

drift velocity vd α electric field => for electric fields of E >105 V/cm, velocity saturates vd(sat) = 107 cm/s

saturation-mode current is no longer a quadratic function of VGS

APPENDIX: RC Models

• Delay of Pi-Model = RC/3+RC/6 = RC/2 agrees with distributed model RC.

• 3-segment pi-model is accurate to 3% in simulation• L-model needs 100 segments for same accuracy!• Pi Model is often used in Spice instead of large number of segments as a

reasonable approximation of distributed RC.

R/3 R/3 R/3

C/2 C/2

Pi- Model

←

APPENDIX: Repeater insertion

• Repeaters are buffers or inverters inserted at regular intervals.• RC delay is proportional to l2

• Now, Delay linearly proportional to l (Bakoglu and Meindl Model →)

Wire Length: l

Driver Receiver

l/N

Driver

Segment

Repeater

l/N

Repeater

l/N

ReceiverRepeater

N Segments

2intint3.2 ood CRCRT

int3.2 CRT od

←

Repeater design (Bakoglu and Mendl)

Minimum size repeaters• W/Ldriver = 1, W/Lload = 3

Cascaded drivers• Sequence of drivers that increase gradually in size• Used to drive large capacitive loads• Power penalty

Optimal repeaters• Increasing size of repeaters to improve propagation time• Increase W/L by h, R becomes Ro/h, C becomes Co.h• Area penalty + Power Penalty

←

Bakoglu and Meindl Model

For a wire with k repeaters each of size h times minimum size inverter is given by:

oo

o hCk

Ck

RhCk

ChRkT 7.04.07.0 intintint

%50

Ro Rint, Cint

Co

RC Load C Load

Bakoglu and Meindl…• By setting dT/dk = 0 and dT/dh = 0, “optimal” values for k and

h are obtained

• Substituting these back, delay is given by

ooCRCRk

7.04.0 intint

o

o

CRCRh

int

int

2intint3.2 ood CRCRT

Bakoglu and Meindl…

• For long-distance interconnections, Cint is on the order of picofarads and Co is on the order of femptofarads, and Rint and R, have values around kilohms;

Therefore, RoCint>>RintCo, and the delay expression can be further simplified to

T =2.3RoCint

• As a result, repeaters can effectively "transform" the RC interconnection load into a capacitive load.

• Delay of a capacitive load is linearly proportional to l.←

APPENDIX: Parameters affecting interconnect performance

• Dielectric• Width

of Interconnect• Diffusion Barrier• Length• Pitch• Aspect Ratio

• Parallel plate equation: C = εA/ Xox

• Dielectric constant– ε= kε0

– ε0 = 8.85 x 10-14 F/cm

– k = 3.9 for SiO2

• To reduce capacitance, we need to use low-k dielectrics– k 3 (or less)

• But, low-k materials have lower thermal conductivity• leads to significant metal-temperature

Parameters affecting interconnect performance

• Width of Interconnect

• Dielectric • Diffusion Barrier• Length• Pitch• Aspect Ratio

Pitch = w + s

But,

←

Parameters affecting interconnect performance

• Diffusion Barrier• Dielectric• Width

of Interconnect• Length• Pitch• Aspect Ratio

• Reduction of copper cross-sectional area– Cu atoms diffuse into silicon and

damage FETs– Must be surrounded by a diffusion

barrier– So, ρ increases

• Barrier thickness doesn’t scale rapidly as the interconnect dimensions because of reliability constraints

Parameters affecting interconnect performance

• Dielectric• Aspect Ratio• Width

of Interconnect• Diffusion Barrier• Pitch• Length

• Aspect ratio: AR = h/w– Old processes had AR << 1– Modern processes have

AR 2• h>>w

• C = ε.(wl)/h• R = ρl/tw

Global interconnect lengths remain the same.

Challenges of VLSI interconnects in deep sub-micron technologies

• Surface Scattering

• Grain Boundary effect

• Barrier Width

MFP of e- in Cu = 40 - 100 nm

These effects lead to the increase in ρo- increases from 1.9μΩ-cm to 4.9μΩ-cm @ 45nm [25] →

• The 50% delay of Y(t) is essentially the median point of the impulse response.• If H(t) is symmetric, the 50% delay is accurately –m(1)

(the first moment of the impulse response). This is Elmore delay.

[17]

←

APPENDIX: Kinetic Inductance

• The total energy associated with electric current is

In normal wires, the energy stored in the magnetic field is significantly larger than the kinetic energy of electrons, and the second integral is negligible.

• Kinetic inductance per unit length is given by

• Reactive impedance is always going to be negligible compared to its resistance. Resistance per unit length is

where τ is the average collision time for carriers.• Kinetic inductance for a carbon nanotube becomes important as the mean free

path of electrons can be very large.

←

APPENDIX: Quantum Capacitance

• To add electric charge to a quantum wire, one must add electrons to available states above the Fermi level (Pauli Exclusion Principle). The required energy to add electric charge Q to a quantum wire is

where the first term is the energy stored in the electric field (CE is the electrostatic capacitance) and e is electron charge.

• By equating this energy to an effective capacitance, the expression for the quantum capacitance (per unit length) is obtained as shown

and has a value in the order of 100 aF/m, in the same order of the electrostatic capacitance of a typical wire above a ground plane.

• As a CNT has four conducting channels as described in the previous sub-section, the effective quantum capacitance resulting from four parallel capacitances cQ is given by 4cQ.

←

APPENDIX

• As rise times decrease the bandwidth of the signal increase, as more no. of higher frequency components (harmonics) need to be accompanied into the signal to achieve this rise-time.

• approximation: BW = 0.35/RT• So, the effective frequency of a 100 MHz wave is 1GHz if only 10 harmonics are

taken.