Interconnect Routing in VLSI

Glauco Borges Valim dos Santos - FUCAS - GME - II - UFRGS - 2004

Considering two metal layers available for doing that - Metal2 and Metal3 (cells would be using only Poly and Metal 1) a topology for this net could be like this ...

met2met3via

With the gates the layout would be:

metmet3via

INV

NOR

NANDB

NANDA

The net is now connected

INV

NOR

NANDB

NANDA

But notice that a Metal 2 segment overlaps with the INV output, turning it unreachable by other connections

INV

NOR

NANDB

NANDA

This in undesirable and is one of the basic routing constraints: do not overlap other nets terminals

INV

NOR

NANDB

NANDA

If we change the layers preferred directions the topology goes like this, and the INV output is overlapped by Metal 3, what makes it still available in Metal 2

INV

NOR

NANDB

NANDA

But this time we’ve switched the via witch use to connect the NANDA output to metal 3, for three other vias in the other gates inputs, in order to make them available to the superior metal layer

INV

NOR

NANDB

NANDA

Vias are resistive, increasing signal propagation delay and should be avoided. What takes us to another basic routing constraint: to reduce the number of vias

Now take a look at this alternative topology. Fot this net topology, lower level connections do not overlap each other making them unreachable

And the number of vias is the same of the first case we considered, only four

And also!!! The total wire area is smaller them the previous topologies. Witch means smaller capacitance to be loaded by the driver output

And this may be the main routing constraint: to reduce wiring area, or wirelength

Although we have focused our attention to a single net until now…

… the routing problem lye over several other nets whose share the same routing area.

There are several other cells …

… with their respective pins …

… and they all should be properly connected.

Routing result by Parrot Tool Set. Screenshot from Yacif Viewer

The full layout for this example goes like this

Routing result example from Cadence Silicon EnsembleTM

Cells Internal layout is not available, only black boxes hiding the intelectual propriety of AMS STD Cell Designers

Highlighted the Filler-Cells (spaces) used for making feasible the routing step (subject for the 2nd part of this tutorial)

Please

feedback-me:

gbvsantos@inf.ufrgs.br