EDK BFM Simulation - Xilinx · 2019-10-18 · EDK BFM Simulation 5 UG254 (v1.0) July 18, 2006 R Preface About This Guide This tutorial is an introduction to using EDK Bus Functional

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EDK BFMSimulation

Tutorial

UG254 (v1.0) July 18, 2006

EDK BFM Simulation www.xilinx.com UG254 (v1.0) July 18, 2006

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© 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

07/18/06 1.0 Initial Xilinx release.

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http://www.xilinx.com

EDK BFM Simulation www.xilinx.com 3UG254 (v1.0) July 18, 2006

Preface: About This GuideAdditional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

EDK BFM Simulation TutorialEDK BFM Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Getting Started with BFM Simulation of Processor IP . . . . . . . . . . . . . . . . . . . . . . . . . 9Using GNU m4 to Generate BFM Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12BFM Simulation of OPB PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table of Contents


4 www.xilinx.com EDK BFM SimulationUG254 (v1.0) July 18, 2006

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Preface

About This Guide

This tutorial is an introduction to using EDK Bus Functional Model (BFM) simulation toverify existing processor IP cores. The tutorial contains four sections:

• EDK BFM Install covers installation of the files needed for EDK BFM simulation.

• Getting Started with BFM Simulation of Processor IP is an introduction to EDK BFMsimulation. The BFM simulation uses the OPB GPIO core.

• Using GNU m4 to Generate BFM Stimuli is a tutorial on the use of m4 to generateBFL, for those readers who would like to generate their own BFL stimuli.

• BFM Simulation of OPB PCI illustrates a BFM simulation of OPB PCI configuration,reinforcing BFM simulation concepts.

The online tutorial files are located at:

http://www.xilinx.com/bvdocs/desfiles/ug254.zip

Additional ResourcesTo find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature.

To search the Answer Database of silicon, software, and IP questions and answers, or tocreate a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

ConventionsThis document uses the following conventions. An example illustrates each convention.

TypographicalThe following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier fontMessages, prompts, andprogram files that the systemdisplays

speed grade: - 100

Courier boldLiteral commands that you enterin a syntactical statement

ngdbuild design_name


http://www.xilinx.com/literature

http://www.xilinx.com/support

http://www.xilinx.com/bvdocs/desfiles/ug254.zip


Preface: About This GuideR

Online DocumentThe following conventions are used in this document:

Helvetica bold

Commands that you select froma menu

File → Open

Keyboard shortcuts Ctrl+C

Italic font

Variables in a syntax statementfor which you must supplyvalues

ngdbuild design_name

References to other manualsSee the Development SystemReference Guide for moreinformation.

Emphasis in textIf a wire is drawn so that itoverlaps the pin of a symbol, thetwo nets are not connected.

Square brackets [ ]

An optional entry or parameter.However, in bus specifications,such as bus[7:0], they arerequired.

ngdbuild [option_name]design_name

Braces { }A list of items from which youmust choose one or more

lowpwr ={on|off}

Vertical bar |Separates items in a list ofchoices

lowpwr ={on|off}

Vertical ellipsis...

Repetitive material that hasbeen omitted

IOB #1: Name = QOUT’IOB #2: Name = CLKIN’...

Horizontal ellipsis . . .Repetitive material that hasbeen omitted

allow block block_name loc1loc2 ... locn;



Blue textCross-reference link to a locationin the current document

See the section “AdditionalResources” for details.

Refer to “Title Formats” inChapter 1 for details.

Red textCross-reference link to a locationin another document

See Figure 2-5 in the Virtex-IIPlatform FPGA User Guide.

Blue, underlined text Hyperlink to a website (URL)Go to http://www.xilinx.comfor the latest speed files.



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EDK BFM Simulation Tutorial

EDK BFM InstallThe files needed to run Bus Functional Model Simulation in EDK are installed and tested inthis section using the following outline.

• Install the files needed to run a BFM simulation• Identify the directory structure of BFM files within EDK• Run BFM simulations on an existing PIP core

EDK BFM simulation of PIP Cores is supported using ModelSim™ and NcSim™simulators, and runs on Linux and Windows™ operating systems. The instructions in thisapplication note are most often given using Windows and ModelSim environment. Ifassistance is needed adapting the instructions for use with Linux/NcSim, please contactXilinx. Unless specified otherwise, the commands in this application note are executed atthe command/Linux prompt.

EDK BFM simulation allows simulation of bus transactions on either the Processor LocalBus (PLB) or On-Chip Processor Bus (OPB), IBM CoreConnect™ buses. A license isavailable from

http://www.xilinx.com/ipcenter/processor_central/register_coreconnect.htm

Figure 1-1: BFM Installation directories

The UG254.zip file contains install_files, m4_exercises, and design directories. Figure 1-1provides the BFM installation directories within EDK.

Run the following steps. All files are provided in ug254.zip.

1. Run bfm_8.1.exe, a self-extracting ZIP file, from the command prompt.

2. Verify that the $XILINX_EDK/hw/XilinxBFMinterface/pcores directorycontains the BFM models. Verify that $XILINX_EDK/bin/nt/xilbfc.exe exists.

<EDK>/gnu/m4/bin/nt/ - gen_bfl_do, gen_bfl_do

<EDK>/gnu/m4/ - proc_defs_opb.m4, proc_defs_plb.m4

<EDK>/hw/XilinxBFMInterface/pcores - BFM simulation models

http://www.xilinx.com/ipcenter/processor_central/register_coreconnect.htm



EDK BFM InstallR

3. Copy edk_bfm.zip to the $XILINX_EDK (%XILINX_EDK%) directory. UnZIPedk_bfm.zip.

4. Verify that $XILINX_EDK/gnu/m4 contains the proc_defs_opb.m4 andproc_defs_plb.m4 files, and that $XILINX_EDK/gnu/m4/bin/nt containsm4.exe. m4 is generally available in Linux distributions, so it does not need to beinstalled.

5. Verify that the$XILINX_EDK/hw/XilinxBFMinterface/pcores/xil_bfm_v1_00_a/hdl/vhdl directory contains the xil_bfm_pkg.vhd file.

6. Add $XILINX_EDK/gnu/m4/bin/nt to $PATH.

7. Invoke XPS and (re)compile the Unisim, Simprim, XilinxCorelib, and Smartmodellibraries. This is needed so that the BFM models are compiled into the BFM libraries.Select Simulation → Compile Simulation Libraries. Select the simulator and HDL.When prompted by the GUI, enter the path to the libraries as shown in Figure 2 andclick Compile.

8. Verify that the modelsim.ini just created in the EDK_Lib directory contains theopb_bfm and plb_bfm libraries. The content of this modelsim.ini needs to beincluded in the active modelsim.ini file. If there are no special libraries in the currentlyactive modelsim.ini, this is done by copying EDK_Lib/modelsim.ini to$MODEL_TECH/win32.

Note: If this modelsim.ini does not have the following libraries, add them:

std = $MODEL_TECH/../stdieee = $MODEL_TECH/../ieeeverilog = $MODEL_TECH/../verilogvital2000 = $MODEL_TECH/../vital2000std_developerskit = $MODEL_TECH/../std_developerskit

Figure 2: Compiling Simulation Libraries

ug254_01_051706



EDK BFM InstallR

synopsys = $MODEL_TECH/../synopsysmodelsim_lib = $MODEL_TECH/../modelsim_lib

To use the PPC405 Smartmodel, uncomment/comment lines in modelsim.ini as below.

libsm = $MODEL_TECH/libsm.sl

libswift = $LMC_HOME/lib/pcnt.lib/libswift.sl

; Veriuser = veriuser.sl

9. Create the edk_bfmsim_tutorial/m4_exercises directory,

10. enter m4 at the command prompt.

11. Enter Hi Mom. m4 echoes Hi Mom.

12. Enter m4exit.

13. Change to the edk_bfmsim_tutorial/opb_gpio/bfmsim directory. Briefly readthe contents of the following files used in BFM simulation:

pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio_tb.vhd

scripts/run.do

scripts/m4/opb_gpio_defs.m4 (opb_gpio.m4)

14. Since ISE libraries (Unisim, Simprim, Coregen) were compiled in step 7, theopb_gpio/simgen.opt file does not need the -X option. Verify that the -E argumentin simgen.opt points to EDK_Lib. From the opb_gpio/bfmsim directory, run:

simgen -f simgen.opt

This creates the simulation models for OPB GPIO.

15. Change to the opb_gpio/bfmsim/simulation/behavioral directory. Optionallyremove all EDK libraries in the bfm_system.do file already mapped in themodelsim.ini file. To do this, remove lines containing duplicated EDK maps(usually 7–31) in bfm_system.do. Add the following lines to the beginning of thebfm_system.do file:

vlib xil_bfm_v1_00_a

vmap xil_bfm_v1_00_a xil_bfm_v1_00_a

vcom -93 -work xil_bfm_v1_00_a $XILINX_EDK/hw/XilinxBFMinterface/pcores/xil_bfm_v1_00_a/hdl/vhdl/xil_bfm_pkg.vhd

Use the hard-coded path for $XILINX_EDK (e.g., C:/EDK8.1).

16. From the opb_gpio/bfmsim/simulation/behavioral directory, comment or removethe C_AR0_BASEADDR/C_AR0_HIGHADDR generics from my_core_wrapper.vhdfile. To do this, add comments to lines 54, 55, 97, 98, and remove the semicolons onlines 53, 96.

17. From the opb_gpio/bfmsim/scripts/m4 directory, run from the commandprompt:

gen_bfl_do opb_gpio

This creates the opb_gpio.bfl and opb_gpio.do files, and moves them up onedirectory to the scripts directory.

18. Invoke ModelSim. From the opb_gpio/bfmsim/simulation/behavioraldirectory, run:

do ../../scripts/run.do



Getting Started with BFM Simulation of Processor IPR

This errors out since the wave.do isn’t complete. Add signals of interest to the waveformviewer, save the wave.do, and re-run.

19. Verify that the simulation results are displayed in the waveform viewer.

20. Make a change to the value of a generic, and rerun the simulation. Fromopb_gpio/bfmsim/scripts/m4, change the C_IS_DUAL generic inopb_gpio_defs.m4.

21. Run:

gen_bfl_do opb_gpio

In the VHDL testbench, change the C_IS_DUAL generic inopb_gpio/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio_tb.vhd on line107.

22. In ModelSim, from opb_gpio/bfmsim/simulation/behavioral, rerun:


Getting Started with BFM Simulation of Processor IPThe OPB GPIO Processor IP core is simulated in this section using the following outline:

A. Identify when stimuli are provided and checked from the OPB side

B. Identify when stimuli are provided and checked from the I/O side

C. Describe the synchronization used to transfer control between the BFL and the VHDLin BFM simulation

Figure 3 is a functional diagram of BFM simulation of a Processor IP core. The BFM ismodeling the microprocessor — either PPC405 or MicroBlaze — which is communicatingto the Processor IP using either the PLB or OPB. The VHDL testbench interfaces to theProcessor IP core ports, which connect to external pins on the FPGA, GPIO_IO_I, andGPIO_IO_O. The C_IS_DUAL generic defines whether a single or dual GPIO is included inthe core. When configured as a single GPIO, the two registers in the OPB GPIO are DATAand TRI, located at C_BASEADDR + 0x0 and C_BASEADDR + 0x4, respectively.

Run a BFM simulation of the OPB GPIO using the steps below.

1. Briefly read the following files:

opb_gpio/bfmsim/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio_tb.vhd

opb_gpio/bfmsim/scripts/m4/opb_gpio_defs.m4

opb_gpio/bfmsim/scripts/m4/opb_gpio.m4

The VHDL testbench, opb_gpio_tb.vhd, provides stimuli to and checks results from theI/O side. The two m4 files, opb_gpio_defs.m4 and opb_gpio.m4, provide stimuli toand check results from the microprocessor side. The opb_gpio_defs.m4 file providesthe symbolic names and addresses for the registers in the OPB GPIO core.

Figure 3: BFM Simulation

BFMProcessor

IPVHDL

Testbench

ug254_02_051706




In the next steps, use the waveform viewer to verify the content of the DATA and TRIregisters.

2. From the edk_bfmsim_tutorial/opb_gpio/bfmsim/simulation/behavioraldirectory, run:


3. As illustrated in Figure 4, verify the reset operation. Reset is done from the OPB side.Verify that from 450 ns to 650 ns, the BFM lines read 0x00000000 and 0xFFFFFFFFin the DATA and TRI registers. Control is transferred to the VHDL testbench, whichwrites the status message to the simulator transcript window indicating that the resetoperation is performed.

Figure 4: OPB GPIO Resetug254_03_051706




4. As illustrated in Figure 5, verify the read operation. From 350 ns to 650 ns,opb_gpio.m4 prompts the VHDL testbench to generate input stimuli intoGPIO_IO_I. The synchronization pulses occur at 350, 450, 550, and 650 ns. The0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, and 0x00000000 input stimuli aregenerated by the testbench at 360, 460, 560, and 660 ns. Control is transferred to theBFL, and the BFM verifies that the data register contains the data received from theGPIO_IO_I inputs at 410, 510, 610, and 710 ns. Control is transferred between the BFMand VHDL by the pulses on synch_in/synch_out at the top of the waveform viewer.

5. As illustrated in Figure 6, verify the write operation. From 750 ns to 1000 ns, thesimulation verifies that the GPIO writes data correctly to the GPIO_IO_O outputs. Theopb_gpio.m4 writes 0x00000000, 0xFFFFFFFF, and 0x00000000, at 770, 860, and940 ns. The opb_gpio_tb.vhd verifies this data at the GPIO_IO_O output pins.

Figure 5: OPB GPIO Read Operation

Figure 6: OPB GPIO Write Operation

ug254_04_051706

ug254_05_051706



Using GNU m4 to Generate BFM StimuliR

6. As illustrated in Figure 7, verify the interrupts in the OPB GPIO. From 1660 ns to2000 ns, the simulation verifies that the interrupts function correctly. In the GPIO, aninterrupt is generated when there is a change in input value on the GPIO_IO_I pin. TheInterrupt Service Register (ISER) is reset at 1580 ns. The BFM receives an interrupt at1840 ns. The BFM reads the ISR at 1940 ns.

7. (Optional) Add code to opb_gpio.m4 and opb_gpio_tb.vhd to write0xF0F0F0F0 from the OPB, check results at the GPIO_IO_0, and display a messageindicating the test done.

8. (Optional) Add code to opb_gpio.m4 and opb_gpio_tb.vhd to generate0xFFFF00000 at GPIO_IO_I, check the results, and display a message indicating thetest done.

Using GNU m4 to Generate BFM StimuliThe first step in understanding BFM stimuli is to read the core_defs.m4 and core.m4 filesfor several cores. Much of the m4/BFL stimuli is based on the following two commands:

read_word(register_symbolic_name, expected_value)

write_word(register_symbolic_name, write_value)

This section provides exercises to understand the details of m4. Arecommended pre-requisite is reading completed m4 files of existing Processor IP cores. The GNU m4 macroprocessor generates Bus Functional Language (BFL) stimuli for simulation using BusFunctional Models (BFMs). The tasks in this section are given below.

• Run GNU m4 interactively and in batch mode

• Read m4 constructs used in generation of BFM stimuli

• Read m4 constructs used to verify stimuli generated by HDL

• Generate BFM stimuli using m4

Figure 7: OPB GPIO Interrupts

ug254_06_051706




Figure 8 shows the flow for generating BFM stimuli. Stimuli in m4 is easier to read andwrite than stimuli in BFL or do files. One obstacle in learning m4 is getting accustomed toreading and writing the forward and backwards ticks, and interpreting their use. The m4interactive mode is a good method for learning m4. Change to theedk_bfmsim_tutorial/m4_exercises directory, enter m4, and run the following commandsin interactive mode.

1. Generate the concatenation of 00000000 and FFFFFFFF.

00000000`’FFFFFFFF

2. Find the length of the string “Xilinx”.

len(`Xilinx’)

3. Find the index number of the first occurrence of the string “li” in the string “Xilinx”.

index(`Xilinx’,`li’)

4. Write the string “yo” in “Toyota” using the substr macro.

substr(`Toyota’,2,2)

5. Replace the X character in Xilinx with Z.

translit(`Xilinx’,`X’,`Z’)

6. Run incr(4).

7. Find the results of the following arithmetic macros.

eval(-3*5)

eval(eval(2+4)*2)

eval(5+5,16)

eval(5+5,16,8)

eval(5+5,2)

8. Run the following macros by first including the proc_defs_opb.m4 file. Theproc_defs_opb.m4 file is used in exercises 7-15.

include(`proc_defs_opb.m4’)

make_num

9. Run the following macros.

strip_hex(0xFFFFFFFF)

strip_hex(make_num)

strip_hex(make_num)`’strip_hex(make_num)

make_num`’make_num

Figure 8: Generating BFM Stimuli

m4 BFC

core_defs.m4

Simulator

ug254_07_051706

core.do<core>.m4





define(`C_BASEADDR’, `0x30000000’)

add_offset(C_BASEADDR, 0x10C)


calc_be(0x00000004,word)

calc_be(0x00000004,halfword)

calc_be(0x00000004,byte)

12. Run the following codes.

def_reg(`CAP’,` 0x3000010C’)

CAP


read_word(0x0000000C, 0x12345678)

read_word(0x0000000A,0x12345678, `req_size=4, req_delay=5’)

read_half(0x0000000A, 0x12345678)

read_byte(0x00000005, 0x12345678)

write_word(0x0000000C,0x12345678)

write_word(0x000000A, 0x12345678,`req_size=4,req_delay=5’)

write_half(0x0000000A, 0x12345678)

write_byte(0x00000005,0x12345678)


forloop(i,0,2,èval(i) ‘)

forloop(i,0,2,èval(i) ‘)

foreach(i,(1,5,17,4), èval(i)’


assert_in

assert

start

set_dev

set_device(device1)

set_device(monitor)

16. Run the following code.

ALL_ONES_WORD

ALL_ONES_BYTE_0

ALL_ZEROES

17. Create the following new macros. (The proc_defs_opb.m4 is not used in theseexercises.)

define(`go’, `hello world’)

go

18. Create a multiply macro.

define (`multiply’,èval(2*4)’)

multiply

define(`multiply’,èval($1*$2)’)

multiply(2,2)

19. Create a macro called concatenate.

define(`concatenate’,$1`’$2)

concatenate(cup,cake)



BFM Simulation of OPB PCIR

20. Run the following m4 batch commands from the m4_exercises directory.

m4 my_makenum.m4

m4 ifelse.m4

m4 forloop.m4

m4 interrupt.m4

21. Run the following m4 commands.

m4 opb_gpio_defs.m4

m4 opb_gpio.m4 > opb_gpio.bfl

Read the file opb_gpio.bfl

22. Run the following m4 command and note the functionality of the divert commands.

m4 test_divert.m4

23. Run the following m4 command and note the reset functionality.

m4 opb_gpio_reset.m4

24. Change the C_IS_DUAL generic to 1, rerun the command above, and observe theoutput.

25. Run the following m4 command and describe how stimuli is generated from the IO(not the OPB) side.

m4 stimulate_gpio_ins.m4

Note: This illustrates that the BFL must request that the VHDL generate this stimuli. Thesynchronization signals required for this operation are shown.

26. Run the following m4 command and describe how stimuli are generated from the OPBside.

m4 stimulate_gpio_outs.m4

27. Change the C_IS_DUAL generic and rerun the command.

28. Run the following command and describe how interrupts are tested in the OPB GPIO.

m4 test_gpio_interrupts.m4

BFM Simulation of OPB PCIIn this section, run a BFM simulation of OPB PCI configuration. Analyze the results in thewaveform viewer in terms of the VHDL stimuli and BFL stimuli.

1. Optionally read the following three files to determine when stimuli are applied andresults are checked.

opb_pci/bfmsim/pcores/opb_pci_v1_02_a/hdl/vhdl/opb_pci_tb.vhd

opb_pci/bfmsim/scripts/m4/opb_pci.m4

opb_pci/bfmsim/scripts/m4/opb_pci_defs.m4

Table 5, “OPB PCI Bus Interface Registers” in the OPB PCI Full Bridge Product Specification(DS437) provides register abbreviations and locations.

2. From opb_pci/bfmsim/scripts/m4 directory, run

gen_bfl_do opb_pci

cd opb_pci/bfmsim/simulation/behavioral


3. In ModelSim, run

View → Structure

View → Signals

http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_pci.pdf




4. Add the generics, and OPB and PCI Bus signals to the waveform viewer.

5. Add V3 signals to the waveform viewer.

6. Run the simulation and determine the simulation time at which the PCI bus is reset.

7. Determine the simulation time at which the CSR is written.

Figure 9 shows the waveform viewer output from a simulation of the configuration of theOPB PCI. The simulation time shown is 2000 ns – 3000 ns. This illustrates the bustransaction that writes the Command Status register in the OPB PCI core.

Figure 9: Configuring the OPB PCI

00000000 3000010C 3000010C 30000110 00000000 30000110

04000080 00000000 00000000 00000000 FFFFFFFF

1111 1111 1111 0000 1111

FFFFFFFF 00010004 FFFFFFFF FFFFFFFF 02000000

1c_include_pci_config

16c_bridge_idsel_addr_bit

1c_num_idsel

0c_include_devnum_reg

opb_clk

opb_abus

opb_dbus 00000000

opb_rnw

opb_be 0000 0000 0000

opb_select

pci_xferack

pci_toutsup

ad FFFFFFFF FFFFFFFF

cbe F F A 0 F

idsel

idsel_int

idsel

frame_n

trdy_n

irdy_n

stop_n

devsel_nug254_08_051706





Documents

EDK BFM Simulation - Xilinx · 2019-10-18 · EDK BFM Simulation 5 UG254 (v1.0) July 18, 2006 R Preface About This Guide This tutorial is an introduction to using EDK Bus Functional