Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu

Design Considerations in CLBs for Deep Sub-Micron

Technologies


Technologies

Louis Alarcón

Octavian Florescu

MotivationMotivation

As technology scales…

– The effects due to process variations will become more pronounced.

• Regular structures are needed to mitigate these effects.

– Leakage will increase as the VTH are scaled.• Low leakage architectures will be needed to

control stand-by power.

Configurable Logic BlockConfigurable Logic Block

• Stack– Regular– Low Leakage– Slow due to RC

delay

• Current Sensing– Recover

performance loss through smaller voltage swings.

DataInputs

S S

OUT

OUTCLK

ProgramBits

PassTransistor

Stack

PassTransistor

Stack

Current Sense

Current Sense

RootInput

A

B S

S

P0

Programming(P0, P1, P2, P3)

Logic

to senseampA

B

B

B

The StackThe Stack

• Inverted multiplexer tree

• “pseudo-differential” currents at the outputs

• Data inputs: 4• Program bits: 16

ION

IOFF 0V1

V2

IBIAS

I1

V = V1 - V2 > 0

V1V2

ION IOFF

CLB

V1 V2

ION IOFF

DCVSL-basedSense Amplifier

(DCVSL-SA)

Clamped Bit-LineSense

Amplifier(CBL)

ConditionalPrecharge

Sense Amplifier

(CP)

Sense Amplifier TopologiesSense Amplifier Topologies

ION

IOFF 0V1

V2

IBIAS

I1

V = V1 - V2 > 0

V1V2

ION IOFF

CLB

V1 V2

ION IOFF


(DCVSL-SA)


Amplifier(CBL)


Sense Amplifier

(CP)


ION

IOFF 0V1

V2

IBIAS

I1

V = V1 - V2 > 0

V1V2

ION IOFF

CLB

V1 V2

ION IOFF


(DCVSL-SA)


Amplifier(CBL)


Sense Amplifier

(CP)


ION

IOFF 0V1

V2

IBIAS

I1

V = V1 - V2 > 0

V1V2

ION IOFF

CLB

V1 V2

ION IOFF


(DCVSL-SA)


Amplifier(CBL)


Sense Amplifier

(CP)


EDP and LeakageEDP and Leakage

CMOS

TG

CBL

CP

DCVSL-SA

Looks too good to be true? It probably is…

EDP

CMOS

TG

CBL

CP

DCVSL-SA

Leakage Current

CLB(Stack)

CLB(Stack)

CPSA

CPSA

ION

IOFF

VSA

RootInput

ION VSA

Process Variation and MismatchProcess Variation and MismatchV should be > 0 for proper sensing

ION,min neededby the senseamplifier

upsize

Sizing for YieldSizing for Yield

CBL CP

DCVSL-SA

CBL

CP

DCVSL-SA

EDP Leakage Current

Yield Target: 99% (Monte Carlo process and mismatch simulations)• needs to be verified in silicon

Constant Yield LinesConstant Yield Lines

• Solid line has a 99% yield over all process corners.– Overkill?

• The yield increases as VDD increases

CP (Upsized)CLB: 10xCP Sense Amp: 2x

CP

EDP CP

PerformanceLoss


• Dash-dotted line represents a constant Yield Line.

• Size of CLB tailored to desired Yield and VDD.

99% yield line

A

B


CP

YieldB = YieldA

EDP CP


99% yield line


CP

EDP CP

CMOS

TG

CP

Upsized EDP

YieldB = YieldA

A

B


CBL 99% line

A

B

CBL (Upsized)

CBL

YieldB = YieldA

EDP CBL

CMOS

TG

CBL

CP

Upsized EDP


DCVSL-SA 99% line

A

B

DCVSL-SA (Upsized)

DCVSL-SA

YieldB = YieldA

EDP

CMOS

TG

CBL

CP

DCVSL-SA

Upsized EDP

EDP and YieldEDP and Yield

CMOSTG

CBLCP

DCVSL-SA

EDP(w/o sizing for yield)

CMOS

TG

CBL

CP

DCVSL-SA

EDP (constant yield)

EDP and YieldEDP and Yield

CMOSTG

CBLCP

DCVSL-SA

EDP(w/o sizing for yield)

CMOS

TG

CBL

CP

DCVSL-SA

EDP (constant yield)

High V

oltage Space

• DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations.

However…• More difficult to design

– Analog-like design process

• Less versatile– Mandatory latch at the output– DVS

• Higher design risk– 6 unacceptable

Summary of ResultsSummary of Results

CMOS

TG

CBL

CP

DCVSL-SA

EDP (constant yield) CMOS

TG

CBL

CP

DCVSL-SA

Leakage Current

Summary of ResultsSummary of Results

• DCVSL-SA best performing SA, and competitive with current TG and CMOS implementations.

However…• More difficult to design

– Analog-like design process

• Less versatile– Mandatory latch at the output– DVS

• Higher design risk– 6 unacceptable

Sense Amplifiers in Future Technologies

Sense Amplifiers in Future Technologies

• Design of Sense Amplifiers in the future will become more challenging.– Impact of process variations will become more

pronounced

– VDD will continue to scale VSA/VDD increases

VTH/VDD increases

• The useful design space will be limited.– Low leakage environments– High voltage, low energy space

Thank youThank you


Technologies


Technologies

Louis Alarcon

Octavian Florescu

Energy – DelayEnergy – Delay

CMOS

TG

CBL

CP

DCVSL-SA

CBL

CP

DCVSL-SA

Low Threshold VoltageLow Threshold Voltage

CMOS

TG

CBL

CP

DCVSL-SA

Documents

Design Considerations in CLBs for Deep Sub-Micron Technologies Louis Alarcón Octavian Florescu