Interconnect Length Estimation in VLSI Designs: A Retrospective

MASSOUD PEDRAMUNIVERSITY OF SOUTHERN CALIFORNIA

Interconnect Length Estimation in VLSI Designs: A

Retrospective

Motivation and Problem Definition

Interconnect represents an increasingly significant part of total circuit delay Longer interconnect is more significant

Interconnect is accurately known only after place/route This leads to timing closure problems Logic design is now coupled with physical design

Interconnect must be considered during: Floorplanning, synthesis, timing verification

We need to be able to predict the length of individual wires before layout, say during technology mapping

Previous Work

Previous work in this area: Pedram and Preas, ICCD-89

Average wire length for given pin-count Heineken and Maly, CICC-96

Wire-length distribution Hamada, Cheng, and Chau, TCAD 1996

Average wire length for given pin-count Srinivas Bodapati, Farid N. Najm, TVLSI 2001 Andrew Kahng and Sherief Reda, SLIP 2006 Dirk Stroobandt Others …

Key Ideas

The number of pins on a net (denoted Pnet) is known to affect net length

The first level neighborhood (denoted Nh1(i) ) of a given net i is defined as: The set of all other nets connected to cells to which

this net is also connectedThe second level neighborhood (denoted

Nh2(i) ) of a given net i is defined as: The union of all first level neighborhoods of nets that

are in the first level neighborhood of this net

Mohammad Javad Dousti and Massoud Pedram(DAC 2013 Paper)

LEQA:Latency Estimation for a Quantum

Algorithm Mapped to a Quantum Circuit Fabric

Related Papers

M. Pedram. B. T. Preas, "Accurate prediction of physical design characteristics of random logic," Proc. of Int'l Conference on Computer Design: VLSI in Computers and Processors, Oct. 1989, pp. 100-108.

M. Pedram. B. T. Preas, "Interconnection length estimation for optimized standard cell layouts," Proc. of Int’l Conference on Computer Aided Design, Nov. 1989, pp. 390-393.

Overview

Introduction & Motivation Problem Statement Preliminaries

Quantum Operation Dependency Graph (QODG) Universal Logic Blocks (ULBs)

Estimating the Latency of a Quantum Algorithm Average Routing Latency for CNOT Gate

LEQA Performance Experimental Results Conclusion

Introduction & Motivation

Total execution time of a software depends on 1. Processor architecture,2. Circuit design, 3. Place and route.

Several estimation methods for the estimation of a software execution time without running it on a specific processor/processor simulator is proposed.

The same paradigm exists for quantum computers:Calculating the exact latency of a quantum algorithm is an expansive proposition since it needs scheduling and placement of quantum operations and routing of qubitsThe exact answer has no use since there is no real-size quantum computer out there!

However, the latency estimation of the mapped quantum circuit still has many applications: Early algorithm/program analysis Helps quantum error correction code (QECC) designers to account enough amount of

resources for QECCs

Problem Statement

Given: A quantum circuit Size of the fabric (width×height) Logical gates delays The capacity of routing channels Speed of a logical qubit through the routing channels

Estimate the latency of the mapped quantum circuit to the quantum circuit fabric.

Preliminaries (1):Quantum Operation Dependency Graph (QODG)

In QODG, nodes represent quantum operations and edges capture data dependencies.

start 1 132 3 4 5 6

14 15 16 17

QODG of ham3 circuit

3-Input Toffoli Gate

H T† T T H

1 2 3 4 12865 10

18T† 7

11 1715 1916

Synthesized ham3 circuit

Preliminaries (2): Universal Logic Blocks (ULBs)

To avoid dealing with complexity, Tiled Quantum Architecture (TQA) is used which is composed of a regular two-dimensional array of ULBs.

ULB ULB

ULBULB

ULBULB ULBULB

A 3×3 Tiled Quantum Architecture (TQA)

Each ULB can perform any FT quantum operations.

ULBs are separated by the routing channels, which are needed to move logical qubits from some source ULBs to a target ULB in the TQA.

CNOT T†

TH T† T 1 2 3 4 5

Estimating the Latency of a Quantum Algorithm

Delay of a quantum algorithm can be formulated as follows:

where is the set of one-qubit FT operations (such as H, T, S,

etc.); and are the number of CNOTs and operations of type

on the critical path; and determine the delay of CNOT and operation of

type respectively; and capture the average routing latency for input

qubits of the CNOT and the input qubit of the operation of type .

Tech, QECC, &QC dependent

values

Easy; Empirically set to 2×Tmove

Main challenge!

A computationally efficient model for estimating the average qubit routing latency for CNOT gates is developed.

The model comprises a number of sub-models dealing with Possible placement locations of each qubit captured as a “presence zone” Congestion in the routing channels captured by “zone overlaps” Intra-zone routing modelled as “shortest Hamiltonian path”

A procedural method, combining the sub-models together to estimate the Qubit routing latency for CNOT gates.

Average Qubit Routing Latency for CNOT Gate

Highly Congested

5 presence zones

Estimating Average Routing Latency for CNOT (

Since the result of the placement is not known a priori, the zones are assumed to be placed randomly (uniformly and independently) on the fabric. can be estimated as

where is the total number of logical qubits in the target quantum

circuit; is the expected area of the quantum circuit fabric which is

covered by exactly overlapping presence zones; is the average routing latency of a qubit when the routing

channels are occupied by qubits; and is the area of the circuit fabric and it is equal to the total

number of ULBs assuming that each ULB is a square.

Should be estimated

Estimating the Expected Covered Surface ()

is the probability that the ULB at position (x,y) on the fabric is covered by a qubit’s presence zone, which is itself randomly positioned on the fabric;

where is the average area of presence zones.

x(0,0)

bb-y+1

Estimating Average Area of Presence Zones (B)

A weighted graph called interaction intensity graph (IIG(V,E)) is built as follows: Nodes of this graph are logical qubits which are denoted by . An edge is added between nodes and if these two qubits

interact with each other. is equal to the number of two-qubit operations between and .

Let denote the number of neighbors of node in the IIG(V,E). Clearly, .

B can be calculated by using a weighted average over the size of the presence zone of all logical qubits

The area of the presence zone associated with , which is denoted by , is calculated as

Average Routing Latency of a Qubit ()

where is the capacity of routing channels is the average routing latency of a qubit

where all routing channels are uncongested

Derivation of this comes

Derivation of the Average Routing Latency of a Qubit ()

Routing latency when can be modeled by an M/M/1/∞ queue. ( is the arrival rate)

Avg. Queue length:

Having the arrival rate and the avg. queue length, Little’s formula gives the average waiting time in the queue:

Ncq-Nc

Estimating

where represents the average routing latency of qubit in an average-size presence zone when the routing channels are uncongested.

One way to estimate is to randomly place qubits in the presence zone of qubit and calculate the expected length of the shortest Hamiltonian path () which goes through these qubits.

Estimating can be estimated By knowing the value of , can be calculated as

follows:

where is a tuning parameter and is a parameter depending on the physical characteristics of the fabric technology mostly the speed of moving a logical qubit through channels. is added to the denominator to give the average routing latency of an operation (i.e., a single edge length).

LEQA Performance

Runtime complexity of LEQA can be written as follows:

where is the number of vertices in the given

QODG which is equal to the number of operations plus two (including two dummy nodes)

is the number of edges in the given QODG is the number of qubits in the input circuit is the area of the TQA fabric

Polynomial in terms of input size (operation count, qubit count and fabric

Experimental Results (1)

LEQA is compared with a modified version of our previous work QSPR (DATE’12)

0123456789

gf2^16

gf2^18

gf2^19

gf2^20

gf2^50

1048576…

gf2^64

gf2^10

gf2^12

gf2^25

Benchmark

Average error is 2.11%

Worst case error;still low enough

Experimental Results (2)

Shor’s factorization algorithm for a 1024-bit integer has ~1.35×1010 logical operations. Using extrapolation, QSPR would compute the latency in ~2 years whereas LEQA needs only 16.5 hours!!

y = 2E-10x2 + 0.0004x + 2.1123R² = 0.9997

y = 4E-06x + 0.2347R² = 0.9973

0 200,000 400,000 600,000 800,000 1,000,000

Operation Count

Runtime Comparison between LEQA and QSPR (baseline)

QSPR Runtime

LEQA Runtime

115X speedup

78X speedup

y = 2E-10x2 + 0.0004x + 2.1123R² = 0.9997

y = 4E-06x + 0.2347R² = 0.9973

0 200,000 400,000 600,000 800,000 1,000,000

Operation Count

Runtime Comparison between LEQA and QSPR (baseline)

QSPR Runtime

LEQA Runtime

115X speedup

78X speedup

Conclusion

Persistence of Ideas

The method developed some 25 years ago applies today not to classical computing but also to quantum computing fabric

Gratitude of Scholars

We are who we are because of what we have learned from whom and what we have done since

Voice of Hearts

Friendship and collegiality are key

Interconnect Length Estimation in VLSI Designs: A Retrospective

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