Semiconductors have made real what our ancestors would consider magic. The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Intelligent systems are revolutionizing a variety of industries to help improve energy efciency, quality, and exibility of systems. To achieve these superior experience massive amount of researches are ongoing in the eld of algorithms, embedded HW/SW design, IP core design and SoCs. These are well backed up by govt policies, standards and industry forums. Incredible demand on functionality in a chip in a given power/thermal envelope forcing transistor geometries go smaller which is imposing newer challenges in VLSI design and associated EDA tools/ows/methodologies. In 33rd International Conference of VLSI Design and 19th International Conference on Embedded Design, we plan to bring together all the leaders from industries, academia, industry bodies, government, standard organizations to go over all technology enablers in an “outside-in approach to design VLSI” which includes intelligent systems design, new techniques in algorithms, HW/SW/Protocol standards, core VLSI design, EDA tools/ows/methodologies and core silicon technologies

Theme: Connecting Intelligent Systems to New Age Transistors

33rd International Conference on VLSI Design19th International Conference on Embedded Design

January 4 – 8 , 2020, Leela Palace, Bengaluru, India

Electronic Design Automation : Simulation Tools for Design Verication, SPICE Simulation, Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verication Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal Simulations, Transistor Level Tools, EDA on CloudTransistor Level Design: Silicon Technology Advancements, FinFET, Beyond FinFET, Transistor Level Performance Improvements, Device Microelectronics, Beyond Silicon, PVT Optimization, Design Optimization Corners, Yield Improvement, Post Tapeout Methodology

New Age Transistors and Tools/Flows/Methodology

Embedded Systems Design: ESL, System-level design methodology, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect Tolerant Architectures, Hardware/Software Co-Design & Verication, Recongurable Computing, Embedded Multicores SOC and Systems,Embedded Software Including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip,Articial Intelligence: Deep Neural Network, CNN, Computer Vision, On chip Neural Processing Engines, ML AlgorithmsSystem Level Algorithms and Architectures: Platform Architectures, Chip Partitioning, Power Management, Board Level Design, Packaging, Signal Integrity, Power/Thermal Trade OffHigh Performance Computing: Server Processor Architecture, Compute Efciency, Benchmark Enhancement, Edge Computing, Cloud Computing, Distributed Architecture, Heterogeneous ComputeEfcient Connectivity: Ethernet, Networking Algorithms, 5G, Communication Standards, LTE, SwitchingSecurity: Security Protocols, HW Security Design, SW Security, Architectures, Algorithms

Digital Design: Logic and Physical synthesis, Place & Route, Clock Tree Synthesis, Physical Verication, Static/Dynamic Timing, Signal integrity, xOCV, DFM/DFY, Physical Design for DebugAnalog Design: Analog Mixed Signal IP, High-Speed Interfaces, Various RAM design, IO Buffer,PLL/DLL Design, Standard Cell DesignFPGA: FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping Power/Energy Efciency: Digital/Analog Power Optimization Techniques, Power Architectures, Power/Performance Trade Off, Power Delivery Network, Power Switch, Power/Thermal BalanceVerication and Test: Design for Test (DFT), Product Level Test, Design Verication Techniques, Mixed Signal Verication, Fault Tolerance, DPPM Betterment, Formal Verication, EmulationPower Management and RF: Regulator Design, On Chip Regulator, RF Circuits, Effective Spectrum Utilization, New Transceiver Design in 5G Era, RF Certication, LDO Design, SMPS DesignElectronic Design Automation : Simulation Tools for Design Verication, SPICE Simulation,Logic/Physical Synthesis, EDA for Sub 10nm, Physical Design, Physical Verication Tools, Post Tapeout Toolset, DFT/DFD Tools, ATPG, Static Timing and Timing Exceptions, Mixed Signal SimulationsEmerging Technologies: Nano-CMOS Technologies, MEMS, CMOS Sensors, CAD/EDA Methodologies for Nanotechnology, Nano-Electronics and Nano-Circuits, Nano-Sensors, MEMS Applications, Nano-Assemblies and Devices, Non-Classical CMOS; Post-CMOS Devices; Biomedical Circuits, Carbon Nano-Tubes Based Computing

Call for Papers

Intelligent System Design Efcient Component Design

Deadlines

Abstract SubmissionJune 16, 2019 (Sunday)

Full Paper SubmissionJune 30, 2019 (Sunday)

Acceptance NoticationSeptember 1, 2019 (Sunday)

Camera Ready VersionSeptember 29, 2019 (Sunday)

Regular Papers

Acceptance NoticationSeptember 1, 2019 (Sunday)

Proposal SubmissionJune 16, 2019 (Sunday)

Slide SubmissionNovember 3, 2019 (Sunday)

Tutorials

Abstract SubmissionJune 16, 2019 (Sunday)

Acceptance NoticationSeptember 1, 2019 (Sunday)

Final PresentationSeptember 29, 2019 (Sunday)

Designer Track

High Level ProgramVisionary Keynotes

PHD Forum

Designer Track

Tutorials

Papers

Posters

Women in Engineering

Startup Forum

Panel Discussion

Fellowship

Design Contest

Exhibits