UC San Diego / VLSI CAD Laboratory Toward Quantifying the IC Design Value of Interconnect Technology Improvement Tuck-Boon Chan, Andrew B. Kahng, Jiajia

UC San Diego / VLSI CAD Laboratory

Toward Quantifying the IC Design Value of Interconnect Technology

Improvement

Toward Quantifying the IC Design Value of Interconnect Technology

Improvement

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li

VLSI CAD LABORATORY, UC San Diegohttp://vlsicad.ucsd.edu

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OutlineOutline

Motivation Related Work Our Framework Experiments and Results Conclusion

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OutlineOutline


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MotivationMotivation Wire delay increases with technology scaling Improvement of BEOL both important and expensive Issue 1: no systematic quantification of ROI from BEOL

improvement Issue 2: unclear whether BEOL improvement benefits can

be leveraged by EDA tools Goals:

– A framework to quantify BEOL improvement values guide BEOL technology investment and targets

– Assess EDA tools’ ability to leverage improved BEOL = potential “EDA gap”

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Focus of Our WorkFocus of Our Work Product quality comes from interaction among design,

BEOL technology, EDA tool We focus on interaction between BEOL and EDA

Design

BEOL Technology

EDA toolThis work

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OutlineOutline


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Related WorkRelated Work

Studies of DRAM or simple logic circuits, not at chip-level Ignores interaction between BEOL technology, EDA tool [Li01] – DRAM performance improvements from low-k [Kapur02] – R, C impacts on signal, power [Bamal06] – Performance, energy comparison studies

with different interconnect technologies

Focus on variation, not future BEOL improvements [Jeong10] – Chip-level impacts of interconnect variation

due to double-patterning

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OutlineOutline


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Our Framework Our Framework

Timing and power analysis

1.Modify BEOL files to model R, C reductions in future technologies– Modify ITF files – Use Synopsys StarRC to

convert ITF to TLUplus files

2.Design implementation (RTL-to-layout and signoff) with original and modified BEOL files

3.Run timing, power analysis

Modified BEOL files

Hypothetical RC reductions

Original BEOL files

Circuit implemented with original

BEOL

Circuit implemented with modified

BEOL

Circuit implementation flow (synthesis, place and route)

Designs

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TestbedTestbed Designs: {aes_cipher, des_perf, mpeg2, pci_bridge32}

from OpenCores x {fast, slow} clock periods Technology: TSMC 45nm, LVT and HVT

20SOC and below can be very different SP&R: Synopsys Design Compiler + IC Compiler

– Execute each P&R run three times denoising Timing and power analysis: Synopsys IC Compiler Signoff: no hold or EM violation, TNS < 30ps

Apples-to-apples comparison for design metrics

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OutlineOutline


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Expt 1: Impact of R, C Reduction on PowerExpt 1: Impact of R, C Reduction on Power 45% R, C reduction only leads to 8% power reduction R, C reduction improves timing fewer / smaller cells

leakage power ↓ (but, only on critical paths) C reduction load cap ↓ net switching power ↓

(but, gate cap dominates)

R, C=55% R, C=70% R, C=85% R, C=100%0.6

0.7

0.8

0.9

1.0

1.1min average linear max

No

rma

lize

d P

ow

er

R, C=α%: implementation with α% dielectric constant and metal resistivity w.r.t original BEOL

R, C reduction occurs on M2-M5

Power of implementation with original BEOL

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Impact of R, C Reduction on AreaImpact of R, C Reduction on Area

R, C reduction leads to little improvement in area Tool uses Vt swapping to exploit improved timing

– Same footprint of LVT and HVT cells same post-opt area Optimization methodology of EDA tools affects value

extracted from improved BEOL

R, C=55% R, C=70% R, C=85% R, C=100%0.6

0.7

0.8

0.9

1.0


No

rma

lize

d A

rea

Area of implementation with original BEOL

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Expt 2: Reduction in R vs. in CExpt 2: Reduction in R vs. in C In this experiment, C reduction offers more benefits

–Wire delay ↓ trade timing for power–R reduction improves wire delay–C reduction improves wire delay + load cap

R reduction can be critical with high Vdd, temperature Technology R&D might focus more on C reduction

C=55% C=70% C=85% C=100%0.7

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0.9

1.0

1.1min average linear

No

rma

lize

d P

ow

er

R=55% R=70% R=85% R=100%0.7

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0.9

1.0


No

rma

lize

d P

ow

er

Power w/ only R reduction Power w/ only C reduction

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Expt 3: R, C Reduction in Advanced TechnologyExpt 3: R, C Reduction in Advanced Technology Wire delay becomes critical in advanced technologies

– Impact of R reduction increases– We model advanced technology = increase R by 8x

Benefits of R, C reduction increase in advanced technologies

R=55% C=55% R, C=55%0.7

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0.9

1.0

1.1

No

rma

lize

d L

ea

ka

ge 5%

2%

Leakage power

R=55% C=55% R, C=55%0.7

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1.0

1.1

No

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lize

d T

ota

l P

ow

er

Total power

AdvancedCurrent

AdvancedCurrent

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Expt 4: Impact of Layer SelectionExpt 4: Impact of Layer Selection

BEOL improvement incurs high manufacturing cost– What is optimum subset of layers to improve under cost limits?– Flexible BEOL = subset of layers is selectively improved– Inappropriate selection of R, C-reduced layers is suboptimal

Guideline: reduce R, C on adjacent and highly utilized layers

Small difference between different layer selections– Tools’ ability to leverage the improved BEOL layers?

0.8

0.9

1.0

1.1min average max

No

rma

lize

d P

ow

er

{2,3,4,5} {2,3} {2,4} {2,5} {3,4} {3,5} {4,5}

Layers with improved BEOL

RC-reduced layers are far from each other

RC reduction has more benefit on highly utilized layers

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Tools’ Exploitation of R, C ReductionTools’ Exploitation of R, C Reduction

Assessment flow1. Implement designs with both original and improved BEOL2. Run timing and power analysis with improved BEOL3. Compare frequency, power

Preliminary results show tool can leverage R, C reduction– Case 1 might be misguided during optimization

800 850 900 950 1000 10508

9

10

11

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Frequency (MHz)

Po

we

r (m

W)

800 850 900 950 1000 10508

9

10

11

12

13

Frequency (MHz)

Po

we

r (m

W)

Case 1: Implementation with original BEOL, analyzed with modified BEOL Case 2: Implementation with modified BEOL, analyzed with modified BEOL

Reduced R, C on M3, M4 Reduced R, C on M2, M5

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RC-Awareness in EDA ToolsRC-Awareness in EDA Tools A “smart” router should be aware of improved BEOL

– Route setup critical paths on layers with small R, C– Route hold critical paths on layers with large R, C

∆wire distribution (of layer x) = %wire on layer x - %wire on layer x

Assessment: – Implement designs with flexible BEOL – Check ∆wire distribution of layers for setup- and

hold-critical nets

w/ improved BEOL w/ original BEOL

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Experimental ResultsExperimental Results Compare ∆wire distribution from current router (bars)

and a hypothetical RC-aware router (ovals)– White (Orange) = positive (negative) ∆wire distribution – Same color of bar and dotted oval RC-awareness

Router is not fully responsive to BEOL R, C reduction

-8%

0%

8%

-8%

0%

8%

-8%

0%

8%

-8%0%8%

∆W

ire

dist

ribut

ion

{2,3,4,5} {2,3} {2,4} {2,5} {3,4} {3,5} {4,5}

Layers with reduced RC

-8%

0%

8%

-8%0%8%

-8%0%8%

-8%

0%

8%

M2

M3

M4

M5

{2,3,4,5} {2,3} {2,4} {2,5} {3,4} {3,5} {4,5}

Layers with reduced RC

Setup-critical nets Hold-critical nets

√ √ √ √

√ √

√ √ √

√√

√

X X

XX

√

√

√

√

X

X X

X X X

X X

XX

X

X

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OutlineOutline


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ConclusionConclusion Framework to quantify impact of interconnect

resistance and/or capacitance reductions on chip-level design metrics

Reduction in capacitance gives more benefits than in resistance– R reduction can be critical in wire-delay dominant designs

(due to high Vdd, temperature or advanced technology) Capability of EDA tools to leverage improved BEOL has

room for improvement Ongoing works

– Iso-constraints vs. iso-GDS

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0% 5% 10%

15%

20%

25%

30%

35%

40%

45%

80%

84%

88%

92%

96%

100%

0% 5% 10%

15%

20%

25%

30%

35%

40%

45%

90%

92%

94%

96%

98%

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ISO-GDS ExptISO-GDS Expt Basic tradeoffs to exploit improved BEOL

– R, C reduction improved timing Vdd ↓ Power ↓

0% 5% 10%

15%

20%

25%

30%

35%

40%

45%

0%

2%

4%

6%

8%

10%Frequency improvement

Vdd reduction

Power reduction

R, C reduction R, C reduction

R, C reduction

Gate-wire balance

Performance requirement+ device type

Activity factor + nominal voltage + device type

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ConclusionConclusion Framework to quantify impact of interconnect

resistance and/or capacitance reductions on chip-level design metrics

Reduction in capacitance gives more benefits than in resistance– R reduction can be critical in wire-delay dominant designs

(due to high Vdd, temperature or advanced technology) Capability of EDA tools to leverage improved BEOL has

room for improvement Ongoing works

– Iso-constraints vs. iso-GDS– Study impact of interconnect R, C reduction across wide

supply voltages– Extend our analyses to M1 and middle-of-line layers

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AcknowledgmentsAcknowledgments Work supported from Sandia National Labs,

Qualcomm, Samsung, NSF, SRC, the IMPACT (UC Discovery) and IMPACT+ centers

Thank You!

Backup Slides

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Values of Improved BEOLValues of Improved BEOL Question 1: What is overall impact of R and/or C

reduction(s) on design metrics?– 45% R, C reduction 8% power reduction, similar area

Question 2: Which reductions offer more benefits, in R or in C?– C reduction offers more benefits– R reduction can be critical with high Vdd, temperature

Question 3: How will impacts of R, C reduction change in advanced technology nodes?– Benefits of R, C reduction increase in advanced technology

Question 4: What is optimum subset of layers to improve under cost limits?– Should reduce R, C on adjacent and highly utilized layers

Documents

UC San Diego / VLSI CAD Laboratory Toward Quantifying the IC Design Value of Interconnect Technology Improvement Tuck-Boon Chan, Andrew B. Kahng, Jiajia