Verilog HDL

Hardware Description Language

HDL – a “language” for describing hardware

Two industry IEEE standards: Verilog VHDL (Very High Speed Integrated Circuit HDL)

Verilog Originally designed for simulation and verification

Gateway Design Automation, 1983 Functionality later added for synthesis

CAD Design Process

Design conception

Truth table VerilogSchematic capture

Simple synthesis Translation

Merge

Boolean equations INITIAL SYNTHESIS TOOLS

DESIGN ENTRY

Design correct?

Logic synthesis, physical design, timing simulation

Functional simulation

No

Yes

Synthesis Using Verilog

There are two ways to describe circuits in Verilog

Structural Use Verilog “gate” constructs to represent logic gates Write Verilog code that connects these parts together

Behavioral flow Use procedural and “assign” constructs to indicate what

actions to take The Verilog “compiler” converts to the schematic for you

Verilog Miscellanea

Comments: just like C++ // this is a single line comment /* this is a multi-line

comment */

White space (spaces, tabs, blank lines) is ignored

Identifier names Letters, digits, _, $ Can’t start with a digit Case-sensitive! There are also reserved words can’t be one of these

Verilog Types

There are NO user-defined types

There are only two data types: wire

Represents a physical connection between structural elements (think of this as a wire connecting various gates)

This is the most common type for structural style wire is a net type and is the default if you don’t specify a type

reg Represents an abstract storage element (think of this as an

unsigned integer variable) This is used in the behavioral style only

Verilog Modules and Ports

Circuits and sub-circuits are described in modules module … endmodule

The arguments to the module are called ports Ports are of type

input output inout bidirectional port; of limited use to us

Ports can be scalar (single bit) or vector (multi-bit) Ports are a scalar wire type unless you specify otherwise Example:

input [3:0] A; // a 4 bit (vector) input port (wire) called A

Verilog Structural Synthesis

The half-adder (sum part only):

module halfAdder(S,A,B);input A, B;output S;wire AC, BC, X, Y;

not(AC,A); // AC ~Anot(BC,B); // BC ~Band(X,A,BC); // X A & BCand(Y,B,AC); // Y B & ACor(S,X,Y); // S X | Y

endmodule

Verilog Primitive Gates

and(f,a,b,…) f = (a ∙ b …) or(f,a,b,…) f = (a + b + …) not(f,a) f = a' nand(f,a,b,…) f = (a ∙ b …)' nor(f,a,b,…) f = (a + b + …)' xor(f,a,b,…) f = (a b …) xnor(f,a,b,…) f = (a b …)

You can also “name” the gates if you like … and And1(z1,x,y); // this gate is named And1

Comments on Structural Design

Order of statements in structural style is irrelevant This is NOT like a typical programming language Everything operates concurrently (in parallel)

Primitive gates can have any number of inputs (called fan in) The Verilog compiler will decide what the practical limit is

and build the circuit accordingly (by cascading the gates)

All structural elements are connected with wires Wire is the default type, so sometimes the “declarations”

are omitted

Example: 3 Way Light Control

Example: 3 way light control 1 light L 3 light switches (A, B, C) A is a master on/off:

If A = off, then light L is always off If A = on, the behavior depends

on B and C only

Let 0 represent “off” Let 1 represent “on”

SOP Equation?

SOP: L = ABC’ + AB’C

A B C L

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

Example: 3 Way Light Control

The SOP implementation of the 3 way light control with gates:

with Verilog:module light3Way(L,A,B,C);

input A, B, C; output L;

not Not1(BC,B), Not2(CC,C); and And1(f,A,B,CC), And2(g,A,BC,C); or Or1(L,f,g);endmodule

Behavioral Synthesis Using Verilog

Behavioral style uses Boolean algebra to express the behavior of the circuit

L = (A B' C)+(A B C') for the 3 way light control

module light3Way(L,A,B,C); input A, B, C; output L;

assign L = (A & ~B & C) | (A & B & ~C);endmodule

Continuous Assignment

The assign statement is key in data flow synthesis The RHS is recomputed when a value in the RHS changes The new value of the RHS is assigned to the LHS after the

propagation delay (default delay is 0) The LHS must be a net (i.e. wire) type

Example: assign L = (A & ~B & C) | (A & B & ~C);

If A or B or C changes, then L is reassigned

The Verilog compiler will construct the schematic for you

Boolean Operators

Category Examples Bit length

Bitwise ~A, A & B, A | B, A^B (xor), A~^B (xnor) L(A)

Logical !A, A&&B, A||B 1

Reduction &A, ~&A, |A, ~|A, ^~A, ~^A 1

Relational A==B, A!=B, A>B, A<B, A>=B, A<=B 1

Arithmetic A+B, A-B, -A, A*B, A/B Max(L(A),L(B))

Shift A<<B, A>>B L(A)

Concatenate {A,….,B} L(A)+…+L(B)

Replication {B{A}} B*L(A)

Condition A ? B : C Max(L(B),L(C))

Behavioral Style for Full-Adder

module fullAdder(S,Cout,A,B,Cin);input A,B,Cin;output S,Cout;

assign S = A ^ B ^ Cin;assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

Another Behavioral Style for Full-Adder

module fullAdder(S,Cout,A,B,Cin);input A,B,C;output S,Cout;

assign {Cout,S} = A+B+Cin; // + means addition

endmodule

Verilog also supports arithmetic operations! compiles them down to library versions of the circuit

Gate Delays

Gates may be specified with a delay – optional

not #3 Not1(x,A);

or #5 Or1(F,B,x);

The propagation delay is in “units” which can be set independently from the code

Propagation delays have no meaning for synthesis, only for simulation Hence, we won’t use them

Typical Design Process

Graphical Entry

HDL Entry

Compiler

Waveform/Timing Diagram

Timing Analysis

Program the FPGAUP2 Board

CAD and Synthesis

Analysis vs Synthesis (1)

Analysis process Determine the function performed by an existing circuit

What does this do?

Synthesis process Design a new circuit that implements a desired function

f = A ∙ B' + A' ∙ B aka A B

Analysis vs Synthesis (2)

Analysis is usually pretty easy

Synthesis is more complicated Most of digital design is about synthesis

Synthesis can be done by hand For large systems, this is not reasonable to expect

At least if you want good quality circuits

Synthesis can also be done with CAD tools Using schematic capture Using a Hardware Description Language (HDL)

Verilog VHDL (Very High Speed Integrated Circuit HDL)

Synthesis (1)

Given the table of combinations:

What is the circuit?

A B f

0 0 1

0 1 1

1 0 0

1 1 1

Synthesis (2)

The same function can be done more simply as

How do you get the “minimum cost” design? There are a few different techniques

Boolean algebra: a mathematical technique Karnaugh maps: a visual technique Quine-McClusky: an algorithmic technique

What Does Minimum Cost Mean?

One example of Cost:

Cost = #gates + #input “pins” to each gate

Cost = 2 + 3 = 5

Cost = 6 + 11 = 17

Other Examples of Cost

# of gates Area of circuit Estimated routing cost (for wires) Shortest Critical Path Delay

can be measured in many different ways Best Average Case Path

Example: Binary Addition

1 bit binary addition (with no carry-in) 2 single bit inputs (A, B) 1 single bit output sum S = A + B 1 single bit output carry-out Cout

A B S

0 0 0

0 1 1

1 0 1

1 1 0

A B Cout

0 0 0

0 1 0

1 0 0

1 1 1

Example: Binary Addition with Carry-in

1 bit binary addition with carry-in 3 single bit inputs (A, B, Cin) 1 single bit output sum S = A + B + Cin 1 single bit output carry-out Cout

S

111

011

101

001

1

1

0

0

B

10

00

10

1

0

0

1

0

1

1

0

1

1

1

0

1

0

0

000

CoutCinA

More Gates

NAND: Opposite of AND (“NOT AND”) NOR: Opposite of OR (“NOT OR”) XOR: Exactly 1 input is 1, for 2-input

XOR. (For more inputs -- odd number of 1s)

XNOR: Opposite of XOR (“NOT XOR”)

x0011

y0101

F1001

x0011

y0101

F0110

x0011

y0101

F1000

x0011

y0101

F1110

x

y

x

yFF

NORNAND XOR XNOR1

0

x y

Fx

y

1

0

x

x

y

y

F

NAND NOR

• NAND same as AND with power & ground switched

• Why? nMOS conducts 0s well, but not 1s (reasons beyond our scope) -- so NAND more efficient

• Likewise, NOR same as OR with power/ground switched

• AND in CMOS: NAND with NOT

• OR in CMOS: NOR with NOT

• So NAND/NOR more common

More Gates: Example Uses

Aircraft lavatory sign example S = (abc)’

Detecting all 0s Use NOR

Detecting equality Use XNOR

Detecting odd # of 1s Use XOR Useful for generating “parity”

bit common for detecting errors

S

Circuit

abc

000

1

a0b0

a1b1

a2b2

A=B

Circuit Simplification

Two circuits are functionally equivalent if the circuit behavior is the same for all inputs

Simplification is the process of finding a functionally equivalent circuit that costs less

Boolean algebraic simplification is rarely done much in practice, but all other techniques are based on this process

Binary Addition with Carry-in … Again

We had determined the SOP:

S = (A' B' Cin)+(A' B Cin')+(A B' Cin')+(A B Cin)

Cout = (A' B Cin)+(A B' Cin)+(A B Cin')+(A B Cin)

These can be greatly simplified

Using Boolean algebra often results in a non-SOP form not even two-level logic

Simplification of S and Cout

S = Cin'A'B + Cin'A B' + Cin A' B' + Cin A B

= Cin'(A' B + A B') + Cin (A' B' + A B)

= Cin' (A B) + Cin (A B)'

= Cin (A B)

= Cin A B

Cout = Cin' A B + Cin A' B + Cin A B' + Cin A B= Cin(A B) + A B

… or equivalently …

= A B + B Cin + A Cin (the “majority” function)

Gate Level Implementation: Full-Adder

A gate level implementation (not SOP) for S is

A (multi-level) gate level implementation for Cout is

The result is called a “full-adder”:FA

A

B

S

Cou tC in

Summary of Algebraic Simplification

Using Boolean algebra to simplify expressions can be quite challenging

There are easier ways Karnaugh maps Algorithmic methods

We’ll do both soon

Comments on SOP and POS

Neither the SOP nor the POS forms guarantee a minimum cost implementation Sometimes a multi-level form does better!

Most practical devices use only NAND or NOR gates anyway

So, how is all of this helpful?

Circuit minimization methods can be developed from this basis Converting SOP and POS to NAND/NOR circuits is easy