The all-new computer for

VARIAN

Ei- 1Extendable Architecture The Varian 73 is available with either semiconductor or core memories, or any combination of the two. With memory mapping (a future option) up to 262K of memory can be included in the system. All memories are dual port for fast interleaving of I/O and proces- sor functions. Built-in features allow I multiple central processors to share memory, greatly simplifying the imple- mentation of a multi-processor system.

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165-Nanosecond Microinstruction Time The Varian 73 has set a new standard I.

VARIAN 73 THE ALL-NEW COMPUTER FOR THE NEW COMPUTER AGE

For the better part of a decade, Varian 620-series computers have paced the minicomputer industry. Each new model has represented a dramatic improvement in performance, and an equally dramatic reduction in the dol- lars paid for that performance.

Now, with the introduction of the Varian 73, Varian Data Machines has achieved a major step-function change in the power and potential of the mini- computer as a systems component.

The Varian 73 has been designed spe- cifically to meet the new, more sophis- ticated demands that have developed as users have gained experience in applying minicomputers to thousands

for processing speed. Microinstruc- tions are carried out in 165 nanosec- 1.!! of applications.

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These demands have included faster processing times, a more efficient and flexible instruction repertoire, ex-

onds. With semiconductor memory, .. register-reference instructions are 1

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panded memories, a faster, more ver- satile input/output structure, simpler interfacing between multiple proces- sors and memories.

The Varian 73 meets all these require- ments, with performance to sparD

User-Accessible Microprogramming The Varian 73 is a microprogrammed computer, with 64-bit control words

2 - 8 #:

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dictating the flow of data through a 16-register processing section. This powerful combination permits the writing of exceptionally fast and effi- cient programs. The computer can process a l l p rev ious Var ian 620 programs, and with the addition of a Writable Control Store option, the microprogram can be extended to meet any special system requirements.

'he Varian 73 has set a new standard or speed and flexibility.

Data flow is controlled by hundreds of microinstructions stored in a read-only memory. Execution time per microin- truction is only 165 nanoseconds. And f that isn't enough speed and flexibil-

ity, the user can add an optional Writ- able Control Store to create his own m i c r o i n s t w ~~ g t ,: x-:*-5-= .

h * --~ % & ~ ~ ~ & & l i l ~ ~ n r n-The stand- ard Varian 73 m program consists of 512 microinstructions, each a 64-bit word stored in the processor ROM. The 64 b i t s a r e d iv ided in to f ie lds which control the flow and manipula- tion of data throughout the machine. A single microinstruction can dictate a number of different machine functions: register, memory and I /O transfers , arithmetic and logical operations, and tests on the conditions of registers.

processor microprogram can be sup- plemented by an optional Writable Contro l S to re memory conta in inn microinstructions written by the use] The standard Varian 73 microprogram is designed to decode and emulate the widely used Varian 620 instruction set. Special microprograms can also be wri t ten, using the powerful 64-bit microinstruction format, to adapt the Varian 73 to special application re-quirements.

Bfg4$teb. ibility is pro-

vided by 1 6 general-purpose and 8 special-purpose 16-bit registers , all accessible to the microprogram.

gs - Processors , memories, and PMA (Priority Memory Access) 1 / 0 controllers are all co nected to a common bus structure f u r fast data transfers and ease of expap- sion. Two parallel buses are provide1 allowing data transfer from a periph- eral to a 4K or 8K memory module, for example, while the processor accesses a second memory module. Multiple processors, peripheral devices, and u] to 262K words of memory can share the parallel buses. Advantages of th' unique structure are detailed on thG following pages.

Varian 73 Memory Expansion

Memory Bus A

I

1(DMA & 1 1 0 Bus)

I [Memory Bus

AddresafBata Bus Micr~prop~ramtie Uts] Control Bw

(MBits]

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#

The Varian 73 ha added a new dimen- sion to the architecture of computer memory systems. Both core and MOS memories are available in 8K modules, each pack-aged an a single board. All share a common, dual bus structure, along with multiple processors and PMA controllers. Processors equipped with the Memory Map option will be able to address 262K of memory.

'rn ;,.'m; -Cycle time for core memories iB a fast 860 nanoseconds. The rnemorit, ,re available in 4K and 8K modules.

- Semiconductor memories, with a cycle time of 330 nanoseconds, are available in 1K,2K, 4K,and 8Kmodules. Theymay be com- bined with core memories in any pro- portion. Addressing and programming are identical for the two types of mem-ories. MOS memories are for optimum speed and throughput; core memories for optimum econamy. A battery-pow-ered Data Save option may be added to the power supply when semi-conduc- tor memory is included in the system.

'@%qaJ&rb-- Beth core and MOS mem-odes am provided with two fully im- plemented ports, each connected to one of two parallel memory buses. In multiple-memory systems, this means that one memory may be communicat- ing with a processor while another is

transferring data to or from another processor or an VO device. Priorities between the bu.ses are implemented by memory -control circuits, with Bus A having priority over Bus B.

-,---, !erforms address relocation and memory protection for up to 282K memory locations by translating the 15-

-bit virtual memo y address and a 4-bit k ~ yinto an 18-bit physical address. Up to 16 independent protection parti-tions may be simultaneously assigned. Any user program may employ up to 3ZK words of memory in 512-word -blocks. Completely protected, read- only, and common memory blocks may be defined.

Mmory @mtw*-The memory-pro-tect option pre.dts the program from accessing any 512-word segment of memory that has been "protected" by a mask stored in the option. The 64-bit mask provides protection for a full 32K memory block. The mask can be applied, removed, and changed under p r o m control.

Mrrsnqm Fatit9 -Another memory option checks the parity of every data transfer on the dual memory bus. Two parity bits are used, one for the 8most significant bite, the other for the 8 least significant bits. This facilitates byt packing and retrieval with a parit check on each byte that is transferred.

Memory Module

Semiconductor Memory Module

,

The Varian 73 gives the system de-signer four different ways to cornmu-nicgte with peripherals and other data sources. The result is unprecedented flexibility in selecting the I/O tech- dqae that will provide the highestpos-sible data transfer rate at minimum cast in processor time.

All data transfers, except PMA, are over the party-he T/O bus, with 18bi-directional linw for addresses and for data, plus an additional 14 lines for timing, sense, end control signals. PMA transfers are direct to memory, with separate 1 6 - h e bums £QE addrm-sea and data,

interrupt structure, expandable at low cost ta up to 88 levels, with automatie interrupt identification, External con-trollers can all request intermpfa and specify the interrupt location via the address lines of the Varian 73 I/O bus. An optional Priority Interrupt Module [PIM] provides hardware priority ar-bitration and interrupt address (vector]

erals. to prepare controllers for other types of 110 transfers, and to commu-nicate with law-speed devices, such as a teletype. Any peripheral controller can also initiate a data transfer (or sig-4 its completion) by an interrupt to the processor.-. - ..

and memory are effected in the DMA mode. The technique is implemented by a Buffef Interlace Contralier @ I q option that stores the initial and find addresses of the data words to be transferred, The transfers are made on a "cycle stealing" basis, DMA transfers can occur at rates up to 333,000 words per second, hlgn-Sy $'M. - Special contrc ' lines ar, ,rovided for peripheral cot- trollers that are able to operate at "high speed" DMA rates, up to 1 rnillia words per second. A similar BIC op-tion is used to implement transfers at thin higher rat- - rity Memn & w w a FMA.1 VO-D transfr~rs,,. Jm EpU meraw

generation for 8 levels. Up to 8 PIM's rate (3.03 million words per second, in may be interfaced to the I/O bus of a the case af a MOS memory) can be Varian 73processor. Interrupts may be enabled or dfsabled individually or in gmups.

obtained through the PMA channel, A PMA controller is loaded with the in-itial and final addresses of the data

ntrd UCI- Programmed IIO words to be transferred. Controller operations are initiated by the central data and address lines are ccannacted processor and are used prim~rilyto direr"'-' '-the memary bus. control and sense the atate of periph-

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oontrd and job accauatabi2ity; a sys-t%mpreparatfonprogram,systemmain-tenance program, source progmn edi- ,tor,objar;tpragrmdebugpackage, and a program Ilbrary. MOS eonsewas mafn memory space I

for the user by allovving till dtwma , rrlements, except for e small Resident Marsitar, te be stored an fhe robthg memory or magnetie tape and loaded into the cornputex only when n d d . f ibappllea even to the SyatamExecu-tive which servesaa the central control element. 1Example OI MOB hj~drati~u Other

Deviect

Both systems fncarporata a full repar-Zaire of utility psograms, as well as D M MR snd FORTRAN IV language z;y&processors.M09 slsa includes RPGIV. Bckrrdda

\

VOXTEX [Vasfan Onnitask Rml-The Executive] isa multi-progremmtngsys-tarn with special features designed for real-tfma appliceffons. A number of

"bac&poun&' program am exeaut-ed during the idle-the intarwats embed- Valeian MOS @biter Operating Sys-ded in most real-time operations. The tem] is an integrated batch-process effect b to give the system tha utility softwaresystem designed to boast pttr-of two camputass far the pdos of one. farrnance and simplify ctperatim for

the medim-to-larae-scale systemuser.-VORTEX alao Lncrew~the &~iaaoy MOS is available in &, -b,

any instal'atlan which the 'Om- magnetic-tape resident vudons, and putel is to 'perate On numO includes a complete I/* Can-] Syg-ber of different programs in sequence. t, and Exsctltivs. Theusersirn~lyarstabliabesihspriority of the jobs t i be executed;the-system ttutamatically schedules and nrns the pragrams without further operator intarvm-tTaa

Features offeredby MOS are aatomatic idmbification of bath printed listings and binary object output with the jctb Fftle and date 50 provide for program

The Varian 73 incorporates a number of innovative packaging concepts, all aimed at increasing reliability and per- formance, as well as simplifying the task of system expansion or change.

For the f irs t time, a t ruly universal mainframe backplane has been pro- v i d e d . Al l c o m p u t e r c i r c u i t r y i s mounted on large single-board mod- ules, 15.6 inches by 19 inches, inserted through the front of the computer. The modules plug into a multilayer printed- circuit backplane which contains the dual memory buses and control sig- nals. Any module can be placed in any slot position.

Connected to the front of the modules are flexible cables with controlled im- pedance for the I/O interconnections (Programmed I/O, DMA, High-speed DMA, and PMA).

A valuable side benefit of this pack- aging technique is that no extender boards or other devices that might alter the computer performance are required for servicing the individual modules. The module is simply moved to the uppermost slot and with the computer chassis drawn out on slides, serviced from the top.

The combination of large board pack- aging and extensive use of MSI and LSI circuits has reduced both the com- ponent count and the path lengths be- tween components. With a minimum number of interconnections and board- to-board cabling, the Varian 73 repre-

apt&=

Tka Mdnfrartta C b m b-The s y s tems designer has the choice of two Varian 73 mainframe chassis. The 7- inch chassis provides 7 slot positions, plus space for two I/O controllers. The 14-inch chassis increases the slot posi- tions to 17. A 32K MOS-memory sys- tem can be contained in the smaller chassis; a 120K system in the larger. Additional memory can be housed in a second 7-inch or 14-inch chassis. If space is required for additional 1 / 0 controllers, a 101/z-inch I/O Expansion Chassis is used.

I ae G~EIWI are available. The Programmer's Console has all the controls and indicators needed to load and debug programs. The Operator's Console has only those controls needed to start and stop the computer. A key switch provides security for the pro- gram being run.

-A separate s1/4-inch p u w w supply can drive a full 32K sys- tem, core or MOS. A Power Failure/ Restart mainframe option provides protection against momentary loss or reduction of ac power. A Data Save option can be added to provide stand- by battery power for MOS memory modules.

VARIAN 73

ASSEMBLER

INSTRUCTIONS

Load % Store Instructions LDA Load A Register IDA1 Load A Register Immediate LDAE Load A Register Extended LDB Load B Register LDBI Load B Register Immediate LDBE Load B Register Extended LDX Load X Register LDXI Load X Register Immediate LDXE Load X Register Extended STA Store A Register STAI Store A Register Immediate STAE Store A Register Extended STB Store B Register STBI Store B Register Immediate STBE Store B Register Extended STX Store X Register STXI Store X Register Immediate STXE Store X Register Extended TSA Transfer Switches to A Register Arithmetic Instructions INR Increment Memory and Replace INRI Increment and Replace Immediate INRE Increment Memory and Replace Extended ADD Add Memory to A Register ADD1 Add Memory to A Register Immediate ADDE Add Memory to A Register Extended SUB Subtract Memory from A Register SUB1 Subtract Memory from A Register Immediate SUBE Subtract Memory from A Register Extended MUL Mult inh MULI ~ u l t & l ; Immediate MULE Multiply Extended DIV Divide DIVI Divide Immediate DIVE Divide Extended Logic Ins1 tructions ORA Inclusive-OR Memory and A Register ORAI Inclusive-OR to A Register Immediate ORAE Inclusive-OR Memory and A Register

Extended ERA Exclusive-OR Memory and A Register ERA1 Exclusive-OR to A Register Immediate ERAE Exclusive-OR Memory and A Register

Extended ANA AND Memory and A Register ANAI AND to A Register Immediate ANAE AND Memory and A Register Extended rump Instructions* IMP Jump Unconditionally JOF Jump if Overflow Indicator Set J AP Jump if A Register Positive JAN Jump ~f A Register Negative JAZ Jump if A Register Zero JBz Jump if B Register Zero IXz Jump if X Register Zero JSS1 Jump if Sense Switch 1 Set JSS2 Jump if Sense Switch 2 Set JSS3 Jump if Sense Switch 3 Set

Jump if Combined Conditions Are Met Z N Z Jump if A Register Not &ro JBNZ Jump if B Register Not Zero JXNZ J m p if X Register Not Zero JSlN Jump if S e m e Switch 2 IWt §.el JS2N Jump 2# Sense Sw1tch2 NDT Set JS3N Jump if Sense Switch 3 Not Set IJMP Indexed Jump JSR Jump Unconditionally and Set Return

i n Index Register JOFN Jump if Overflow Indicator Not Set BT Bit Test SRE Skip if Register Equal to Memory Jump-And-Mark Instmdions* JMPM Jump and Mark Unconditionally JOFM Jump and Mark i f Overflow Set TANM Jump and Mark if A Register Negative JAPM Jump and Mark if A Register Positive JAZM Jump and Mark if A Register Zero JBZM Jump and Mark if B Register Zero

JS3M Jump and Mark if Sense Switch 3 Set JIFM Jump and Mark ~f Combined Conditions

Are Met JOFNM Jump and Mark if Overflow Not Set JANZM Jump and Mark if A Register Not Zero JBNZM Jump and Mark if B Register Not Zero JXNZM Jump and Mark if X Register Not Zero ISINM Jump and Mark if Sense Switch 1 Not Set TSZNM Jump and Mark if Sense Switch Z Not Set JS3NM Jump and Mark if Sense Switch 3 Not Set Execation Instmctions* Execution Times XEC Execute Unconditionally In Nanoseconds XOF Execute if Overflow Set sc Core

Memory Memory XAP Execute i f A Register Positive XAN Execute if A Register Negative

660 1320 XAZ Execute if A Register Zero 660 1320 XBZ Execute if B Register Zero 990 1980 XXZ Execute if X Register Zero 660 1320 XS1 Execute if Sense Switch 1 SetS O 1320 XS2 Execute if Sense Switch 2 Set390 1980 XS3 Execute if Sense Switch 3 Ser660 1520 XIF Execute if Combined Conditions Are Met 660 1320 XOFN Execute if Overflow Not Set 990 1980 XANZ Execute if A Register Not Zero 660 1320 XBNZ Execute if B Register Not Zero 660 1320 XXNZ Executive if X Register Not Zero 990 1980 XSlN Execute if Sense Switch 1 Not Set 660 1320 XS2N Execute if Sense Switch Z Not Set 660 1320 XS3N Execute if Sense Switch 3 Not Set 990 1980 660 1320 Control Instructions

HLT Halt660 1320 990 1980 NOP No Operation

3300-3795 3341-4836 SOF Set Overflow Indicator ROE Reset Overflow Indicator

990 1980 Shift Instruction$** 990 1980 LSRA Logical Shift Right A Register 1320 2640 LSRB Logical Shift Right B Register 660 LRLA Logical Rotate Left A Register 1320 LRLB LogicaI Rotate Left B Register 660 1320 990 1980

LLSR Long Logxal Shift Right 660 1320 LLRL Long Logical Rotate Left 660 1320 ASRA Arithmetic Shift Right A Register 990 1960 ASLA Arithmetic Shift Left A Register

LASR Long Arithmetic Shift Right 48265321 LASL Long Arithmetic Shift Left 48614156 ASRB Arithmetic S h ~ f t Right B Register 54865881 ASLB Arithmetic Shift Left B Register 515-5981 49914616 Register-Change Instmctions 5818-6641 IAR Increment A Reaister

IBR Increment B ~ e 5 s t e r IXR Increment X Register 1320 DAR Decrement A Register 1320 DBR Decrement B Register DXR Decrement X Register 1980 CPA Complement A Register 1320 CPB Complement B Register 1320 CPX Complement X Register TAB Transfer A Register to B Register 1980 TAX Transfer A Register to X Register is20 TBA Transfe? B Register to A Register 1320 TBX Transfer B Register to X Register 1980 TXA Transfer X Register to A Register TXB Transfer X Register to B Register

1320 TZA Transfer Zero to A Register 1320 TZB Transfer Zero to B Register 1320 TZX Transfer Zero to X Register 1320 AOFA Add Overflow to A Register 1320 AOFB Add Overflow to B Register 1320 AOFX Add Overflow to X Register 1320 SOFA Subtract Overflow from A Register1320 SOFB Subtract Overflow from B Register la20 SOEX Subtract Overflow from X Register 1320 MERGE Merge Source to Destination 1320 INCR Increment Source to Destination 1320 DECR Decrement Source to Destination 1320 COMPL Complement Source to Destination iszo ZERO Zero Register 1 1 I/O Instructions 1320 SEN Program Sense 1320 EXC External Control

CIA Clear and Input to A Register 1820 CIB Clear and Iuput to B Register 1x20 CIAB Clear and Input to A and B Registers

152&1891 INA Input to A Register 2021-2186 INB Input tn B Register

INAB Input to A and B Register OAR Output from A Register

1880 OBR Output from B Registerlg80,lSZO OAB Output from A and B Registers 1980,1320 IME Input to Memory , 1 W , 1320 OME Output from Memory 1980, 1320 1980, 1320 * First time is for condition true [for each indirect

JXZM Jump and Mark if X Register Zero 1980, 1320 level add 371 ns for SC memory, 660 n s for core JSlM Jump and Mark if Sense Switch 1 Set 1980,1320 memory). Second time is for condition not true. JS2M Jump and Mark if Sense Switch 2 Set 1980, 1820 ** For n shifts, add 165x1nanoseconds.

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SALES OFFICES PENNSYLVANIA Varian GmbH I - varian data machines 520 Penn Ave. Ludwigsfelderstr. 280 Ft. Washington, Pa. 19034 D-8 Munchen 50 (215) 643-2355 Tel: (0811) 1471059

CALIFORNIA Telex: 522523

8 varian rubsidiary

. 2722 michelson drive i~ine/california/92684(714) 833-2400

9901 So. Paramount Blvd. Downey, Calif. 90240 (213) 927-2673

4940 El Camino Real Los Altos, Calif. 94022 (415) 968-9996

611 Hansen Way Palo Alto, Calif. 94303 (415)493-4000

1065 Camino del Rio South San Diego, Calif. 92110 (714) 298-9292

FLORIDA 5223 Indian Hill Rd. Orlando, Florida 32808 (305) 299-2001

314 South Missouri Avenue, Suite 205 Clearwater, Florida 33516 (813) 446-8513

GEORGIA 180 Allen Road N.W., Suite 202 Atlanta, Georgia 30328 (404) 252-0047

ILLINOIS 205 West Touhy Ave. Park Ridge, Illinois 60068 (312) 692-7184

MARYLAND 4701 Lydell Drive Cheverly, Md. 20781 (301) 773-6770

MASSACHUSETTS 400 Wyman Street Waltham, Mass. 02154 (617) 890-6072

MICHIGAN 30215 Southfield Road Southfield, Mich. 48076 (313)645-9950

MISSOURI 9811 West Florissant, Suite 201 St. Louis, Missouri 63136 (314) 524-0880

NEW MEXICO 9004 Menaul Blvd., N.E. Albuquerque, New Mexico 87112 (505) 298-5570

NEW YORK 2 Hamilton Ave. New Rochelle, N.Y. 10801 (914) 636-8118 (212) 325-5248

3700 East Ave. Rochester, N.Y. 14618 (716) 586-3273

OHIO 25000 Euclid Ave. Euclid, Ohio 44117 (216) 261-2115

TEXAS P.O. Box 689 558 So. Central Expressway Richardson, Texas 75080 (214) 231-5145

5750 Bintliff, Suite 202 Houston, Texas 77036 (713) 781-0105

WASHINGTON Bldg. 2, Suite 210-D 300 120th Ave., N.E. Bellevue, Washington 98005 (206) 455-2568

AUSTRALIA Varian Pty. Ltd. 82 Christie St. St. Leonards N.S.W. 2065 BELGIUM S.A. Varian Benelux N.V. Rue Drootbeek 32 B-1020 Bruxelles Tel: (02) 288056 Telex: 24361

BRAZIL Varian Industria e

Comercio Ltda. Alameda Lorena 1834 01424 Sao Paulo Tel: 80-80-27 or 81-74-16

Varian Industria e Comercio Ltda.

Avenida Almirante Barroso 97 Sala 70113 Rio de Janeiro, Brazil Tel: 222-8434

CANADA Varian Assoc. of Canada Ltd. 6358 Viscount Road Malton, Ontario 416-677-9303

Varian Assoc. of Canada Ltd. Box 1347, 63 Bedford

Place Bonaventure Montreal 114, Quebec Tel: 514-871-1073 Telex: 01-20853

Varian Assoc. of Canada Ltd. Box 10025 Pacific Centre 700 West Georgia St. Vancouver 1, B.C.

FRANCE Varian S.A. Quartier de Courtaboeuf P.O. Box 12 F-91 Orsay Tel: (1) 9077826 Telex: 27642

GERMANY Varian GmbH Postfach 1154 Hilpertstr. 8 D-61 Darmstadt Tel: (06151) 86386 Telex: 419429

V

Varian GmbH Schulstrasse 18-20 D-506 Bensberg-Refrath Tel: (02204) 61066 Telex: 8878516

Varian GmbH Breitwiesenstr. 9 D-7 Stuttgart-Vaihingen Tel: (0711) 732028

Varian MAT GmbH Woltmershauserstr. 442 D-28 Bremen 10 Tel: (0421) 547119

HOLLAND Varian N.V. Maasluisstraat 100 Amsterdam Tel: (020) 159410 Telex: 14099

ISRAEL Varian Electronics Ltd. Rh. Haeshel7 Ramat Gan, Israel

MEXICO Varian S.A. Fco. Petrarca 326 Mexico 5, D.F.

SWEDEN Varian AB Skytteholmsvagen 7 D S-17122 Solna Tel: (08) 820030 Telex: 10403

SWITZERLAND Varian AG Viaduktstr. 65 CH-4011 Base1 Tel: (081) 223185 Telex: 62900

Varian AG* Steinhauserstr. CH-6300 Z U ~ Tel: (042) 232575 Telex: 7884112, 78844

UNITED KINGDOM Varian Associates Ltd. Russell House Molesey Road Walton-on-Thames Tel: (0932) 228766 Telex: 261351

Varian Associates Ltd. Donibristle Industrial Estate Block 5, Inverkeithing Dunfermline, FifeIScotland Tel: 3121 at Inverkeithing Telex: 72314

*European Headquarters: Socialist Countries, Yugoslavia, Spain, Portugal, Italy, Greece, Turkey, Africa, Near East, and India.