Programmable Logic and Storage Devices(2)

8/9/2019 Programmable Logic and Storage Devices(2)

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Digital Systems Design 2

Programmable Logic and Storage DevicesChapter 8: “Advanced Digital Design with the Verilog DL!"#ichael D$ Ciletti$#emory" CPLDs and %P&AsChapter '(: “Digital Design Principles and Practices!" )ohn%$ *a+erly" Prentice all" 2(('" ,hird -dition


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Programmable Logic and StorageDevices

*ith advancement o. hardware technology: Density Comple/ity Si0e

1. .ieldprogrammable gate arrays 3%P&As4" it provides an

attractive and coste..icient alternative to semic5stomapplication speci.ic integrated circ5its 3AS6Cs4$

,he opport5nity to reali0e large circ5its in %P&As hascreated press5re .or a change in the method by whichcirc5its are designed .or %P&Abased applications: Schematic entry tools can be prod5ctive and e..icient when

designs are small$ ,rend is toward larger and larger designs targeted .or %P&As$

,h5s" lang5agebased design methodology has becomeessential to %P&Abased design .lows$


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Programmable Logic and StorageDevices

,echnologies available .or implementing digital circ5its range .rom: Standard 6ntegrated Circ5its 36Cs4 5sed in lowdensity7lowper.ormance

applications" ,o Cellbased and .5llc5stom 6Cs .or highdensity7highper.ormance circ5its$

Standard 6Cs: Can be man5.act5red cheaply"

6mplement very limited" basic .5nctionality at low levels o. integration$ C5stomi0ed 6Cs 6mplement speciali0ed .5nctionality with a high level o. integration ave a small mar+et Creates inventory ris+ beca5se the 5antities that co5ld be sold do not warrant the

e/pense o. their development and prod5ction$ Programmable Logic Devices:

9etween two e/tremes o. density and per.ormance that characteri0e standardparts and .5llc5stom circ5its$

9orn o5t o. necessity created by two con.licting realities: Large" dense" highper.ormance circ5its cannot be b5ild practically or economically

.rom discrete devices Dedicated 6CS cannot be prod5ces economically to satis.y a diversity o. lowvol5me

applciations$


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Programmable Logic Devices

%or most 5ptodate PLDs see:www$einsite$net7ednmag

PLDs have a .i/ed architect5re

%5nctionality is programmed .or a speci.ic application Programming is done by:

#an5.act5rer mas+programmable logic devices3#PLD4

-nd


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Programmable Logic Devices ,he .irst type o. PLDs considered has the A?D1 plane str5ct5re shown in

the .ig5re$ ,his type o. architect5re is 5sed to implement 1#s" PLAs" and PALs$ 6t implements 9oolean e/pressions in S5m o. Prod5cts 3S1P4 .orm:

A?D plane .orms prod5ct terms selectively .rom the inp5ts" and 1 plane .orms o5tp5ts .rom s5ms o. selected prod5ct terms$

A programmable interconnect .abric @oins the two planes" so that the o5tp5tsimplement s5mo.prod5ct e/pressions o. the inp5ts$

*hether and how a plane can be programmed determines the partic5lartype o. PLD that is implemented by the overall str5ct5re$

A?D Plane 1 Plane6np5ts 15tp5ts

Prod5ct ,erms

A?D1 plane str5ct5re o. a programmable logic device


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Storage Devices

,he architect5re 5sed to implement PLDs lends itsel.to implementation o. storage devices$

Storage Devices can be: ead1nly" or

andom Accessdepending on whether the contents o. a memory cellcan be written d5ring normal operation o. the device$

1# 3readonly memory4 is a device programmed tohold certain contents" which remain 5nchanged d5ringoperation and a.ter power is removed .rom the

device$ A# 3randomaccess memory4 in contrast its contents

can be changed d5ring operation" and they vanishwhen the power is removed$


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ead1nly #emory 31#4

ead1nly #emory31#4 A 2n / b 1# consists o.

an addressable array o.semicond5ctor memory

cells organi0ed as 2n

words o. b bits each$ 1# 6nter.ace:

n = inp5ts de.iningaddress lines$

b = o5tp5ts called bitlines$

1# is non-volatilememory $ 6t;s content ispreserved even i. nopower is applied$


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ead1nly #emory 31#4

A?D1 planes .or a 1#:

Address

Decoder3?onprogrammable4

A?D Plane

1 Plane#emory Array

2n / b

b = 15tp5ts3bit lines4

2n #interms 3*ord lines4.ormed .rom inp5ts

A3(4A3'4

A3i4

A3n'4

D3b'4 D3i4 D3(4


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inp5t" o5tp5t combinational logic.5nction$

Inputs Outputs

A2 A' A( D> D2 D' D(

( ( ( ' ' ' (

( ( ' ' ' ( '

( ' ( ' ( ' '

( ' ' ( ' ' '

' ( ( ( ( ( '

' ( ' ( ( ' (

' ' ( ( ' ( (

' ' ' ' ( ( (


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B4 to obtain one passm5ltiplier thro5gh a conventional PLD;s A?D1 array$

*ith 1# one can reali0e the .5nction with one passthro5gh a 28 / 8 32B84 1#$

Contents o. a 1# are normally speci.ied by a .ilethat contains one entry .or every address in the 1#$

,he nice thin+ abo5t 1#based design is that one

can 5s5ally write a simple program in a highlevellang5age to calc5late what sho5ld be stored in the1#$


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,wodimensional decoding

As can be seen" twodimensional decoding allows a '28/'1# to be b5ilt with a >to8 decoder and a 'Binp5tm5ltiple/er 3whose comple/ity is comparable to that o. a to'B decoder4$

A '#/' om co5ld be b5ilt with a '(to'(2 decoder and

'(2inp5t m5ltiple/er$ A lot simpler than the onedimensional alternative$ Additional bene.it to red5ction o. decoding comple/ity is

that twodimensional decoding has one other bene.it = itleads to a chip whose physical dimensions are close tos5are important .or chip .abrication and pac+aging$

6n 1#s with m5ltiple data o5tp5ts the storage arrayscorresponding to each data o5tp5t may be made narrowerin order to achieve an overall chip layo5t that is closer tos5are$ %or e/ample" the ne/t .ig5re shows the possiblelayo5t o. a >2F / 8 1#$


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Possible layo5t o. a >2F / 8 1#


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Commercial 1# ,ypes

A modern 1# is .abricated as a single 6C chipG one thatstores # bits with a price 5nder H$

Vario5s methods are 5sed to “program! the in.ormationstored in a 1#:

#as+ Programmable 1#s$ #an5.act5rer has to be provided with the 1# content in order

to create one or more c5stomi0ed mas+s to man5.act5re 1#swith the re5ired pattern$

1# man5.act5rers impose a mas+ charge o. several tho5sanddollars .or the c5stomi0ed aspects o. mas+1# prod5ction$9eca5se o. mas+ charges and the .o5rwee+ delay typically

re5ired to obtain programmed chips" mas+ 1#s are normally5sed today only in very highvol5me applications$

%or a lowvol5me applications there are more coste..ectivechoices" disc5ssed ne/t$


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Commercial 1# ,ypes

Programmable readonly memory 3P1#4 Similar to a mas+ 1#" e/cept that the c5stomer may store

data val5es 3program the P1#4 in @5st a .ew min5tes$ P1# is man5.act5red with all o. its diodes or transistors

“connected!$ ,his corresponds to having all desired bits at apartic5lar val5e 3typically “'!4$ ,he P1# programmer can be

5sed to set desired bits to the opposite val5e$ 6n bipolar P1#s this is done by vapori0ing tiny .5sible lin+s

inside the P1# corresponding to each bit$ A lin+ is vapori0ed by selecting it 5sing the P1#;s address

and data lines" and then applying a highvoltage p5lse 3'(>(V4 to the device thro5gh a special inp5t pin$

-arly reliability problems with vapori0ed lin+s technology were

solved and reliable .5siblelin+ technology is 5sed now days notonly in bipolar P1#s b5t also in the bipolar PLD circ5its$


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Commercial 1# ,ypes

-rasable programmable readonly memory 3-P1#4: -P1# is programmable @5st li+e P1#$ 6n addition it also can be “erased! to all 'sstate by e/posing it

to 5ltraviolet light$ -P1# 5ses a di..erent technology called “.loatinggate #1S!$ -P1# man5.act5rers g5arantee that a properly programmed

bit will retain E(I o. its charge .or at least '( years even i. thepart is stored at '2o C$

6ns5lating material s5rro5nding the .loating gate becomesslightly cond5ctive i. it is e/posed to 5ltraviolet light with acertain wavelength which provides .or the -P1# content to beerased$

#ost common application o. -P1#s is to store programs in

microprocessor systems$ -P1#s are typically 5sed d5ring development$ 1#s and

P1#s are 5sed once the program is .inali0ed beca5se 5s5allythey cost less than -P1#s o. similar capacity$


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Commercial 1# ,ypes

-lectrically -rasable Programmable ead1nly #emory3--P1#4$ 6t is li+e and -P1# e/cept that individ5al stored bits

may be erased electrically$

%loating gates in an --P1# are s5rro5nded by am5ch thinner ins5lating layer and can be erased byapplying a voltage o. the opposite polarity as thecharging voltage to the non.loating gate$

Large --P1#s 3'# bit and larger4 allow erasing onlyin .i/edsi0e bloc+s" typically '28'2 Fbits 3'BB

Fbytes4 at a time$ ,hese memories are typicallycalled .lash -P1#s or .lash memories$

--P1# can be reprogrammed only a limited n5mbero. times 36ns5lating layer wares o..4$


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Logic Symbols .or standard -P1#s in28pin d5al inline pac+ages$


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1# Applications

6n addition to the most common application o. 1#s.or program storage in microprocessor systems" thereare many other applications that can provide a lowcost reali0ation o. a comple/ or “random!

combinational logic .5nction$ -/ample o. Voice Signals:

*hen an analog voice signal enters a typicaltelephone systems" it is sampled 8"((( times persecond and converted into a se5ence o. 8bit bytesrepresenting the analog signal at each samplingpoint$

,his e/ample will show how 1#based circ5its caneasily deal with this highly encoded in.ormation$


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Coding Voice Samples

,he simplest 8bit encoding o. the sign andamplit5de o. an analog signal wo5ld be an8bit integer in the two;s complement orsignedmagnit5de system$

8bit linear encoding yields a dynamic rangeo. only 28 J 2B di..erent val5es$

,his corresponds to a dynamic range insignal power o. 2(Klog32B48d9$

9y comparison" compact a5dio dis+s 5se a'Bbit linear encoding with a theoreticaldynamic range o. 2(Klog32'B4MBd9


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Coding o. Voice Samples ?orth American telephone networ+ 5ses an 8bit compo5nded encoding

called N=law PC# 3p5lse code mod5lation4$ ,he ne/t .ig5re shows the .ormat o. an 8bit coded byte: a sort o. .loating

point representation containing sign 3S4" e/ponent 3-4 and mantissa 3#4.ields$

,he analog val5e V represented by a byte in this .ormat is given by the.orm5la: V J 3'2s4KO32-4K32#>>4>>Q

An analog signal represented in this .ormat can range .rom8'MK+ to 8'MK+" where + is arbitrary scale .actor$

,he range o. the signals is 2K8'M and the smallest di..erence that can berepresented is only 2 3when -J(4" so the dynamic range is 2(Klog38'M4E8d9$

sign e/ponent mantissa

E B > 2 ' (

S - #


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Coding o. Voice Samples

6n many types o. phone connections voice signal is p5rposelyatten5ated by a .ew decibels to ma+e things wor+ better$

&iven a N=law PC# byte" a digital atten5ator m5st prod5ce adi..erent PC# byte that represents the original analog signalm5ltiplied by a speci.ied atten5ation .actor$

1ne way to b5ild a digital atten5ator is shown in the ne/t.ig5re$ -ach bloc+ in the .ig5re can be b5ild with perhaps a do0en

#S6 chips or a CPLD or %P&A

Nlaw tolinear

decoder

8

'/'

m5ltiplier

'

'

linear toNlaw

encoder

8'


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Coding o. Voice Samples

Alternative reali0ation o. digitalatten5ator can be done 5sing a singleine/pensive 8+/8 1# instead$

,his 1# can apply any o. >2di..erent atten5ation .actors to a N=law inp5t byte$

igh orderaddress bits select a table"and the low order address bits selectan entry$


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Digital Con.erence Circ5it

6n the analog telephone networ+" it is easy to ma+e a con.erenceconnection between three or more parties: )5st connect the analog phone wires together and yo5 get an analog

s5mming @5nction$ 6n the digital networ+" digital con.erence circ5it m5st incl5de a

digital adder that prod5ces o5tp5t samples corresponding to the

s5ms o. the inp5t samples$ *e have seen how to create binary adders .or 8bit operands$

owever" binary adders cannot process N=law PC# bytes directly$ ,he 8bit N=law PC# bytes m5st be converted to 'bit linear .ormat" ,he signals then can be added" es5lting signal m5st then be converted to 8bit N=law PC# as in

previo5s e/ample$

Again" one co5ld create a comple/ adder or alternatively the same.5nction be per.ormed by a single BF / 8 1#$ ,he 1# has 'B address inp5ts accommodating two 8bit N=law PC#

operands$ %or each pair o. operand val5es" the corresponding 1# address

contains the precomp5ted 8bit N=law PC# s5m$


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1#based Designs 3Advantages4

Previo5s two e/amples ill5strate many advantages o. b5ilding comple/combinational .5nctions with 1#s$

#ost comple/ .5nctions: Are generally di..ic5lt to design with a c5stom digital logic 1# reali0ation o. those .5nctions is alternatively straight .orward$

%or a moderately comple/ .5nction" a 1#based circ5it is 5s5ally .asterthan a circ5it 5sing m5ltiple SS67#S6 devices and PLDs" and o.ten .asterthan an %P&A or c5stom LS6 chip in a comparable technology$

,he program that generates the 1# contents can easily be str5ct5red tohandle 5n5s5al or 5nde.ined cases that wo5ld re5ire additional hardware inany other designs$ %or e/ample adder .5nction o. the previo5s e/ample caneasily handle o5to.range s5ms$

A 1#;s .5nction is easily modi.ied @5st by changing the stored pattern"5s5ally witho5t changing any e/ternal connections$ %or e/ample" the PC#atten5ator and adder 1#;s in the previo5s e/ample can be changed to 5se8bit A=law PC#" the standard digital voice coding in -5rope$

,he prices o. 1#s and other str5ct5red logic devices are always dropping"ma+ing them more economical and their densities are always increasing"e/panding the scope o. problems that can be solved with a single chip$


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1#based Designs3Disadvantages4

%or a simple to moderately comple/.5nctions" a 1#based circ5it may cost more" cons5me more power" or r5n slower

then a circ5it 5sing a .ew SS67#S6 devices andPLDs or small %P&A$

%or .5nctions more than 2( inp5ts" a 1#based circ5it is impractical beca5se o. the

limit on 1# si0es that are available$ %ore/ample" one wo5ldn;t b5ild a 'Bbit adderin 1# = it wo5ld re5ire billions and billionso. bits$


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Comple/ Programmable LogicDevices

Since their inception years ago" programmable logicdevices have been very .le/ible wor+horses o. digitaldesign$

As 6C technology advanced" there was nat5rally greatinterest in creating larger PLD architect5res to ta+eadvantage o. increased chip density$ ,he 5estion iswhy didn;t man5.act5rers @5st scale the e/istingarchitect5resR

%or e/ample" i. DA# densities increased by a .actoro. B over the last '( years" why co5ldntman5.act5res scale the 'BV8 3'B inp5t signals and itscomplements" and a n5mber o. 'Bvariable prod5ctterms4 to create a “'28VB!R S5ch device wo5ld haveB 671 pins" and some n5mber 3say 84 o. '28variableprod5ct terms .or each o. its '28 logic macrocells$


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Comple/ Programmable LogicDevices

,his new chip “'28VB! co5ldcombine the .5nctions o. a largercollection o. 'BV8 and o..er terri.ic

per.ormance and .le/ibility 5sing anyinp5t in any o5tp5t .5nctionR

,his new chip wo5ld be very .le/ibleb5t it wo5ld not have a goodper.ormance$


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ow to e/pand PLD architect5reR

6ncrease T o. inp5ts and o5tp5ts in a conventionalPLDR -$g$" 'BV8 U 2(V8 U 22V'($ *hy not U >2V'B U '28VB R

Problems: n times the n5mber o. inp5ts and o5tp5ts re5ires n2

as m5ch chip area too costly logic gets slower as n5mber o. inp5ts to A?D array

increases

Sol5tion: m5ltiple PLDs with a relatively smallprogrammable interconnect$ Less general than a single large PLD" b5t can 5se

so.tware “.itter! to partition into smaller PLD bloc+s$


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CPLDs vs$ %P&As

CPLDarchitect5re:

Small n5mber o.largishPLDs 3e$g$" “>BV'8!4on a single chip

Programmableinterconnect betweenPLDs


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CPLDs vs$ %P&As

%P&Aarchitect5re

#5ch larger n5mber o.smaller programmablelogic bloc+s$

-mbedded in a sea o.lots and lotso. programmableinterconnect$


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CPLD .amilies

6dentical individ5al PLD bloc+s 3ilin/ “%9s!4replicated in di..erent .amily members$ Di..erent n5mber o. PLD bloc+s Di..erent n5mber o. 671 pins

#any CPLDs have .ewer 671 pins than macrocells “95ried! #acrocells provide needed logic terms

internally b5t these o5tp5ts are not connectede/ternally$

6C pac+age si0e dictates T o. 671 pins b5t not the

total T o. macrocells$ ,ypical CPLD .amilies have devices with di..ering

reso5rces in the same 6C pac+age$


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ilin/ CPLDs

?otice overlap in reso5rce availability in a partic5lar pac+age$


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ilin/ CPLDs

Another .eat5re o. this .amily is that a given chip" s5ch asCCM'(8 is available in several di..erent pac+ages$ ,his isimportant not only to accommodate di..erent man5.act5ringpractices b5t also to provide some choice and potential savings inthe n5mber o. e/ternal 671 pins provided$ 6n most applications" itis not necessary .or all internal signal o. a state machine or

s5bsystem to be visible to and 5sed by the rest o. the system$ ,h5s" even tho5gh the CM'(8 has '(8 macrocells" the o5tp5tso. at most BM o. them can be connected e/ternally in the 8pinPLCC version o. the device$ 6n .act many o. the BM 671 pins wo5ld typically be 5sed .or inp5ts" in

which case even .ewer o5tp5ts wo5ld be visible e/ternally$ ?ote that the remaining macrocell o5tp5ts are still 5ite 5sable

internally" since they can be hoo+ed 5p internally thro5gh the CPLD;s

programmable interconnect$ #acrocells whose o5tp5ts are 5sable only internally are sometimes

called buried macrocells$


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ilin/ M((.amily CPLDarchitect5re

671 pins can be 5sed as inp5t" o5tp5t or bidirectionalpins according to the device;s programming$

Special p5rpose pins: &SF = global cloc+

&S = global set7reset &,S = global threestate controlsG

one o. these signals can be selected in eachmacrocell to o5tp5t enable the corresponding o5tp5tdriver when the macrocell;s o5tp5t is hoo+ed 5p to ane/ternal 671 pin$

1nly %9;s are shown in the previo5s schematicdiagram" however" CM(( architect5re scales toaccommodate 'B %bs in th CM288$


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ilin/ M((.amily CPLDarchitect5re

egardless o. the speci.ic .amily member" each %9programmably receives >B signals .rom the switchmatri/$

,he inp5ts to the switch matri/ are the '8 macrocell

o5tp5ts .rom each o. the %9s and the e/ternal inp5ts.rom the 671 pins$ -ach %9 also has '8 o5tp5ts that r5n “5nder! the

switch matri/ as shown in the previo5s .ig5reconnecting to the 671 bloc+s$

,hese are merely the o5tp5tenable signals .or the671 bloc+ o5tp5t driversG ,hey are 5sed when the %9 macrocell;s o5tp5t is

hoo+ed 5p to an e/ternal 671 pin$


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M((.amily .5nction bloc+s 3%9s4architect5re

'8 macrocells per %9

>B inp5ts per %9 3partitioning challenge" b5t alsoreason .or relatively compact si0e o. %9s4

#acrocell o5tp5ts can go to 671 cells or bac+ intoswitch matri/ to be ro5ted to this or other %9s$


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M((.amily .5nction bloc+s 3%9s4architect5re

,he basic CM(( %9 programmableA?D array has @5st M( prod5ct terms$

owever" it also has product-term

allocation$ ,his mechanism allows a macrocell;s

5n5sed prod5ct terms to be 5sed byother nearby macrocells in the same %9$

?e/t slide depicts a logic diagram o. theCM(( prod5ctterm allocator andmacrocell$


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M((series macrocell 3'8 per %94

Up to 5 productterms

Programmableinversion or XORproduct term

Global clock or product-term clock

Set control

Reset control

OE control


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M((series prod5ctterm allocator

programmablesteeringelements

Share terms fromabove and below


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Switch matri/ .or CM'(8 Co5ld be anything .rom a

limited set o. m5ltiple/ers to a.5ll crossbar$

#5ltiple/er small" .ast" b5tdi..ic5lt .itting

Crossbar easy .itting b5tlarge and slow

%inding a complete set o.connections thro5gh a sparseswitch matri/ is ?Pcompleteproblem$

%or each di..erent CPLDbaseddesign" a set o. switchmatri/connections m5st be .o5nd be

“.itter! so.tware$ ,ypically this so.tware

together with overall CPLDdesign are part o.man5.act5rers “secret sa5ce!


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%P&As

istorically" %P&A architect5res and companies began aro5nd thesame time as CPLDs$ ilin/ la5nched the world;s .irst commercial %P&A in 'M8" with the

vintage C2((( device .amily$ C>((( and C((( .amilies soon .ollowed" setting the stage .or

today;s Spartan and Virte/ device .amilies$

-ach evol5tion o. devices bro5ght improvements in density"per.ormance" voltage levels" pin co5nts" and .5nctionality$ ,h5s C(((" Spartan and Spartan7L devices have the same basic

architect5re$ %P&As are closer to “programmable AS6Cs! large emphasis on

interconnection ro5ting ,iming is di..ic5lt to predict m5ltiple hops vs$ the .i/ed delay o. a

CPLD;s switch matri/$ 95t more “scalable! to large si0es$

%P&A programmable logic bloc+s have only a .ew inp5ts and ' or 2.lip.lops" b5t there are a lot more o. them compared to then5mber o. macrocells in a CPLD$


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&eneral %P&A chip architect5re

a$+$a$ CL9 “con.ig5rable logicbloc+!


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ilin/ (((series %P&As


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%P&A specsmanship

,wo .lip.lops per CL9" pl5s two per671 cell$

2 “gates! per CL9 i. 5sed .or logic$

>2 bits o. A# per CL9 i. not 5sed .orlogic$

All o. this is valid only i. yo5r designhas a “per.ect .it!$


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Con.ig5rable Logic 9loc+ 3CL94


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CL9 .5nction generators 3%" &" 4

2' single port A#$ A# is loaded .rom an e/ternal P1# at system

initiali0ation$ 9road capability 5sing %" &" and :

Any 2 .5ncs o. vars" pl5s a .5nc o. > vars

Any .5nc o. vars Any .5nc o. vars" pl5s some .5ncs o. B vars Some .5ncs o. M vars" incl5ding parity and bit

cascadable e5ality chec+ing


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Dedicated %ast Carry and 9orrowLogic

,he % and & .5nction generators o. the C((( .amily have: separate dedicated logic .or .ast carry and borrow generation" with dedicated ro5ting to lin+ the e/tra signal to the .5nction

generator in the ad@acent CL9$ 1ne .5nction generator 3%4 can be 5sed to add a(b(" and

Second .5nction generator 3&4 can generate a'b'$ ,he .ast carry will .orward the carry to the ne/t CL9 above

or below$

%ast carry and borrow logic increases the e..iciencyper.ormance o. adders" s5btractors" acc5m5lators"

comparators" and co5nters$


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CL9 inp5t and o5tp5t connections b5ried in the sea o. interconnect


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C((( 6nterconnect eso5rces

6n the C((( there is a rich set o. connections between singlelength lines and the CL9 inp5ts and o5tp5ts$ Capabilities .or nearestneighbor and acrossthechip connection

between CL9s$ ,wo “single! gro5ps are optimi0ed .or .le/ible connectivity between

ad@acent bloc+s witho5t the small n5mber o. 5nidirectional limitation o.wires in the “Direct Connect! gro5ps$

*ith “single! wires it is possible to connect a CL9 to another that;smore than one hop away" b5t they wo5ld have to go thro5gh aprogrammable switch .or each hop which adds delay$

*ires in the “Do5ble! gro5ps travel past two CL9s be.ore hitting aswitch" so they provide shorter delays .or longer connections$

,he “Long! gro5ps o. wires do not go thro5gh any programmableswitches at all: instead" they travel all the way across or down a row orcol5mn and are driven by threestate drivers near the CL9$


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Detail connections controlled byA# bits


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Programmable Switch #atri/ 3PS#4

-ach diamond in the shaded area indicating PS#: 6s a programmable switch element 3SP-4 that can

connect any line to any other as shown in the ne/tslide 5nder 3b4$

*hile the PS# is essential" 5sing it has a price =signals inc5r a small delay each time they hopthro5gh a PS-$

igh5ality %P&A .itter so.tware searches .or not @5st any CL9 placement and wire connections thatwor+$

,he “placement and ro5ting! tool spends a lot o. timetrying to optimi0e device per.ormance by .inding aplacement that allows short connections" and thenro5ting the connections themselves$


60/63


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,he .itter;s @ob

Partition logic .5nctions into CL9s Arrange the CL9s 6nterconnect the CL9s

#inimi0e the n5mber o. CL9s 5sed #inimi0e the si0e and delay o. interconnect

5sed *or+ with constraints

“Loc+ed! 671 pins Criticalpath delays Set5p and hold times o. storage elements


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671 bloc+s


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Problems common to CPLDs and%P&As

Pin loc+ing Small changes" and certainly large ones" can

ca5se the .itter to pic+ a di..erent allocation o.671 bloc+s and pino5t$

Loc+ing too early may ma+e the res5lting circ5itslower or not .it at all$ 5nning o5t o. reso5rces

Design may “blow 5p! i. it doesn;t all .it on asingle device$

1nchip interconnect reso5rces are m5ch richerthan o..chipG e$g$" barrelshi.ter e/ample$ Larger devices are e/ponentially more

e/pensive$

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Programmable Logic and Storage Devices(2)