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EET 3143 Programmable Logic Devices Michigan Technological University Electrical Engineering Technology Instructor: Dr. Nasser Alaraje

EET 3143 Programmable Logic Devices

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EET 3143 Programmable Logic Devices. Michigan Technological University Electrical Engineering Technology Instructor: Dr. Nasser Alaraje. Contact Information. Name : Abdulnasser (Nasser) Alaraje Office : 417 EERC Building Phone (O): 487-1661 Email : [email protected] - PowerPoint PPT Presentation

Text of EET 3143 Programmable Logic Devices

Slide 1

EET 3143 Programmable Logic DevicesMichigan Technological UniversityElectrical Engineering TechnologyInstructor: Dr. Nasser Alaraje

Slide -2Contact InformationName: Abdulnasser (Nasser) AlarajeOffice: 417 EERC BuildingPhone (O): 487-1661Email: [email protected] Hours: MWF 10:00 am 12:00 pm (or by appointment)

Slide -23Practical CourseCourse Objectives:Upon Successful completion of this course, students should:Learn how to use HDL for modeling basic building blocks of digital systemLearn FPGA technology and the impact of using FPGA in logic designLearn FPGA design flow using Alteras Quartus II development softwareGain FPGA design experience by synthesizing, mapping, and placing and routing a given design on Alteras DE2 FPGA evaluation boardWork in groups of two or three and thereby learn how to cooperate in teamsGain a basic understanding of timing analysisLearn how to build SDC files for constraining FPGA designsLearn how to verify timing on simple design using the TimeQuest analyzerSlide -4Why FPGA?Respond to the Market needs of Skilled FPGA EngineersFPGA-based re-programmable logic design became more attractive as a design medium during the last decadeonly 19.5 % of 4-year and 16.5 % of 2-year electrical and computer engineering technology programs at US academic institutions currently have a curriculum component in hardware description language and programmable logic design Curriculum has not yet caught up to industry needs. industry must be driving the curriculum development.

Slide -What projects are FPGAs good forAerospace & DefenseRadiation-tolerant FPGAs along with intellectual property for image processing, waveform generation, and partial reconfiguration for SDRs. AutomotiveAutomotive silicon and IP solutions for gateway and driver assistance systems, comfort, convenience, and in-vehicle infotainment. BroadcastSolutions enabling a vast array of broadcast chain tasks as video and audio finds its way from the studio to production and transmission and then to the consumer. ConsumerCost-effective solutions enabling next generation, full-featured consumer applications, such as converged handsets, digital flat panel displays, information appliances, home networking, and residential set top boxes. Industrial/Scientific/MedicalIndustry-compliant solutions addressing market-specific needs and challenges in industrial automation, motor control, and high-end medical imaging. Storage & ServerData processing solutions for Network Attached Storage (NAS), Storage Area Network (SAN), servers, storage appliances, and more. Wireless CommunicationsRF, base band, connectivity, transport and networking solutions for wireless equipment, addressing standards such as WCDMA, HSDPA, WiMAX and others. Wired CommunicationsEnd-to-end solutions for the Reprogrammable Networking Linecard Packet Processing, Framer/MAC, serial backplanes, and more 5Slide -5Who uses themwww.fpgajobs.com

6Slide -6Why are they importantThey have the ability to revolutionize the way that prototyping is done.Allows companies to get to market quicker and stay in market longer.

7Slide -7XilinxLargest manufacturer of HW Develop hardware and softwareEmbedded PowerPCUniversity Program8Slide -8AlteraSecond largest manufacturerDevelop HW and SWUniversity Program9Slide -9It dependsTimeExisting resourcesMoney Level of effortPreferenceWhich is best?10Slide -10Hardware/Software? Software:Quartus Software

Hardware: DE2 FPGA board11Slide -11

Welcome to the Quartus II Software!Turn on or off inTools Options12Slide -Can be turned off turn it back on through Tools -> Options -> General

However you can also start tutorials, start or open designs.

Tutorial can be started through Help menu as well as Web links.Altera DE2 Development Board

13Slide -1314EntityDescribes all inputs and outputsEvery VHDL design must has at least one entityRequires the use of Identifiers for naming the entity itself as well as the inputs and outputsEntity is a keyword and is reserved in VHDL for this purposeentity isport (signal identifier);end entity ENTITY Or2 IS PORT (x: IN std_logic; y: IN std_logic; F: OUT std_logic);END Or2;

Slide -15ArchitectureArchitecture declaration is where the operation of the logic function is specifiedFor each entity there must be a corresponding architectureEach architecture must be associated by name with an entityarchitecture < architecture name> of isbeginThe description of the logic function goes hereend architecture ARCHITECTURE Or2_beh OF Or2 ISBEGIN

PROCESS(x, y) BEGIN F VHDL statement; when others =>VHDL statements;end case;Slide -23Processes in VHDLProcesses Describe Sequential BehaviorProcesses in VHDL Are Very Powerful StatementsAllow to define an arbitrary behavior that may be difficult to represent by a real circuitNot every process can be synthesizedUse Processes with Caution in the Code to Be SynthesizedUse Processes Freely in TestbenchesSlide -24Logic OperatorsLogic operators

Logic operators precedenceand or nand nor xor not xnor notand or nand nor xor xnorHighestLowestonly in VHDL-93Slide -24No order precedents

Logic Operators - exampleOrder of evaluationNeed to describe XOR using and, or, notC = a and not b or not a and bWill be interpreted as:C = ((a and (not b)) or (not a) and bC = (ab+a)b not correctNeed to use parentheses as followsC = (a and not b) or (not a and b)Associative logical operatorand, or, xor, xnor are associative.f tclk, clr => tclr, sload => tsload, cnt_en => tcnt_en, data => tdata, q => tq);top_countercounterclkclrcnt_ensloaddataqtclktclrcnt_entsloaddatatq16Slide -253254Complete Code LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_arith.all;

ENTITY top_counter ISPORT (tclk, tclr, tsload, tcnt_en : IN std_logic;tdata : IN std_logic_vector (15 DOWNTO 0);tq : OUT std_logic_vector (15 DOWNTO 0));END ENTITY top_counter;ARCHITECTURE logic OF top_counter IS

COMPONENT pcounterGENERIC (width : INTEGER);PORT (clk, clr, sload, cnt_en : IN std_logic;data : IN std_logic_vector (width - 1 DOWNTO 0);q : OUT std_logic_vector (width - 1 DOWNTO 0));END COMPONENT;

BEGIN

u1 : pcounter GENERIC MAP (width => 16) PORT MAP (clk => tclk, clr => tclr, sload => tsload, cnt_en => tcnt_en, data => tdata, q => tq);

END ARCHITECTURE logic;Slide -254255Generate StatementsUsed to create structural blocksResolved at compile timeReduce amount of codeCan be nestedFor-generateCreates zero or a set number of duplicates of a structureNo need to individual instantiate each duplicateIf-generateConditionally selects whether zero or one structure is madeSlide -255256For-GenerateSyntax

Sets the number of structures createdSimilar to FOR loopCan only use concurrent statementsLabel is requiredlabel : FOR IN GENERATE--concurrent statementsEND GENERATE label;

Slide -256PARITY: Block Diagram

257Slide -PARITY: Entity DeclarationLIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC );END parity;

258Slide -PARITY: Block Diagram

xor_out(1)xor_out(2)xor_out(3)xor_out(4)xor_out(5)xor_out(6)259Slide -PARITY: ArchitectureARCHITECTURE parity_dataflow OF parity IS

SIGNAL xor_out: std_logic_vector (6 downto 1);

BEGIN

xor_out(1)