CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to PALsIntroduction to PALsProgrammable Array LogicProgrammable Array Logic

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Programmable Array Logic (PAL)Programmable Array Logic (PAL)

Developed by John Birkner & Hua-Thye ChuaDeveloped by John Birkner & Hua-Thye Chua

Monolithic Memories, Inc.Monolithic Memories, Inc.1976 1976

Used to implement functions in Boolean equation Used to implement functions in Boolean equation formform

(Recall PROM used tabular form)(Recall PROM used tabular form)

More efficient use of IC real estateMore efficient use of IC real estateDevelopers continued into FPGAsDevelopers continued into FPGAs

Co-founders of QuicklogicCo-founders of Quicklogic

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Programmable Array Logic (PAL)Programmable Array Logic (PAL)

AND array inputs are programmableAND array inputs are programmableOR array connections are fixedOR array connections are fixed

The output of each AND gate is permanently The output of each AND gate is permanently connected to an OR gateconnected to an OR gateProduct terms cannot be shared by OR gatesProduct terms cannot be shared by OR gates

Simplified PAL block diagram:Simplified PAL block diagram:

Fixed

Connections

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PAL Block PAL Block DiagramDiagram

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs

A more realistic block diagram of a PAL A more realistic block diagram of a PAL would show multiple inputs and outputswould show multiple inputs and outputs

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PAL Architecture: SimplifiedPAL Architecture: Simplified

Inputs are available in both Inputs are available in both true and inverted formtrue and inverted form

Multiple input AND gatesMultiple input AND gates

Each OR gate has a Each OR gate has a specific number of specific number of product terms as fixed product terms as fixed inputsinputs

Outputs from OR gatesOutputs from OR gates

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Using PALs: An ExampleUsing PALs: An Example

P 1

P 2

x 1 x 2 x 3

P 3

P 4

321212

3213211

xxx'x'xf

x'x'x'xxxf

Implement the following:

AND plane

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Using PALs: An ExampleUsing PALs: An Example

P 1

P 2

x 1 x 2 x 3

P 3

P 4

321212

3213211

xxx'x'xf

x'x'x'xxxf

AND plane

P4P3

P2P1

f1

f2

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PAL Architecture: More RealisticPAL Architecture: More Realistic

Six (6) inputs are Six (6) inputs are available in both true available in both true and inverted formand inverted formTwelve (12) input Twelve (12) input AND gatesAND gatesEach OR gate has a Each OR gate has a four (4) product terms four (4) product terms as fixed inputsas fixed inputsFour (4) outputsFour (4) outputs

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PAL Architecture: More RealisticPAL Architecture: More Realistic

The fact that the AND The fact that the AND array is programmable array is programmable makes it possible for makes it possible for these devices to have these devices to have many inputsmany inputsThe fact that the OR The fact that the OR array is fixed makes array is fixed makes the devices small the devices small (which means less (which means less expensive) and fastexpensive) and fast

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PAL ArchitecturePAL Architecture

An actual PAL deviceAn actual PAL devicePAL16L8PAL16L8

32 input AND gates32 input AND gatesup to 8 output functionsup to 8 output functions

See Figure 7-24 in the See Figure 7-24 in the Sandige bookSandige book

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PAL Outputs Can Be LatchedPAL Outputs Can Be Latched

Typical PALs have:Typical PALs have:from 10 to 20 inputsfrom 10 to 20 inputsfrom 2 to 10 outputsfrom 2 to 10 outputsfrom 2 to 8 AND gates driving each OR gatefrom 2 to 8 AND gates driving each OR gateoften include D flip-flopsoften include D flip-flops

f 1

To AND plane

D Q

Clock

Select Enable

Flip-flop

MUX output is “fed back” to the AND plane.

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Understanding the PAL DiagramUnderstanding the PAL Diagram

A portion of the Realistic PAL diagram shown earlier

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Understanding the DiagramUnderstanding the Diagram

Horizontal Lines indicate a product term. Vertical lines provide True and Complemented forms of external inputs.

Although product terms appear to have only one input, it actually has 2*n inputs, for n external inputs.

D J

P

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PAL Product TermsPAL Product Terms

This looks like an AND gate with one input. It is actually many more: B

B’AA’CC’

H’H

Drawn with a single line (above) to save space.

B B’A A’ C C’ D D’ I I’ J J’ E E’ F F’ K K’GG’H H’

P

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D J

P

Fuse PointsFuse Points

A cross over of a Vertical input line and a horizontal product term line is a FUSE LOCATION. When the PAL is in its blank or erased state, all FUSES are connected. This means that each product term implements the equation:

( A A’ B B’ C C’……. KK’) which will be ‘0’! This means that the output will be high!

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D J

P

PAL ProgrammingPAL Programming

To program, we will BLOW most of the fuses (break the vertical/horizontal crossover connection). To indicate a logic function, will use an ‘ X ‘ over a fuse will be kept INTACT.

Will mark intact fuse location

When a fuse is blown, that product term input acts as a permanent logic ‘1’ so that the input no longer effects the product term.

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An Example: P’ = D + J’An Example: P’ = D + J’

When implementing an equation, sometimes will not want to use all available product terms. If ALL fuses along product term are left intact, then product term value will be ‘0’ and will not affect equation. Mark unused AND gates by placing an X over them as shown.

D J

P

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Example Product Term AC’H’Example Product Term AC’H’

The connections will be:

B B’A A’ C C’ D D’I I’ J J’ E E’ F F’ K K’GG’H H’

11A11C’

H’1

Fuse blown

Fuse blown

Fuse intactFuse blown

Fuse blownFuse intact

Fuse blown

Fuse intact

Actually, fuses are not ‘blown’ in eraseable PLDs - the connection is broken in a non-destructive way.

P

P

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Another ExampleAnother Example

A

B

C

D

G

H

I

J

P

P’ = A’BGH’ + CD’ + HIJ + BG’H

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Alternative PAL DiagramsAlternative PAL Diagrams

Implements sum-of-Implements sum-of-products expressions products expressions Four external inputs (and Four external inputs (and complements)complements)Feedback path from Feedback path from output Foutput F11

Product term connections Product term connections made via fusesmade via fuses

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Implementing a FunctionImplementing a Function

Consider implementing the Consider implementing the following expression:following expression:II1 1 II2 2 II3 3 + + II22’ ’ II33’ ’ II4 4 + + II1 1 II4 4 = = FF11

Note that only functions of up Note that only functions of up to three product terms can be to three product terms can be implementedimplemented

larger functions need to be larger functions need to be chained together via the chained together via the feedback pathfeedback path

xx x x

x xxx

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10 primary inputs10 primary inputs8 outputs, with 7 AND gates per 8 outputs, with 7 AND gates per outputoutput1 AND used for 3-state enable1 AND used for 3-state enable6 outputs available as inputs6 outputs available as inputs

more inputs, at expense of outputsmore inputs, at expense of outputs

Note inversion on outputsNote inversion on outputsoutput is complement of sum-of-output is complement of sum-of-productsproductsnewer PALs have selectable newer PALs have selectable inversioninversion

Example 7-12 from SandigeExample 7-12 from Sandige

Figure 7-24

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PAL Output MacrocellsPAL Output Macrocells

4 to 1 MUX4 to 1 MUX00 = registered active low00 = registered active low

01 = registered active high01 = registered active high

10 = comb. active low10 = comb. active low

11 = comb. active high11 = comb. active high

2 to 1 MUX2 to 1 MUXOutput feedbackOutput feedback

External inputExternal input

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PAL Output MacrocellsPAL Output Macrocells

Registered modeRegistered mode

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PAL Output MacrocellsPAL Output Macrocells

combinational modecombinational mode