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MOS Transistor Modeling for RF Integrated Circuit Design © C. Enz, March, 2002 MSM 2002 - WCM Tutorial 1 MOS TRANSISTOR MODELING MOS TRANSISTOR MODELING FOR RF IC DESIGN FOR RF IC DESIGN Christian Enz [email protected] Swiss Center for Electronics and Microtechnology © C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 2 INTRODUCTION INTRODUCTION Strong demand for low-cost, small form-factor and low-power transceivers Deep submicron CMOS well suited for wireless High f t and good RF noise performance High integration capabilities Design of RF ICs remains a challenge Crucial to accurately predict performance of RF ICs Requires accurate MOST models valid for all bias from dc to RF and for a large range of geometries

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Page 1: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

1

MOS TRANSISTOR MODELING MOS TRANSISTOR MODELING FOR RF IC DESIGNFOR RF IC DESIGN

Christian Enz

[email protected]

Swis

s C

ente

r for

Ele

ctro

nics

and

Mic

rote

chno

logy

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 2

INTRODUCTIONINTRODUCTIONStrong demand for low-cost, small form-factor and low-power transceiversDeep submicron CMOS well suited for wireless

High ft and good RF noise performanceHigh integration capabilities

Design of RF ICs remains a challengeCrucial to accurately predict performance of RF ICsRequires accurate MOST models valid for all bias from dc to RF and for a large range of geometries

Page 2: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

2

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 3

OUTLINEOUTLINECMOS Technology EvolutionSmall-signal MOS Transistor Modeling at RF

Quasi-Static (QS) ModelNon-Quasi-Static (NQS) Model

MOST Noise Modeling at RFLarge-Signal ModelingModerate and Weak Inversion for RF CircuitsConclusion

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 4

TYPICAL RF MULTIFINGER DEVICETYPICAL RF MULTIFINGER DEVICERF MOS Transistors are usually large devicesImplemented as multi-finger devices due to limited width

G

S

D

S

D

S

Wf

Lf

Nf : # of fingers

Wf : width of a single finger

Lf : length of a single finger

Weff=Nf·Wf : total width

Minimum # of drain diffusions

Page 3: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

3

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 5

TRANSIT FREQUENCY EVOLUTIONTRANSIT FREQUENCY EVOLUTION

H. Iwai and H. S. Momose, “Technology Towards Low-Power / Low-voltage and Scaling of MOSFETs,” Microelectronic Engineering, vol. 39, No. 1-4, pp. 7-30, Dec. 1997.

120

100

80

60

40

20

010-7 10-6 10-5 10-4 10-3

ID / Weff [A/µm]

f t[G

Hz]

Lf =0.07µm

0.11µm

0.16µm

0.26µm0.36µm0.51µm

Nf = 40, Wf = 5 µm, Weff = Nf·Wf = 200 µm,VD = 2 V

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 6

TRANSIT FREQUENCY SCALINGTRANSIT FREQUENCY SCALINGFor L < 0.1 µm larger than 150 GHz can be expected

H. S. Momose et al., IEDM 1996.

21

21

fgg

mt

LCgf ∝⋅=

π

VD = 1.5 Vgm = gm-maxNf = 40Wf = 5 µmWeff = 200 µm

1

10

100

1000

Slope = -2

0.05 0.1 0.2 0.5 1

f t-pea

k[G

Hz]

Lf [µm]

Page 4: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

4

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 7

VD = 1.5 VNf = 40Wf = 25 µmWeff = 1000 µmLf = 0.12 µm

f = 8 GHz

NF m

in[d

B]ID / Weff [A/µm]

10

0

2

4

6

8

10-7 10-6 10-5 10-4 10-3

f = 5 GHz

f = 2 GHz

MINIMUM NOISE FIGUREMINIMUM NOISE FIGURENFmin of 0.5 dB @ 2 GHz can be achieved

25

20

15

10

5

01 2 5 10

4

3

2

1

0

NF m

in[d

B]

Frequency [GHz]G

a [dB]

Ga

NFmin

H. S. Momose et al., IEDM 1996.

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 8

SMALLSMALL--SIGNAL MOST MODELING AT RFSIGNAL MOST MODELING AT RFEquivalent circuit at RFApproximate Y-parameters analysisSubstrate couplingNQS versus QS

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MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

5

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 9

Gate (G)Substrate (B) Source (S) Drain (D) Substrate (B)

MOST EQUIVALENT CIRCUITMOST EQUIVALENT CIRCUITB G DS

RdbRsb

Rd

DdbDsb Rdsb

MiCgso Cgdo

Rg

CgboRs

D

B

G

S

B

di

gi

si

bi db

intrinsic part of compact

model

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 10

SMALLSMALL--SIGNAL INTRINSIC MODELSIGNAL INTRINSIC MODEL

Ims

ImYgdi

Ydsi

Ybdi

Imd

Ybsi

YgsiYgbi

di

bi

gi

si

bi

NQS Model

Ims

Im

Imd

gds

CgdiCgsiCgbi

CdbiCsbi

di

bi

gi

si

bi

QS Model

Both models valid in all modes of operations

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MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

6

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 11

QUASIQUASI--STATIC SMALLSTATIC SMALL--SIGNAL MODELSIGNAL MODEL(in saturation)(in saturation)

gds

Rdsb CdbCsb

CgdIm

Rd

Rg

Cgb

Ims

Cgs

Rs

Rsb Rdb

I1

I2D

G

S

B B

bi db

di

gi

si

V1

V2 ( )( )

ms

ms

m

mqs

qsmsms

qsmm

gC

gC

jgY

jgY

==

−⋅=

−⋅=

τ

ωτωτ

1

1

( ) ( )( )( ) ( )( )biVsiVYI

biVgiVYI

msms

mm−⋅=

−⋅=

Bulk referenced model:

msmsmms

mmmCjgYnY

CjgYω

ω−=⋅=

−=

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 12

SOURCE AND DRAINSOURCE AND DRAINRESISTANCES SCALINGRESISTANCES SCALING

Rvia

RsalRcon

RsdeLdif

Hdif

salicide

effconsdeviasalconsdes WRRRRRRR 1∝+≅+++=

Rs and Rd dominated by contact and source/drain extensions (SDE) resistances

ffeff WNW ⋅≡

Page 7: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 13

S

DG G

R R

Rg2 = R/2 = Rg1/4

S

DG

R R

Rg1 = 2R

gshff

fg R

LNW

R ⋅⋅

⋅⋅≅31κ

1=κ 41=κ

GATE RESISTANCE SCALINGGATE RESISTANCE SCALING

Rgsh is the gate sheet resistance (typically 3 Ω/sq)Rg can usually be made negligible using multi-finger devices and contacting the gate on both sides

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 14

CAPACITANCES SCALINGCAPACITANCES SCALING

effWC ∝eff

ds WRR 1, ∝

The different RC time constants due to Rs and Rd do not depend on Weff but only on the gate length Lf and overlap length LovThe poles due to Rs and Rd are at a much higher frequency than typically the transit frequency ft and can therefore be neglected when calculating the Y-parameters

ffeff WNW ⋅≡

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MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 15

APPROXIMATE YAPPROXIMATE Y--PARAMETERSPARAMETERSAssuming ωRgCgg << 1

( ) ( )( ) ( )gdbdgdbdgggds

gdmgdmgggm

gdgdggg

ggggg

CCjCCCRgY

CCjCCCRgY

CjCCRY

CjCRY

+⋅++⋅+≅

+⋅−+⋅−≅

−−≅

+≅

ωωωω

ωωωω

222

221

212

2211

gbgdgsgg CCCC ++≡

Can be used for direct extraction

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 16

0 2 4 6 8 100

0.5

1Rey11[mA/V]

Frequency [GHz]

0 2 4 6 8 10-0.2

0

0.2Rey12[mA/V]

0 2 4 6 8 100

102030

Rey21[mA/V]

0 2 4 6 8 1001.02.0Rey22

[mA/V]

measured

N-channel, Nf = 10, Wf = 12 µm, Lf = 0.36 µm, VG = 1 V, VD = 1 V

MEASURED vs. ANALYTICALYMEASURED vs. ANALYTICALY--PARAM.PARAM.

analytical

Imy12[mA/V]

0 2 4 6 8 10-3-2-10

Imy11[mA/V]

0 2 4 6 8 1005

1015

0 2 4 6 8 10-8-6-4-20

Imy21[mA/V]

0 2 4 6 8 1002468

Imy22[mA/V]

Frequency [GHz]

Substrate coupling

effect

Cm=0

Without trans-

capacitance

Page 9: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

9

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 17

INTRAINTRA--DEVICE SUBSTRATE COUPLINGDEVICE SUBSTRATE COUPLINGB G DS

Rsb

RdsbDdb(Cjdb)

Dsb(Cjsb)

Rdb

BB

bidbsb

Rd

DdbDsb

MiCgso Cgdo

Rg

CgboRs di

gi

si

RdbRsb

Rdsb

D

B

G

S

B

sb dbbi

BB

bidbsb

[Liu, IEDM 97]

BB

bidbsb

[Tiemeijer, ESSDERC 98]

BB

bidbsb

[Tin, CICC 99]

Eliminate to save 1 node

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 18

SUBSTRATE RESISTANCES SCALINGSUBSTRATE RESISTANCES SCALING

fdb WR 1∝

fsb WR 1∝

S

S

S

D

D

G

B

B

Symmetricsubstrate contacts

S

S

S

D

D

G

B

B

“Horse-shoe”substrate contacts s

sb NR 1∝

ddb NR 1∝

Page 10: MOS TRANSISTOR MODELING FOR RF IC DESIGN

MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

10

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 19

SUBSTRATE NETWORK EXTRACTIONSUBSTRATE NETWORK EXTRACTION (1/2)(1/2)

Assuming Rs << Rds simplifies schematic

22Y 22Y ′

2222 YY dg RandRgdeembeddin

′ →

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 20

SUBSTRATE NETWORK EXTRACTIONSUBSTRATE NETWORK EXTRACTION (2/2)(2/2)

gmb estimated from gmgm extracted from ReY’21 at low-frequencyRsb≈Rdb, Rdsb, Csb and Cdb extracted by local optimization

22Y ′ subY

gdds

subRandCgdeembeddin

CjR

YYY dsgd ω−−′≅ →′ 12222

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MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 21

EXTRACTED EXTRACTED YYsubsubN-channel, Nf = 20, Wf = 10 µm, Lf = 0.5 µm, VG = 1.18 V, VD = 1 V, VS = 0 V

6.0x10-3

5.0

4.0

3.0

2.0

1.0

0.0ReY

sub

and

ImY

sub

[A/V

]

1086420

Frequency [GHz]

Cgb + Csb=334 fF Cdb=114 fF Rdsb=19 ΩRsb=Rdb=180 Ω

meas. sim.

ReYsub

ImYsub

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 22

0 2 4 6 8 100102030

Rey21[mA/V]

0 2 4 6 8 1001.02.0Rey22

[mA/V]

0 2 4 6 8 100

0.5

1Rey11[mA/V]

0 2 4 6 8 10-0.2

0

0.2Rey12[mA/V]

Frequency [GHz]

Imy12[mA/V]

0 2 4 6 8 10-3-2-10

Imy22[mA/V]

0 2 4 6 8 1002468

Imy11[mA/V]

0 2 4 6 8 1005

1015

Imy21[mA/V]

0 2 4 6 8 10-8-6-4-20

Frequency [GHz]

N-channel, Nf = 10, Wf = 12 µm, Lf = 0.36 µm, VG = 1 V, VD = 1 V , EKV v2.6

YY--PARAMETERS VERSUS FREQUENCYPARAMETERS VERSUS FREQUENCYmeasured analyticalsimulation

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MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 23

YY--PARAMETERS VERSUS BIASPARAMETERS VERSUS BIASN-channel, Nf = 10, Wf = 12 µm, Lf = 0.36 µm, f = 1 GHz, VD = 0.5, 1, 1.5 V, EKV v2.6

Imy11[mA/V]

Imy12[mA/V]

Imy21[mA/V]

Imy22[mA/V]

ID / Ispec

0

1

2

-1

-0.5

0

-1

-0.5

0

0

1

2

10-2

10-1

100

101

102

103

Rey11[µA/V]

Rey12[µA/V]

Rey21[mA/V]

Rey22[A/V]

-10

0

10

10-510-410-310-210-1

0

10

20

0102030

measuredsimulation

10-2

10-1

100

101

102

103

ID / Ispec

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 24

MEASURED AND SIMULATED fMEASURED AND SIMULATED fttN-channel, Nf = 10, Wf = 12 µm, Lf = 0.36 µm and Lf = 0.56 µm

VD = 0.5, 1, 1.5 V, EKV v2.6

0.12

4

12

4

102

4

100

Tran

sit F

requ

ency

ft [

GH

z]

0.01 0.1 1 10 100 1000ID / Ispec

weak inv. strong inv.

0.5 V

1 V

VD=1.5 V

1.5 V1 V

0.5 V

meas. (Lf = 0.36 µm) meas. (Lf = 0.56 µm) sim. (EKV v2.6)

Ispec≈184.36µA for Lf=0.36µmIspec≈118.52µA for Lf=0.56µm

25

20

15

10

5

0Tran

sit F

requ

ency

f t [G

Hz]

0.01 0.1 1 10 100 1000ID / Ispec

weak inv. strong inv.

0.5 V 1 V

VD=1.5 V

1.5 V

1 V

0.5 V

meas. (Lf = 0.36 µm) meas. (Lf = 0.56 µm) sim. (EKV v2.6)

Ispec≈184.36µA for Lf=0.36µmIspec≈118.52µA for Lf=0.56µm

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MOS Transistor Modeling for RF Integrated Circuit Design

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 25

Ims

Im Ygdi

gds

Ybdi

Imd

Ybsi

YgsiYgbi

di

bi

gi

si

bi

NONNON--QUASIQUASI--STATIC (NQS) MODELSTATIC (NQS) MODEL( ) ( )( )

( ) ( )( )( ) ( )( )biVdiVYI

biVsiVIbiVgiVYI

mdmd

ms

mm

−⋅=−⋅=

−⋅=

msY

( )( )gdioxn

ngbi

mdnm

YCjY

YY

−−⋅=

−⋅=−

gsi

ms

Y

Y

ω1

1

Source/drain symetry

⇒⇒

gdi

md

YY

gsi

msYY

Gate/bulk "symetry"

⋅−=

⋅−=

gdibdi

bsi

YnY

nY

)1(

)1( gsiY

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 26

NQS TRANSADMITTANCES (1/2)NQS TRANSADMITTANCES (1/2)Normalized source transadmittance given by

1:1

1)sinh(

<<⋅⋅+

≅=≡ qsqsms

msm for

jgY τω

τωλλξ

qsj ωτλ 3)1( ⋅+≡

( )

⋅≅⋅

=+

++⋅= −−

WI

SI

q

qqSTOG

T

f nVVVnU

i

f

ffqs

61

1541

152

3

2

0 1

5104301

ττ

with

)(20 Teffeff UL ⋅≡ µτ

In saturation

with

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 27

NQS TRANSADMITTANCES (2/2)NQS TRANSADMITTANCES (2/2)

0.01

0.1

1

10M

ag ξ

m

0.1 1 10

-180-135

-90-45

04590

135180

Arg

ξm

0.1 1 10ω⋅τqs

full nqs function 1st-order 2nd-order quasi-static

0.01

0.1

1

10

Mag

y21

/ g m

0.1 1 10

-180

-90

0

90

180

Arg

y21

/ g m

[d

eg]

0.1 1 10ω⋅τqs

NMOS in saturationL = 10 µmVG = 0.5, 0.6, 0.7, 0.8,

0.9, 1.0, 1.2, 1.5 V

theory measurements

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 28

NQS ADMITTANCES (1/2)NQS ADMITTANCES (1/2)Admittances are given by

ccoxgsi cCjY ξω ⋅⋅=

oxfeffox CLWC ′⋅⋅=

=++

++⋅⋅=

WIqSI

qq

qqqc

frf

rffc

32

231

)1(

)342(

where)sinh(1)cosh(2

λλλξ

⋅−⋅≡c qsj ωτλ 3)1( ⋅+≡

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 29

2

4

0.12

4

12

Mag

ξc

0.1 1 10 100

-60

-45

-30

-15

0

Arg

ξc

0.1 1 10 100ω⋅τqs

Theory VG–VTO = 0.25 V

VG–VTO = 0.5 V VG–VTO = 1.5 V VG–VTO = 2.5 V

PMOSW = 300 µmL = 300 µm

NQS ADMITTANCES (2/2)NQS ADMITTANCES (2/2)

2

4

0.12

4

12

Mag

ξc

0.1 1 10 100

-60

-45

-30

-15

0

Arg

ξc

0.1 1 10 100ω⋅τqs

full nqs function 1st-order approx. 2nd-order approx.

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 30

NQS SUBCKT RESULTSNQS SUBCKT RESULTSP-channel, Nf = 10, Wf = 12 µm, Lf = 0.76 µm, VG = 1 V, VD = 1 V

-3x10-3

-2

-1

0

1

Re

Y12

[A/

V]

1086420Frequency [GHz]

-3x10-3

-2

-1

0

1

ImY

12 [A/V]

1/(2πτm)=4.5 GHzα1=gm1/gm=1.351/(2πτgs)=7 GHzα2=C2/Cgsi=0.635

Rg-poly=1.7 ΩCgsi=220 fFgm=2 mA/V

ReY12

ImY12

1.0x10-3

0.8

0.6

0.4

0.2

0.0

Re

Y22

[A/

V]

1086420Frequency [GHz]

6x10-3

5

4

3

2

1

0

ImY

22 [A/V]

no nqs

with nqs

ImY22

ReY22

meas. sim. (no nqs) sim. (with nqs)

-4x10-3

-2

0

2

Re

Y21

[A/

V]

1086420Frequency [GHz]

-4x10-3

-2

0

2

ImY

21 [A/V]

no nqswith nqs

no nqs

with nqs

ImY21

ReY21

12x10-3

10

8

6

4

2

0

Re

Y11

[A/

V]

1086420Frequency [GHz]

12x10-3

10

8

6

4

2

0

ImY

11 [A/V]

no nqsReY11

ImY11

with nqs

no nqs

with nqs

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MOS Transistor Modeling for RF Integrated Circuit Design

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 31

NOISE MODEL IN SATURATIONNOISE MODEL IN SATURATION

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 32

CHANNEL THERMAL NOISECHANNEL THERMAL NOISEChannel thermal noise power spectral density (PSD)

msnchnchind gGwithGkTS ⋅=⋅= γ4

γ noise excess factorin saturation and for long-channel

=− SI

WIlongsat 32

21γ

Figure of merit for device in saturation

msatnchsatsatm

ms

m

nchsat gGn

gg

gG ⋅=⇒⋅=⋅=≡ αγγα

Source transconductance

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 33

EFFECT OF VELOCITY SATURATIONEFFECT OF VELOCITY SATURATION

For short-channel devices in SI and saturation ⇒ lateral electrical field larger than critical field ⇒ carrier velocity saturationCarrier velocity limited ⇒ additional charge builds up close to the drain ⇒ additional thermal noise without increase of gm ⇒increase of γsat compared to the long-channel value 2/3

Charge builds-up at drain

high lateralelectrical field

Carrier enter velocity

saturation

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 34

HOT CARRIERS AND EFFECTIVE TEMP.HOT CARRIERS AND EFFECTIVE TEMP.High lateral electric field ⇒ carrier not in thermal equilibrium with lattice ⇒ higher carrier temperature ⇒ higher thermal noise

31

1

K=

+⋅=

mEETT

m

t

xeff

P. Klein, EDL, Aug. 1999.

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EXCESS NOISE FACTOR MODEL (1/2)EXCESS NOISE FACTOR MODEL (1/2)In SI and in saturation, these effects can be included in a modified noise excess factor according

112 −+⋅−⋅=

⋅−≡

effc

SP

effc

SDsatLEVV

LEVVz

)1()1( 21

32 +⋅⋅⋅++⋅= zz

EEzt

csatγ

velocity saturation hot carriers

where

VDsat corresponds to the drain voltage at which the output conductance becomes zero

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 36

EXCESS NOISE FACTOR MODEL (2/2)EXCESS NOISE FACTOR MODEL (2/2)5

4

3

2

1

0Ther

mal n

oise

exce

ss fa

ctor γ

sat

0.12 3 4 5 6 7

12 3 4 5 6 7

10Leff [µm]

Et = Ec = 1 V/µmVG - VT0 = 0.5 V

without hot electrons with hot electrons

VG - VT0 = 0.5 V

VG - VT0 = 0.3 VVG - VT0 = 0.3 V

2/3

CONTR

OVERT

IAL

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 37

drain noise

induced gate noise

INDUCED GATE NOISE (IGN)INDUCED GATE NOISE (IGN)(in saturation)(in saturation)

( ) ( ) ( ) ( )m

gssat

ms

gsngnging g

CgC

GwithGkTS22

54

ωβ

ωδωω ⋅=⋅=⋅=

For long-channel in saturation nand sat 53

4 δβδ ≡=

vnind

ing

S D

G

S D

G

ing

ind

noiselessnoisy piece of channel induced gate noise

drain noise

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 38

CORRELATION FACTOR OF IGNCORRELATION FACTOR OF IGN

+ j

x0 L

0

– jCorre

lation

coeff

icien

t(li

near

regi

on)

source drain

inding

indingSS

Sc

⋅≡ ,

( )+

==

saturationjcVregionlinear

cg

DS 00

For long-channel 4.0≅gc

Watch sign!

Watch sign!

X=0 Ling

ind

vnM1 M2

ing

ind

vnRch1 Rch2

Cgd1 Cgs2

S D

G

ing

ind

noiseless

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 39

NOISY TWONOISY TWO--PORTPORTI1 INout

Ys V1Noisy

two-port

I1in

I2vn

V2V1Noiselesstwo-port

( ) ( ) ( ) ( )fGkTfSfRkTfS ii ⋅≡⋅≡ 44 vvsss jBGY +≡

2

*

n

nncccijBGYvv⋅=+≡

Noise sources vn and in are usually correlated

vRYGGGG

admittancencorrelatio

ciucorrelated

iceduncorrelat

iui ⋅+=+= 2

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 40

NOISE FACTOR & NOISE PARAMETERSNOISE FACTOR & NOISE PARAMETERS

( ) ( )[ ]22min optsopts BBGGRFF −+−⋅+=

s

vG

Fmin, Rv, Gopt and Bopt (or Γopt) are the four noise parameters extracted from noise measurementsF=Fmin for Gs=Gopt AND Bs=Bopt (noise matching)The circuit parameters Gi, Gc and Bc are given by

( )optc

optc

optoptopti

BBRGRF

G

RBGRYG

−=−−

=

⋅+=⋅=

v

v

vv

212min

222

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SIMPLE MOST NOISE ANALYSISSIMPLE MOST NOISE ANALYSISRgI1

Cgs

indgm·Vgsi gmb·Vbsi

Rsub

inrsub

I2

ingV1 V2Vgsi

Vbsi

( )

t

gscoptgsopt

mgsat

subRmbg

subsat

gRmgg

m

satsubg

F

CBBCGg

R

ωω

ωω

αααα

αα

α

⋅+≅

⋅−≅−=⋅≅

⋅++= ≅⋅

⋅≡≅

⋅≡

04.11

1.147.0

1

min

2.0

2

05.0v

induced gate noise

gate resistance

noise

channel noise

substrate noise

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 42

RELATIVE CONTRIBUTION OF IGN (1/2)RELATIVE CONTRIBUTION OF IGN (1/2)1.41.21.00.80.60.40.20.0

(Fm

in −

1) ⋅

f t /

f

0.50.40.30.20.10

f / ft

(1,1,1,0) (1,1,1,1) approx

(1,0,0,0) (1,1,0,0)

0.5

0.4

0.3

0.2

0.1

0.0

Gop

t ⋅ R

o ⋅ f

t / f

0.50.40.30.20.10

f / ft

(1,1,1,0) (1,1,1,1)

(1,0,0,0) (1,1,0,0)

Fmin and Gopt are both strongly sensitive to IGN and Rg, but not to Rsub nor to cg

Switches definition: (Rg, Rsub, IGN (cg=0), IGN (cg≠0))

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1.41.21.00.80.60.40.20.0

Rv /

Ro

0.50.40.30.20.10

f / ft

(0,0,0,0) (1,0,0,0) (1,1,0,0) (1,1,1,1)

1.2

1.0

0.8

0.6

0.4

0.2

0.0

−Bop

t ⋅ R

o ⋅ f

t / f

0.50.40.30.20.10

f / ft

(1,0,0,0) (1,1,0,0) (1,1,1,0) (1,1,1,1)

RELATIVE CONTRIBUTION OF IGN (2/2)RELATIVE CONTRIBUTION OF IGN (2/2)

Rv is dominated by channel noise and a little by substrate (20%) and gate noise (5%), but insensitive to IGN and cg

Bopt is insensitive to Rg, Rsub and IGN but not to cg

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 44

MEAS. AND SIM. NOISE PARAMETERSMEAS. AND SIM. NOISE PARAMETERSN-channel, Nf = 10, Wf = 10 µm, Lf = 0.36 µm, VG = 0.743 V, VD = 1 V, VS = 0 V

EKV v2.6, Z0 = 50 Ω, ID = 1.038 mA, ft = 12.5 GHz

0.1 0.2 0.3 0.4 0.5f / ft

0

0.5

1

1.5

2

NF m

in[d

B]

0.1 0.2 0.3 0.4 0.50

0.0250.05

0.0750.1

0.1250.15

f / ft

Gop

t·Zo

[-]

00.5

11.5

22.5

0.1 0.2 0.3 0.4 0.5f / ft

Rv

/ Zo

[-]

αg=0 and αsub=0

measuresimulation (with ing)analytic

-0.3-0.25-0.2

-0.15-0.1

-0.050

0.1 0.2 0.3 0.4 0.5f / ft

B opt

·Zo

[-]

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 45

Nf = 10, Wf = 12 µm, Lf = 0.36 µmVG = 1.055 V, VD = 1 V, VS = 0 V, fspot = 900MHz

-40 -35 -30 -25 -20 -15 -10 -5 0-80-70-60-50-40-30-20-10

01020

Pin [dBm]

P out

[dBm

]

fund (meas.)2nd (meas.)3rd (meas.)BSIM3v3 (sim.)

-60

-50

-40

-30

-20

-10

0

10

1 100.3 303ID [mA]

P out

[dBm

]

fund (meas.)2nd (meas.)3rd (meas.)BSIM3v3 (sim.)

Nf = 10, Wf = 12 µm, Lf = 0.36 µmPin = -4 dBm, VD = 1 V, VS = 0 V, fspot = 900 MHz

LARGELARGE--SIGNAL MODELSIGNAL MODELStill dominated by the static (dc) I-V non linearity

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 46

MODERATE INV. FOR RF CIRCUITSMODERATE INV. FOR RF CIRCUITSMoving operating points from strong to moderate or even weak inversion offers the following advantages:

Higher current efficiency (higher gm/ID)Lower electrical fields within device

No velocity saturation (1/L2 scaling instead of 1/L)No hot electrons (lower noise excess factor)

Low-voltage operation compatible with the supply voltages required by deep-submicron processes

Higher nonlinearity due to exp I-V lawModerate inversion seems to be a good trade-off

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ININ-- AND EXAND EX--TRINSIC TIME CONSTANTSTRINSIC TIME CONSTANTS

10-12

10-11

10-10

10-9

Tim

e co

nsta

nts

[s]

0.01 0.1 1 10 100 1000

ID / Ispec

108

109

1010

1011

Transit frequency [Hz]strong inv.weak inv.

measured simulated

τiτe

τt

ft (right axis)

m

ggo

m

ggi

extrinsice

intrinsici

tt g

CgC

f+≅+=≡ ττ

πτ

21

N-channel, Nf = 10, Wf = 10 µm, Lf = 0.36 µm, Ispec = 184 µA, VD = 1 V, VS = 0 V

© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 48

CONCLUSIONCONCLUSIONSimple scalable RF MOS model implemented in Spice as a subCKT has been presentedGate resistance, intra-device substrate coupling, NQS effects, thermal noise, induced gate noiseValidated up to 10 GHz, from moderate to strong inversion and for several geometriesFor deep submicron processes, operating points can be moved from strong to moderate inversion

Better current efficiency, no high electrical field effectsGood trade-off for low-voltage

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© C. Enz, March, 2002 MSM 2002 - WCM Tutorial on MOS Transistor Modeling for RF Integrated Circuit Design 49

ACKNOWLEDGMENTSACKNOWLEDGMENTSF. Pengg from CSEMA.-S. Porret, T. Melly and J.-M. Sallese from EPFL

and my former colleagues from ConexantY. Cheng, M. Matloubian, M. Schroter, V. Dellatorre

as well asD. Pehlke, J. Chen, J. Deen and L. Tocci

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[14] H. S. Momose, R. Fujimoto, S. Otaka, E. Morifuji, T. Ohguro, T. Yoshitomi, H. Kimijima, S. I. Nakamura, T. Morimoto, Y. Katsumata, H. Tanimoto and H. Iwai, “RF Noise in 1.5 nm Gate Oxide MOSFETs and Evaluation of the NMOS LNA Circuit Integrated on a Chip,” Proc. of the VLSI Symposium on Technology, June 1998.

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[56] H. J. Park, P. K. Ko and C. Hu, “A Charge Conserving Non-Quasi-Static (NQS) MOSFET Model for SPICE Transient Anal-ysis,” IEEE Transactions on Computer-Aided Design, vol. 10, pp. 629-642, May 1991.

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