Upload
masc0610
View
240
Download
0
Embed Size (px)
Citation preview
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 1/52
CSE 151-- Intro to VLSI Design
Fadi J. Kurdahi
EECS Dept., UC IrvineFall 2011
Lecture 3: Semiconductors
Lecture 4: MOS Transistors intro
Adapted from Digital Integrated Circuits: A Design Perspective, 2nd Ed. PH
2003. © J. Rabaey, A. Chandrakasan, B. Nikolic
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 2/52
Credits
Slides used in this course have been adaptedfrom the following two sources:
• Course slides by the textbook author:
http://bwrc.eecs.berkeley.edu/Icbook/slides.htm
• Course slides adapted from above by:http://bwrc.eecs.berkeley.edu/IcBook/slides_PennState.htm
• Many applets, animations, videos from the internet. Seesources next to each item in the slides.
• All materials on this page and its sub-pages and all linked files are copyright 2003 by Prentice-Hall/Pearson Education, andmay be downloaded and printed for instructional purposes by instructors using the book. Permission is given to incorporateexcerpts of these materials in instructors' classroom presentations and handouts. The following credit line should be included:"Adapted from (complete bibliographic citation). Copyright 2003 Prentice Hall/Pearson."Permission expressly is not given to publish these materials, in either original or modified form, in printed, electronic, or anyother format.
2
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 3/52
3
Overview of Last Lecture• Digital integrated circuits experience exponential
growth in complexity (Moore’s law) and performance
• Design in the deep submicron (DSM) era creates newchallenges
– Devices become somewhat different
– Global clocking becomes more challenging
– Interconnect effects play a more significant role
– Power dissipation may be the limiting factor
• Our goal in this class will be to understand and design
digital integrated circuits in the deep submicron era
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 4/52
4
Goal of this chapter
• Present intuitive understanding of deviceoperation
• Introduction of basic device equations
• Introduction of models for manualanalysis• Introduction of models for SPICE
simulation
• Analysis of secondary and deep-sub-micron effects
• Future trends
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 5/52
Very quick review of basic circuits
• Field
• Current
• Resistance• Capacitance
• Ohm’s law
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 6/52
Electric Field
• E=F/q (F = electric force, q= charge)
++
+
+
++
+
+
--
-
-
--
-
-
E
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 7/52
http://www.absorblearning.com/media/item.action?quick=6l#
Current FlowThe flow of charges through a conductor gives rise to a current
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 8/52
Resistance
• Electrons arescattered as theymove.
• Impedes the flow of
current throughmaterial
• Resistance affectedby: material, length,cross section
• Dissipates power asheat
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 9/52
Factors affecting Resistance
http://phet.colorado.edu/sims/resistance-in-a-wire/resistance-in-a-wire_en.html
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 10/52
Capacitors
http://micro.magnet.fsu.edu/electromag/java/lightning/index.html
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 11/52
http://micro.magnet.fsu.edu/electromag/java/capacitance/index.html
Factors affecting capacitance
•Plate area•Spacing between plates•Type of dielectric•C = e*A/d•e = dielectric•A= area•d = thickness
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 12/52
Ohm’s Law
http://phet.colorado.edu/sims/ohms-law/ohms-law_en.html
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 13/52
Kirchhoff’s Laws
http://en.wikipedia.org/wiki/Kirchhoff%27s_circuit_laws
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 14/52
14
A First-Order RC Network
v out
v in C
R
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 15/52
RC Network Simulation
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 16/52
http://www.youtube.com/watch?v=8Pnsbh0DrE4
Conductors, insulators and Semiconductors
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 17/52
17
Semiconductors
• Pure semiconductors have low and equalconcentrations of electrons and holes low electrical conductivity
• Si has 4 valence electrons
• Phosphorous, arsenic, etc.. Have 5 electrons provide one free electron
• Silicon doped w/these material becomes n-type
• Dual argument applies for trivalent material (e.g.
Boron, gallium) p-type
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 18/52
18
Venturecaplaw | FEBRUARY 10, 2010
Semiconductor Devices Module 1 Theory Lesson 1 Segment 4 set1s4,
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 19/52
19
Intrinsic and Extrinsic Semiconductors
http:// www.youtube.com/watch?v=o-PPbmMm0eA&feature=related
S i d t
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 20/52
20
Semiconductors
Source: http://php.scripts.psu.edu/users/i/r/irh1/SWF/Semiconductors.swf
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 21/52
21
The Diode
n
p
p
n
B ASiO2
Al
A
B
Al
A
B
Cross-section of pn-junction in an IC process
One-dimensionalrepresentation diode symbol
Mostly occurring as parasitic element in Digital ICs
Dopedw/acceptorimpurities
(e.g. Boron).Mostly Holes
Dopedw/donor
impurities(e.g.
Phosphorus).Mostly
Electrons
Diodes
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 22/52
Diodes
22http://www.youtube.com/watch?v=W6QUEq0nUH8&feature=related
Di d P i
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 23/52
Diode Properties
23http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/diode.html
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 24/52
24
Review: DiodeThe ideal diode equation (for both forward and reverse-
bias conditions) isID = IS(e VD / T – 1)
where VD is the voltage applied to the junction – a forward-bias lowers the
potential barrier allowingcarriers to flow across thediode junction
– a reverse-bias raises thepotential barrier and thediode becomes nonconducting
T = kT/q = 26mV at 300K
IS is the saturation current of the diode
+
-
VD
-0.5
0.5
1.5
2.5
-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1
VD (V)
Diode Animation
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 25/52
25
The MOS Transistor
Polysilicon Aluminum
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 26/52
26
The NMOS Transistor Cross Sectionn areas have been doped with donor ions(arsenic) of concentration ND - electrons
are the majority carriers
p areas have been doped with acceptor ions (boron) of concentration NA - holes
are the majority carriers
Gate oxide (SiO2)
n+
Source Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide(SiO2)n+
PolysiliconGate
L
W
MOSFET Operation
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 27/52
27
MOSFET Operation
http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/mosfet.html
Th MOS C it (R f )
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 28/52
http://www-g.eng.cam.ac.uk/mentor/IIA/VLSI/CMOS1/CMOS1.html
The MOS Capacitor (Reference)
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 29/52
MOS Transistors as Switches
29http://tams-www.informatik.uni-hamburg.de/applets/cmos/cmosdemo.html
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 30/52
30
Switch Model of NMOS Transistor
Gate
Source(of carriers)
Drain(of carriers)
| VGS |
| VGS | < | VT | | VGS | > | VT |
Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)
Ron
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 31/52
31
Switch Model of PMOS Transistor
Gate
Source(of carriers)
Drain(of carriers)
| VGS |
| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |
Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)
Ron
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 32/52
In reality
Gate
Source(of carriers)
Drain(of carriers)
| VGS |
| VGS | < | VT | | VGS | > | VT |
Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)
(Small) Ron(Large) Roff
Same for PMOS
Th h ld V lt C t
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 33/52
33
Threshold Voltage Concept
S D
p substrate
B
GVGS
+
-
n+n+
depletionregion
nchannel
The value of VGS where strong inversion occursis called the threshold voltage, VT
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 34/52
34
The Threshold VoltageVT = VT0 + (|-2F + VSB| - |-2F|)
Where
• VT0 is the threshold voltage at VSB = 0 and is mostly afunction of the manufacturing process
• VSB is the source-bulk voltage
• F = -Tln(NA /ni) is the Fermi potential (T = kT/q = 26mV at
300K is the thermal voltage; NA is the acceptor ion concentration; ni
1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon)
• = (2qsiNA)/Cox is the body-effect coefficient (impact
of changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon;Cox = ox /tox is the gate oxide capacitance with ox=3.5x10-11F/m)
Th B d Eff t
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 35/52
35
The Body Effect
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
-2.5 -2 -1.5 -1 -0.5 0
VBS (V)
VSB is the substrate bias
voltage (normally positive for n-channel devices with the bodytied to ground)
A negative bias causes VT toincrease from 0.45V to 0.85V
Can use this trick to help with
power consumption – reducesleakage currents (but slows downthe gate)
VSB always has to be larger
than –0.6V in an NMOS device;otherwise the source-body diodebecomes forward biased
Transistor in Linear Mode
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 36/52
36
Transistor in Linear Mode
S
D
B
G
n+n+
Assuming VGS > VT
VGS VDS
ID
x
V(x) - +
The current is a linear function of both VGS and VDS.
ID = F(VGS and VDS )
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 37/52
37
Voltage-Current Relation: Linear Mode
For long-channel devices (L > 0.25 micron)• When VDS VGS – VT
ID = k’n W/L [(VGS – VT)VDS – VDS2 /2]
where
k’n = nCox = nox /tox = is the process transconductance parameter (n is the carrier mobility(m2 /Vsec))
kn = k’n W/L is the gain factor of the device
For small VDS, there is a linear dependence between VDS and ID, hence the name resistive or linear region
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 38/52
38
Transistor in Saturation Mode
S
D
B
GVGS VDS > VGS - VT
ID
VGS - VT- + n+ n+
Pinch-
off
Assuming VGS > VT
VDS
The current remains constant (saturates).
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 39/52
39
Voltage-Current Relation: Saturation Mode
For long channel devices
• When VDS VGS – VT
ID’ = k’n /2 W/L [(VGS – VT) 2]
since the voltage difference over the induced
channel (from the pinch-off point to the source)remains fixed at VGS – VT
• Some caveats (see the textbook) so ID is not100% constant.
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 40/52
40
Current Determinates
• For a fixed VDS and VGS (> VT), IDS is a functionof
– the distance between the source and drain – L
– the channel width – W
– the threshold voltage – VT
– the thickness of the SiO2 – tox
– the dielectric of the gate insulator (SiO2) – ox
– the carrier mobility
• for nfets: n = 500 cm2 /V-sec• for pfets: p = 180 cm2 /V-sec
Long Channel I V Plot (NMOS)
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 41/52
41
Long Channel I-V Plot (NMOS)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Linear Saturation
VDS = VGS - VT
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
cut-off
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 42/52
42
Current-Voltage Relations
Long-Channel Device
Sh t Ch l Eff t
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 43/52
43
Short Channel Effects
0
10
0 1.5 3
(V/ m)
For an NMOS device with L of .25m, only a couple of voltsdifference between D and S are needed to reach velocity
saturation
c=
Behavior of short channel device mainly due to
Velocity saturation – thevelocity of the carrierssaturates due to scattering(collisions suffered by thecarriers)
5
Voltage Current Relation:
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 44/52
44
Voltage-Current Relation:Velocity Saturation
For short channel devices• Linear: When VDS VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2 /2]
where(V) = 1/(1 + (V/ cL)) is a measure of the degreeof velocity saturation
• Saturation: When VDS = VDSAT VGS – VT
IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2 /2]
Velocity Saturation Effects
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 45/52
45
Velocity Saturation Effects
VDSAT < VGS – VT sothe device enters
saturation before VDS reaches VGS – VT andoperates more often insaturation
For short channel devices
and large enough VGS – VT
IDSAT has a linear dependence wrt VGS so a reducedamount of current is delivered for a given control
voltage
0
10
S C OS
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 46/52
46
Short Channel I-V Plot (NMOS)
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V,
Early Velocity
Saturation
Linear Saturation
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 47/52
47
MOS ID-VGS Characteristics Linear (short-channel)
versus quadratic (long-channel) dependence ofID on VGS in saturation
Velocity-saturationcauses the short-channel device tosaturate at substantiallysmaller values of VDS
resulting in a substantialdrop in current drive
(for VDS = 2.5V, W/L = 1.5)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5VGS (V)
X 10-4
Short Channel I-V Plot (PMOS)
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 48/52
48
Short Channel I-V Plot (PMOS)
-1
-0.8
-0.6
-0.4
-0.2
0
0-1-2
VDS (V)
X 10-4
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
All polarities of all voltages and currents are reversed
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 49/52
49
The MOS Current-Source Model
VT0(V) (V0.5) VDSAT(V) k’(A/V2) (V-1)
NMOS 0.43 0.4 0.63 115 x 10-6 0.06
PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1
S D
G
B
ID
ID = 0 for VGS – VT 0
ID = k’ W/L [(VGS – VT)Vmin –Vmin2 /2](1+VDS)
for VGS – VT 0
with Vmin = min(VGS – VT, VDS, VDSAT)
and VGT = VGS - VT
Determined by the voltages at the four terminals and a set of fivedevice parameters
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 50/52
PSPICE
Simulating CircuitsPSPICE
The Transistor Modeled as a Switch
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 51/52
51
The Transistor Modeled as a Switch
0
1
2
3
4
5
6
7
0.5 1 1.5 2 2.5
VDD (V)
x105
S DRo
n
VGS VT
VDD(V) 1 1.5 2 2.5
NMOS(k) 35 19 15 13
PMOS (k) 115 55 38 31
(for VGS = VDD,VDS = VDD VDD /2)
Modeled as a switch with infiniteoff resistance and a finite on
resistance, Ron
Resistance inverselyproportional to W/L (doublingW halves Ron)
For VDD>>VT+VDSAT /2, Ron independent of VDD
Once VDD approaches VT,Ron increases dramatically
Ron (for W/L = 1)For larger devices divide
Req by W/L
Ci i Th CMOS I
8/3/2019 Lec3 MOS Transistor Review 2
http://slidepdf.com/reader/full/lec3-mos-transistor-review-2 52/52
Circuit: The CMOS Inverter
VDD
Vout
CL
Vin