2424

1 4 ,

13-

0 0 8’

00

0 e.” 12- I doping level

El n = 4.5 x E17 2 0

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35, NO. 12. DECEMBER 1988

11:

10: Breakdown

(volts)

.* wide recess 0 .

t standard recess

. . - 4 - 3 - 2 - 1 0

Pinchoff (volts)

.!% I standard recess 1

Z=0.16mm

4 0 , . . . . , . . . . , . . . . , . . . . 4 - 3 - 2 - 1 0

Pinchoff (volts) Fig. 4. dc electrical measurements from two wafers that clearly shows the

increase in breakdown voltage from the wide gate recess etch process.

than the single-layer process (note the distribution of points in Fig. 4). More data are required to confirm this.

The same spreading of the gate-drain voltage over a longer dis- tance that improves the breakdown voltage should have other ad- vantages as well. The smaller electric field should reduce the tend- ency for thermal “hot” spot creation near the gate edge and also reduce any electromigration of impurities near the gate. Both “hot” spots and electromigration could be a source of device failure.

Although this technique is most useful for FET’s typically used for X-band with dopings of the order of 2 X 10” cm-3 and gate lengths of 0.5 to 1.0 pm, the technique has been successfully used with millimeter-wave FET’s. With a doping level of 4.5 X 10” cm-3 and 0.25-pm gates, a 160-pm FET produced 91 mW (0.57 W/mm) at 32 GHz at a gain of 5 . 5 dB and 27.3-percent power added efficiency. At the same frequency, a 300-pm FET produced 171 mW with a gain of 3.8 dB and an efficiency of 23.4 percent.

The only disadvantage associated with the wide gate etch would be a slightly increased parasitic resistance, and it is a minor factor for power FET’s. The increase comes from the current flowing an extra distance through the channel instead of through the more highly conducive contact layer. Taking 600 Q/square as a typical channel resistance, increasing the recess width even by as much as 0.3 pm would only increase the parasitic resistance by less than 0.2 Q . mm. This would cause an effective decrease in g, by a factor of ( 1 + g , r ) or only a few percent.

REFERENCES

[ 11 S. H . Wemple et a [ . , “Long-term and instantaneous burnout in GaAs power FET mechanisms and solutions,” IEEE Trans. Electron De- vices, vol. ED-28, pp. 834-840, 1981.

[2] P. Saunier et a l . , “High-performance K-band GaAs power field-effect transistors prepared by molecular beam epitaxy,” Appl. Phys. Lett.,

[3] K. Katsukawa et al., “Failure analysis and reliability for X-band power GaAs FET,” NEC Res. Dev . , no. 71, pp. 82-87, Oct. 1983.

[4] M. P. Zaitlin, “Reverse breakdown in GaAs MESFET’s,” lEEE Trans. Electron Devices, vol. 33, pp. 1635-1639, 1986.

[5] H. M. Macksey et a l . , “Fabrication of n + ledge channel structure for GaAs FETs with a single lithography step,” Electron. Lett . , vol. 2 I , no. 21, Oct. 10, 1985.

[6] H. Fukui, “Optimization of low-noise GaAs MESFET’s,” IEEE Trans. Electron Devices, vol. Ed-27, pp. 1034-1037, June 1980.

[7] M. J. Hatzakis, “PMMA copolymers as high sensitivity electron re- sists,” Vue. Sei. Technol., Nov./Dec. 1979.

[8] E. D. Wolf er u l . , “Electron-beam fabrication of quarter-micron T- shaped-gate FETs using a new tri-layer resist system,’’ in IEDM Tech. Dig. , pp. 613-616, 1983.

[9] I. Haller et a l . , “Copolymers of methyl methacrylate and methacrylic acid and their metal salts as radiation sensitive resists,’’ J. Elecrro- chem. Soc., vol. 126, no. 1, Jan. 1979.

[ IO] N . S . Viswanathan et a l . , “Monte Carlo simulation of spatially dis- tributed beams in electron-beam lithography,” J . Vue. Sei. Technol., no. 6, Nov./Dec. 1975.

[ 111 Elvacite Acrylic Resins Properties and Uses, Product Info., E-61906. Rev. 3/84, DuPont Company.

[ 121 J. P. R. David et al., ‘Gate-drain avalanche breakdown in GaAs power MESFET’s,” IEEE Trans. Electron Devices, vol. ED-29, no. 10, Oct. 1982.

VOI. 42, pp. 966-968, 1983.

High-Temperature Latchup Characteristics in VLSI CMOS Circuits

F. S . SHOUCAIR

Abstract-A simple worst case analytical model of holding currents and an empirical model of trigger currents are reported and shown to agree with experimental measurements in the range of 2 5 2 2 5 ° C . Whereas standard bulk CMOS inverters and ring oscillators are in- variably found to latchup near 125”C, their counterparts built on epitaxial wafers remain latchup free up to at least 250°C. These results add to an ongoing systematic effort to model high-temperature effects in integrated MOS technologies and provide worst case latchup infor- mation in the commerical temperature range and beyond.

I. INTRODUCTION Although latchup in CMOS technologies is now a relatively well

understood degradation mechanism, it remains an important con- sideration in the design of down-scaled VLSI processes. The most common precautions that help inhibit latchup are usually imple- mented as minimum “layout design rules” and generally limit the extent of down-scaling for a given process. Other precautionary measures including the use of guard rings, deep-trench isolations, or epitaxial layers lower sheet resistance and raise holding currents required to sustain latchup, but increase process complexity and may limit down scaling.

For a given CMOS structure, the two key parameters that deter- mine susceptibility to latchup are the parasitic bipolar transistors’ current gains and their associated distributed base-emitter shunting resistances. The magnitudes of both of these parameters have been shown to decrease significantly with decreasing temperature [2], [3]. Consequently, it has been suggested, and verified [ l ] , [2], that

Manuscript received March 3, 1988; revised August 15, 1988. The author is with the Department of Electrical Engineering, Brown

University, Providence, RI 02912. IEEE Log Number 8824216.

0018-9383/88/1200-2424$01 .OO 0 1988 IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 12, DECEMBER 1988 2425

CMOS circuits are more resistant to latchup if operated below room temperature. Dooley and Jaeger [ I ] have reported a study of latchup holding and trigger currents in standard 4000 series CMOS chips in the range of 77-300 K and found increases in these cur- rents at liquid-nitrogen temperatures by factors of 3-5 with respect to their room-temperature values. Sangiorgi et al. [2] have exam- ined a "twin-tub" VLSI CMOS process in n-type epitaxial wafers in the range of 400-77 K. They reported that holding and trigger currents increased respectively from "a few milliamperes to 100 mA," and "from a few microamperes to several milliamperes." This suggests that CMOS structures should be more susceptible to latchup at elevated temperatures. The present results confirm this supposition. They are part of an ongoing investigation of the effects of elevated junction temperatures on MOS integrated circuits aimed at improving the design of precision high-temperature analog and digital CMOS VLSI circuits [4]-[6].

11. WORST CASE MODELING AND LEAKAGE CURRENTS The two-parasitic-bipolar transistor model shown in Fig. 1 pro-

vides a useful vehicle for the analysis of the holding current ( I , ) required to sustain latchup because it yields a simple, yet reason- ably accurate (= 10 percent), closed-form expression for this key parameter over the temperature range considered. (A comparably manageable and accurate expression is, unfortunately, not known for the trigger current.) By accounting for leakage currents, it is straightforward to obtain

where P,, and 0, are the n-p-n and p-n-p transistor current gains, IRw and I,, the currents flowing across the p-well and n-substrate resistances Rw and R,, respectively, and IWgen( T ) and I,,,,,,( T ) rep- resent the generation-recombination and diffusion leakage current components flowing acoss the n-substrate to p-well junction. Under worst case conditions where the "beta-product'' (&&) >> 1, (1) reduces to

For our CMOS process, the leakage currents IWgen(T) and T ) have previously been modeled and quantified in detail [4],

[ 5 ] . The measured n-substrate to p-well leakage currents between 25 and 300°C have been presented elsewhere [ 5 , Fig. 51. Whereas generation-recombination currents dominate between 25 and 150"C, diffusion currents prevail between 150 and 300°C. Typical measured leakage current densities are between 1.2 nA/pm2 (bot- tom) and 1.4 nA/pm2 (sidewall) at 250"C, and 1-2 fA/pm2 at room temperature. Furthermore, the following dependences are ob- served in the temperature range under consideration: d 1 V,, 1 / d T = -2 mV/"C, and Rw( T ) - R,( T ) - T", where T i s absolute temperature and m = 2.3 [7]. The relative variations of holding current IH can therefore be predicted by means of ( I ) and these data. The solid lines in Fig. 3(a) have been generated by this method; they were matched to the room-temperature value of 1, for a given structure.

111. EXPERIMENTAL RESULTS All our data pertain to a standard VLSI p-well CMOS rocess

with n-substrate and p-well doping concentrations of 2 X 10' cm-3 and 10" cm-', respectively. We have also examined identical cir- cuits and structures, built with the same process on a set of wafers with a 15-pm n-type epitaxial layer cm-3), on 5-Q.cm n-substrates implanted with phosphorus. Outdiffusion forms an n c region several micrometers thick, reaching nearly to the p-well.

1 1 I I I , I n-

--3 L d , d Z d

1. I-fT 1 m- OVDD

Fig. 1 . Cross section of the p-well CMOS inverter structure used for latchup characterization. The parasitic bipolar transistors are shown along with their distributed base-emitter shunting resistors R , and R,, which vary with dimensions d , and d,.

A ' DD

vis 'OUT

This reduces Rs, Ppnp, and the minority-camer collection volume, thereby inhibiting latchup. The data were collected on wafers orig- inating from three different batch runs for each of the bulk and epitaxial types. Our sample size was typically taken across ten waf- ers per fabrication batch, at five sites per wafer. The results dis- cussed in this section are therefore representative of approximately 150 similar structures.

An important and deliberate consideration in the design of our experimental structures was the following: By making the base widths of the parasitic bipolar devices large, transport (rather than injection-efficiency) limited behavior is obtained. In this mode of operation, the current gains (beta values) of these devices are known to increase with absolute temperature in polynomial fashion (typi- cally as T", where 1 5 rn I 2), whereas in narrow-base devices this temperature increase is exponential [ 11-[3]. We have accord- ingly chosen to concentrate primarily on varying the p-well ( R w ) and n-substrate ( R , ) resistances, by making the base widths d, and d2 variable layout parameters (see Fig. 1). This situation is the one most often encountered, in view of typical practice in CMOS de- sign rules (e.g., MOSIS standard processes). The good agreement of the resulting model with our data appears to validate this ap- proach.

The structure used is the inverter shown in cross section in Fig. 1. The parasitic vertical n-p-n and lateral p-n-p bipolar transistors are indicated on the same figure, along with their distributed shunt- ing base-emitter resistances (represented by lumped components) Rw and Rs for the p-well and n-substrate, respectively. The inverter was examined in various static input/output configurations while the drain terminals of the p- and n-channel MOSFET's were at V,, (swept) and 0 V, respectively. Under these conditions, the power supply current ( I,,) was monitored as a function of V,,, with tem- perature as a parameter. The family of curves shown in Fig. 2(a), (b) were typically observed with an HP4145A dc parameter ana- lyzer, whose maximum supply current was 100 mA.

The experimental data for the holding current shown in Fig. 3(a) are well modeled by (2) over the entire range of 25-225°C. The trigger current data shown in Fig. 3(b) indicate that this parameter decreases as T-", where T is absolute temperature and 3.3 5 m 5 4.1, thereby favorably correlating with the temperature depen- dences of f i n . , - T j ; 1 I y I 2, [3]; and Rw.s - T;, z = 2.3, [7]. In Fig. 2(b), the 200°C curve is offset upward along the cur- rent axis by an amount corresponding to the leakage currents ( = 20 PA). This allows a valuable independent estimate of these cur- rents for a particular structure because the two-dimensional nature of current flow renders exact analytical computations quite diffi- cult. Hence, the net 200°C trigger current (excluding leakage cur- rents) is not 70 pA as might appear to be the case at first glance, but is, in fact, only about 50 pA for the structure with d , = d2 = 25 pm, as shown in Fig. 3(b).

2426 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 12. DECEMBER 1988

d,=d,: 25pm 2 5 I

Power Supply Voltoge VDD.(Volt)

(a) Fig. 2. Typical current-voltage latchup characteristics with temperature

as parameter ford, = d2 = 25 pm: (a) Emphasizing holding current. (b) Emphasizing trigger current.

TEMPERATURE , I’C 1

(a)

- 4

3 300 - - 2 5 0

LL

s 200 LL W

p 150

100 LL k

50

TEMPERATURE .YC)

(b) Fig. 3. Temperature dependences extracted from Fig. 2. Solid lines rep-

resent: (a) Holding current theory (see (2)) matched to 25°C data points. (b) Empirically observed trigger current variations with T - ” , where T i s absolute temperature.

We have attempted to repeat the above measurements on the aforementioned epitaxial wafers, and found that latchup was not triggered, even at 300°C, for any of the above structures (all d , ,

d2 combinations and inputloutput static conditions), a re- markable result. Finally, we compared the functionality of ring os- cillators comprising 101 identical cascaded inverters with d , = d2 = 25 pm, on both types of wafers. Whereas the “epi” oscillators invariably remained functional at 250°C (and some up to 300°C), their bulk-type counterparts all latched up near 125°C.

IV. CONCLUSIONS

We have presented results of an investigation of latchup holding and trigger currents in a standard VLSI CMOS inverter structure in the range of 25-225°C. The data for holding currents are well modeled by a simple analytical expression taking account of tem- perature variations of 1) parasitic bipolar transistors’ current gain (beta) factors, 2) these transistors’ distributed base-emitter resis- tances, and 3) n-substrate to p-well leakage currents. Trigger cur- rents are found to vary as T - ” , where T is absolute temperature, and 3.3 I rn I 4.1. In static biasing conditions, bulk-CMOS in- verters are invariably found to latch up around 125”C, while their epitaxial counterparts are immune to this degradation mechanism up to at least 250°C.

ACKNOWLEDGMENT The author is grateful to Prof. W. R. Patterson of Brown Uni-

versity for valuable suggestions about the manuscript.

REFERENCES

[l] J. G. Dooley and R. C. Jaeger, “Temperature dependence of latchup in CMOS circuits,” IEEE Elecrron Device Lefr., vol. EDL-5, no. 2, pp. 41-43, Feb. 1984.

[2] E. Sangiorgi, R. L. Johnston, M. R. Pinto, P. F. Bechtold, and W. Fichtner, “Temperature dependence of latch-up phenomena in scaled CMOS structures.” IEEE Elecrron Device Lef t . . vol. EDL-7, no. 1 , pp. 28-31, Jan. 1986.

[3] D. B. Estreich, “The physics and modeling of latch-up and CMOS integrated circuits,” Ph.D. dissertation, Stanford Univ., Oct. 1980.

[4] F. S. Shoucair, “Design considerations in high temperature analog CMOS integrated circuits,” IEEE Trans. Componenrs, Hybrids, Man- ufacr. Technol., vol. CHMT-9, no. 3, pp. 242-251, Sept. 1986.

[5] F. S. Shoucair and J. M. Early, “High temperature diffusion leakage current dependent MOSFET small signal conductance,” IEEE Trans. Elecrron Devices, vol. ED-31, no. 12, pp. 1866-1872, Dec. 1984.

[6] F. S . Shoucair, W. Hwang, and P. Jain, “Electrical characteristics of LSI silicon MOSFETs at very high temperatures, Part 111: Modeling and circuit behavior, ” IEEE Trans. Components, Hybrids, Manufact. Technol., vol. CHMT-7, no. I , pp. 146-153, Mar. 1984.

[7] N. D. Arora, J. R. Hauser, and D. J. Roulston, “Electron and hole mobilities in silicon as a function of concentration and temperature,” IEEE Trans. Elecrron Devices, vol. ED-29, no. 2, pp. 292-295, Feb. 1982.