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W/L RATIO and IT’s Effect Dipankar Nath M.E Embedded 2011 batch BITS – Pilani , Hyderabad Campus

vlsi / cmos w/l ratio

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Page 1: vlsi / cmos w/l ratio

W/L RATIO and IT’s Effect

Dipankar NathM.E Embedded 2011 batch

BITS – Pilani , Hyderabad Campus

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MOS : EFFECT OF W AND L IN CURRENT, RESISTANCE

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MOS : EFFECT OF W AND L IN CAPACITANCE,VT

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Area reduced delay/freq? power ?

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Cmos inverter: Charging

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Cmos inverter : Discharging

A fast gate is built either by keeping the output capacitancesmall or by decreasing the on-resistance of the transistor

The latter is achieved by increasing the W/L ratio of the device

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Symmetrical propagation delay

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Cmos inverter : summary

F or an inverter the (W/L) of the NMOS is (W/L)n and that for the PMOS is (W/L)p for Fall time = Rise Time. For the worst case design of the NAND gate, you should set the W/L ratio of the NMOS transistors to 2*(W/L)n (i.e. twice that of the inverter) and that of the PMOS to (W/L)p (i.e. equal to that of the inverter)

1.

2.

3.

4.

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Transistor sizing CMOS NOR

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Optimized NAND Gates W/L ratio of PMos and NMos transistors

CMOS NAND Gates

A

B

A • B

A B

Adding transistors in series (without sizing) slows down the circuit

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Transistor sizing: an approach

– If MOSFET serially connected in a current path, the overall current path resistance will be

– All serially connected MOSFET can be replace with a single MOSFET as

If the MOSFET are connected in parallel combination then,

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W

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RsLR

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Fast Complex Gates: Design Technique 1• Transistor sizing

– as long as fan-out capacitance dominates

• Progressive sizing

InN CL

C3

C2

C1In1

In2

In3

M1

M2

M3

MN

Distributed RC line

M1 > M2 > M3 > … > MN

(the MOSFET closest to the output should be the smallest)

Can reduce delay by more than 20%; decreasing gains as technology shrinks

Resistance of M1(R1) N times in the delayEquation. The resistance of M2(R2) appears N-1 times etc.

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Pseudo-NMOS logic• Pseudo-NMOS: replace PMOS PUN

with single “always-on” PMOS device• Some problems as pseudo-NMOS

inverter:– VOL larger than 0– static power when PDN is on

• Advantages– Replace large PMOS stacks with single

device– Reduces overall gate size, input

capacitance– Especially useful for wide-NOR structures

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THANK YOU