# vlsi / cmos w/l ratio

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vlsi / cmos w/l ratio

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W/L RATIO and ITs EffectDipankar Nath Click to edit Master subtitle style M.E Embedded 2011 batch BITS Pilani , Hyderabad Campus

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MOS : EFFECT OF W AND L IN CURRENT, RESISTANCE

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MOS : EFFECT OF W AND L IN CAPACITANCE,VT

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Area reduced delay/freq? power ?

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Cmos inverter: Charging

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Cmos inverter : Discharging

A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance of the transistor The latter is 12/30/12 achieved by increasing the W/L ratio of the device

Symmetrical propagation delay

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Cmos inverter : summary1.

2. 3.

4.

F or an inverter the (W/L) of the NMOS is (W/L)n and that for the PMOS is (W/L)p for Fall time = Rise Time. For the worst case design of the NAND gate, you should set the W/L ratio of the NMOS transistors to 2*(W/L)n (i.e. twice that of the inverter) and t of the PMOS to (W/L)p (i.e. equal to that of the inverter)

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Transistor sizing CMOS NOR

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CMOS NAND GatesA B A B

A B

Adding transistors in series (without sizing) slows down the circuit

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Optimized NAND Gates W/L ratio of PMos and NMos transistors

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If MOSFET serially connected in a RsL RsL2 current path,Rthe 1overallRsL3 + .. = + + current path W1 W2 W3 resistance will be L L LR = Rs (1

Transistor sizing: an approach+2

W1

W2

+

3

W3

= ..)

All serially connected MOSFET can be

Fast Complex Gates: Design Technique 1 Transistor sizing

as long as fan-out capacitance dominatesDistributed RC line M1 > M2 > M3 > > MN

InN MN C Progressive sizing L In3M3

(the MOSFET closest to the output should be the In2 M2 smallest) Can reduce delay by In1 M1 more than 20%; decreasing gains as Resistance of M1(R1) N times in the delaytechnology shrinksC 3 C 2 C 1Equation. The resistance of M2(R2) appears N-1 12/30/12 times etc.

Pseudo-NMOS logic

Pseudo-NMOS: replace PMOS PUN with single always-on PMOS device Some problems as pseudo-NMOS inverter:

VOL larger than 0 static power when PDN is on Replace large PMOS stacks

Advantages12/30/12

THANK YOU

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