Vlsi l4 Static Cmos Inv

  • View
    215

  • Download
    0

Embed Size (px)

Text of Vlsi l4 Static Cmos Inv

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    1/26

    VLSI Design: L4 Static CMOS Inverter.1 Chau/Cichy UCSD ECE

    ECE 260AVLSI Digital Circuits & SystemsFall 2002

    Lecture 04: CMOS Inverter (static view)

    Paul M. Chau ( chau@ece.ucsd.edu )

    [Adapted from Rabaeys Digital Integrated Circuits , 2002, J. Rabaey et al.;MJIrwin PSU 2002]

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    2/26

    VLSI Design: L4 Static CMOS Inverter.2 Chau/Cichy UCSD ECE

    Review: Design Abstraction Levels

    SYSTEM

    GATE

    CIRCUIT

    VoutVin

    CIRCUIT

    VoutVin

    MODULE

    +

    DEVICE

    n+S D

    n+

    G

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    3/26

    VLSI Design: L4 Static CMOS Inverter.3 Chau/Cichy UCSD ECE

    Review: The MOS Transistor

    Gate oxide

    n+

    Source Drain

    p substrate

    Bulk (Body)

    p+ stopper

    Field-Oxide

    (SiO 2)n+

    PolysiliconGate

    L

    W

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    4/26

    VLSI Design: L4 Static CMOS Inverter.4 Chau/Cichy UCSD ECE

    CMOS Inverter:A First Look

    VDD

    VoutC L

    Vin

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    5/26

    VLSI Design: L4 Static CMOS Inverter.5 Chau/Cichy UCSD ECE

    CMOS Inverter:Steady State Response

    VDD

    R n

    Vout = 0

    Vin = V DD

    VDD

    R p

    Vout = 1

    Vin = 0

    V OL = 0 V OH = V DD

    V M = f(R n, R p )

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    6/26

    VLSI Design: L4 Static CMOS Inverter.6 Chau/Cichy UCSD ECE

    CMOS Propertiesq Full rail-to-rail swing high noise margins

    l

    Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless

    q Always a path to V dd or GND in steady state lowoutput impedance (output resistance in k range) large fan-out (albeit with degraded performance)

    q Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-stateinput current

    q No direct path steady-state between power and ground no static power dissipation

    q Propagation delay function of load capacitance andresistance of transistors

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    7/26VLSI Design: L4 Static CMOS Inverter.7 Chau/Cichy UCSD ECE

    Review: Short Channel I-V Plot (NMOS)

    0

    0.5

    1

    1.5

    2

    2.5

    0 0.5 1 1.5 2 2.5

    ID

    ( A )

    VDS (V)

    X 10 -4

    VGS = 1.0V

    VGS = 1.5V

    VGS = 2.0V

    VGS = 2.5V

    L i n e a r

    d e p e n d e n c e

    NMOS transistor, 0.25um, Ld = 0.25um , W/L = 1.5, V DD = 2.5V, V T = 0.4V

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    8/26VLSI Design: L4 Static CMOS Inverter.8 Chau/Cichy UCSD ECE

    Review: Short Channel I-V Plot (PMOS)

    -1

    -0.8

    -0.6

    -0.4

    -0.2

    00-1-2

    ID ( A )

    VDS (V)

    X 10 -4

    VGS = -1.0V

    VGS = -1.5V

    VGS = -2.0V

    VGS = -2.5V

    PMOS transistor, 0.25um, Ld = 0.25um , W/L = 1.5, V DD = 2.5V, V T = -0.4V

    l All polarities of all voltages and currents are reversed

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    9/26VLSI Design: L4 Static CMOS Inverter.9 Chau/Cichy UCSD ECE

    Transforming PMOS I-V Lines

    IDSp = -I DSnVGSn = V in ; VGSp = V in - VDDVDSn = Vout ; VDSp = Vout - VDD

    Vout

    IDn

    VGSp = -2.5

    VGSp = -1Mirror around x-axisVin = VDD + V GSpIDn = -IDp

    Vin = 1.5

    Vin = 0

    Vin = 1.5

    Vin = 0

    Horiz. shift over V DDVout = VDD + VDSp

    l Want common coordinate set V in, Vout , and I Dn

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    10/26VLSI Design: L4 Static CMOS Inverter.10 Chau/Cichy UCSD ECE

    CMOS Inverter Load Lines

    0

    0.5

    1

    1.5

    2

    2.5

    0 0.5 1 1.5 2 2.5

    ID n

    ( A )

    Vout (V)

    X 10 -4

    Vin = 1.0V

    Vin = 1.5V

    Vin = 2.0V

    Vin = 2.5V

    0.25um, W/L n = 1.5, W/Lp = 4.5 , VDD = 2.5V, V Tn = 0.4V, V Tp = -0.4V

    Vin = 0V

    Vin = 0.5V

    Vin = 1.0V

    Vin = 1.5V

    Vin = 0.5VVin = 2.0V

    Vin = 2.5V

    Vin = 2VVin = 1.5V

    Vin = 1VVin = 0.5V

    Vin = 0V

    PMOS NMOS

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    11/26VLSI Design: L4 Static CMOS Inverter.11 Chau/Cichy UCSD ECE

    CMOS Inverter VTC

    0

    0.5

    1

    1.5

    2

    2.5

    0 0.5 1 1.5 2 2.5

    Vin (V)

    V o u

    t ( V

    )

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    12/26VLSI Design: L4 Static CMOS Inverter.12 Chau/Cichy UCSD ECE

    CMOS Inverter VTC

    0

    0.5

    1

    1.5

    2

    2.5

    0 0.5 1 1.5 2 2.5

    Vin (V)

    V o u

    t ( V

    )

    NMOS off

    PMOS resNMOS satPMOS res

    NMOS satPMOS sat

    NMOS resPMOS sat NMOS res

    PMOS off

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    13/26VLSI Design: L4 Static CMOS Inverter.13 Chau/Cichy UCSD ECE

    CMOS Inverter:Switch Model of Dynamic Behavior

    VDD

    R n

    VoutC L

    Vin = V DD

    VDD

    R p

    VoutC L

    Vin = 0

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    14/26VLSI Design: L4 Static CMOS Inverter.14 Chau/Cichy UCSD ECE

    CMOS Inverter:Switch Model of Dynamic Behavior

    VDD

    R n

    VoutC L

    Vin = V DD

    VDD

    R p

    VoutC L

    Vin = 0

    l Gate response time is determined by the time to charge C Lthrough R p (discharge C L through R n)

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    15/26

    VLSI Design: L4 Static CMOS Inverter.15 Chau/Cichy UCSD ECE

    Relative Transistor Sizing

    q When designing static CMOS circuits,balance the driving strengths of thetransistors by making the PMOS section

    wider than the NMOS section tol maximize the noise margins andl obtain symmetrical characteristics

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    16/26

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    17/26

    VLSI Design: L4 Static CMOS Inverter.17 Chau/Cichy UCSD ECE

    Switch Threshold Exampleq In our generic 0.25 micron CMOS process, using the

    process parameters from slide L03.25, a VDD

    = 2.5V, anda minimum size NMOS device ((W/L) n of 1.5)

    -0.1-30 x 10 -6-1-0.4-0.4PMOS

    0.06115 x 10 -60.630.40.43 NMOS (V -1)k(A/V 2)VDSAT (V

    ) (V 0.5 )VT0(V)

    (W/L) p

    (W/L) n=

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    18/26

    VLSI Design: L4 Static CMOS Inverter.18 Chau/Cichy UCSD ECE

    Switch Threshold Exampleq In our generic 0.25 micron CMOS process, using the

    process parameters from slide L03.25, a VDD

    = 2.5V, anda minimum size NMOS device ((W/L) n of 1.5)

    -0.1-30 x 10 -6-1-0.4-0.4PMOS

    0.06115 x 10 -60.630.40.43 NMOS (V -1)k(A/V 2)VDSAT (V

    ) (V 0.5 )VT0(V)

    (W/L) p 115 x 10 -6 0.63 (1.25 0.43 0.63/2)

    (W/L) n -30 x 10 -6 -1.0 (1.25 0.4 1.0/2)= x x = 3.5

    (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    19/26

    VLSI Design: L4 Static CMOS Inverter.19 Chau/Cichy UCSD ECE

    Simulated Inverter V M

    0.8

    0.9

    1

    1.1

    1.2

    1.3

    1.4

    1.5

    0 1 10

    (W/L)p/(W/L)n

    VM

    ( V

    )

    q VM is relativelyinsensitive to variations indevice ratio

    l setting the ratio to 3, 2.5and 2 gives V Ms of 1.22V,1.18V, and 1.13V

    q Increasing the width of the PMOS moves V Mtowards V DD

    q Increasing the width of the NMOS moves V Mtoward GND

    .1

    Note: x-axis is semilog

    ~3.4

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    20/26

    VLSI Design: L4 Static CMOS Inverter.20 Chau/Cichy UCSD ECE

    Noise Margins Determining V IH and V IL

    0

    1

    2

    3

    VIL VIHVin

    Vo

    u t

    VOH = VDD

    VM

    By definition, V IH and V IL arewhere dV out /dV in = -1 (= gain)

    VOL = GND

    A piece-wise linear approximation of VTC

    NMH = VDD - VIHNM

    L= V

    IL- GND

    Approximating:VIH = V M - VM /gVIL = VM + (V DD - VM )/g

    So high gain in the transitionregion is very desirable

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    21/26

    VLSI Design: L4 Static CMOS Inverter.21 Chau/Cichy UCSD ECE

    CMOS Inverter VTC from Simulation

    0

    0.5

    1

    1.5

    2

    2.5

    0 0.5 1 1.5 2 2.5

    Vin (V)

    V o u

    t ( V )

    0.25um, (W/L) p/(W/L) n = 3.4

    (W/L) n = 1.5 (min size)VDD = 2.5V

    VM 1.25V, g = -27.5

    VIL = 1.2V, V IH = 1.3VNML = NM H = 1.2(actual values areVIL = 1.03V, V IH = 1.45V

    NML = 1.03V & NM H = 1.05V)

    Output resistancelow-output = 2.4k high-output = 3.3k

  • 7/28/2019 Vlsi l4 Static Cmos Inv

    22/26

    VLSI Design: L4 Static CMOS Inverter.22 Chau/Cichy UCSD ECE

    Gain Determinates

    -18

    -16

    -14

    -12

    -10

    -8

    -6

    -4

    -2

    0

    0 0.5 1 1.5 2

    Vin

    g a i n

    Gain is a strong function of theslopes of the currents in thesaturation region, for V in = VM

    (1+r)g ----------------------------------

    (VM-VTn-VDSATn /2)( n - p )

    Determined by technologyparameters, especially channellength modulati