Cmos Vlsi Ic Design

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    CMOS VLSI IC Design

    A decent understanding of all tasks required to designand fabricate a chip takes years of experience

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    Commonly used keywords

    INTEGRATED CIRC IT !IC"#any transistors on one chip

    $ER% &ARGE 'CA&E INTEGRATI(N !$&'I")ery #any transistors !* +,,,, gates" on one chip

    C(-.&E-ENTAR% -ETA& (/IDE'E-IC(ND CT(R !C-('" TEC0N(&(G%cheap1 high integration density1 lo2 po2er

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    Integrated Circuits

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    Packaging the Chip

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    Common Packages

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    Moore's LawIn +675 Gordon -oore predicted that as a resultof continuous #iniaturi8ation transistor count2ould double e)ery +3 #onths

    95: co#pound annual gro2th rate o)er ;9 years

    !No other technology has gro2n so fast so long"Transistors ha)ebeco#e< = s#aller

    = faster= consu#e lesspo2er

    = cheaper to#anufacture

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    Challenges

    The greatest challenge in #odern $&'I design is#anaging system complexity

    'trategies used to cope 2ith Co#plexity Abstraction 'tructured Design Approach Design >lo2

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    Design Abstractions

    1970 1980 1990 2000+

    A b s t r a c t i o n

    Transistor Level

    Gate Level

    RTL

    RegisterTransfer Level

    (HDL)

    RTL !

    "ste# Level

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    Examples of design abstractions (1)A

    $

    %0

    1

    Z = A S' + B S

    Logic Level

    Truth Table

    MSI Building Block

    Gate Level

    Switch Level

    Module Level

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    Examples of design abstractions (2)

    Structural Level V !L

    "egi#ter Tran#$er Level V !LM%S tran#i#tor# Level

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    Structured Design Hierarc&"

    !ivide and &on uer (aradig) 'o larit"

    ?ell=defined interfaces allo2 #odules to be treatedas black boxes Reg larit"

    It #akes easier to reuse blocks

    'tandard cell libraries are a )ery good exa#ple of#odularity and regularity

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    IC Design Hierarchy

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    Standard cells

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    Simplified IC Design Flows

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    Another Simplified IC Design FlowImplementation: Translation!#erge all design filesinto a single netlist"

    De)ice #apping .@R

    Device Programming: Generation conf file Do2nload conf file into de)ice

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    RTL code (Verilog)

    assign cout = (a&b) | (a&c) | (b&c);

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    Gate level netlist (Verilog)

    module carry( input a, b, c,output cout)

    wire x, y, z; and g1(x, a, b);and g2(y, a, c);and g3(z, b, c);or g4(cout, x, y, z);

    endmodule

    a

    bac

    bc

    cout

    *

    +

    ,

    g-

    g.

    g/

    g0

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    Transistor level netlist (Verilog)

    a b

    c

    c

    a b

    b

    a

    a

    b

    coutcn

    n- n.

    n/

    n0

    n1 n2

    (2(1

    (0

    (/

    (.(-

    i-

    i/

    i.

    i0

    module carry( input a, b, c, output cout)

    wire i1, i2, i3, i4, cn;

    tranif1 n1(i1, 0, a);tranif1 n2(i1, 0, b);tranif1 n3(cn, i1, c);tranif1 n4(i2, 0, b);tranif1 n5(cn, i2, a);tranif0 p1(i3, 1, a);tranif0 p2(i3, 1, b);tranif0 p3(cn, i3, c);tranif0 p4(i4, 1, b);tranif0 p5(cn, i4, a);

    tranif1 n6(cout, 0, cn);tranif0 p6(cout, 1, cn);

    endmodule

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    SPICE netlist. SUBC ! CARRY A C C!"# $%% &'%

    '1 1 A &'% &'% ' !* + 1" - 0.1 " A% 0.3/ A* 0.5/'2 1 &'% &'% ' !* + 1" - 0.1 " A% 0.3/ A* 0.5/'3 C' C 1 &'% ' !* + 1" - 0.1 " A% 0.5/ A* 0.5/'4 2 &'% &'% ' !* + 1" - 0.1 " A% 0.15/ A* 0.5/'5 C' A 2 &'% ' !* + 1" - 0.1 " A% 0.5/ A* 0.15//1 3 A $%% $%% / !* + 2" - 0.1 " A% 0.6/ A* 1 //2 3 $%% $%% / !* + 2" - 0.1 " A% 0.6/ A* 1/

    /3 C' C 3 $%% / !* + 2" - 0.1 " A% 1/ A* 1//4 4 $%% $%% / !* + 2" - 0.1 " A% 0.3/ A* 1//5 C' A 4 $%% / !* + 2" - 0.1 " A% 1/ A* 0.3/'6 C!"# C' &'% &'% ' !* + 2" - 0.1 " A% 1/ A* 1//6 C!"# C' $%% $%% / !* + 4" - 0.1 " A% 2/ A* 2/

    C 1 1 &'% 2C 3 3 &'% 3CA A &'% 4C &'% 4CC C &'% 2CC' C' &'% 4CC!"# C!"# &'% 2. "#$S

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    Types of ICs

    ASS3 ASI& 4ull5cu#to)

    Se)i5cu#to)&ell Ba#ed

    Gate Arra #3rogra))able

    &3L! and43GA

    se

    Design 'tyle

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    Standard Cells

    Rows of standardcells with

    routing channelsbetween them

    Memory array

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    Field Programmable Gate Array

    C!"#

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    Internal Structure of a CLB

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    Various on chip structures

    Rando# logic Data paths Arrays Analog

    InputBoutput !IB("

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    Example of random Logic

    'ynthesi8ed -I.' controller

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    Another example of random logic

    'ynthesi8ed -I.'

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    Example of data path

    0and=Crafted -I.' datapath

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    Example of Array

    S"AM chi(

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    Example of Analog structure

    &harge 3u)( 3ha#e5Locked Loo(

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    Bidirectional I/O PAD circuit

    1

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    Physical Design

    >loorplanning and area esti#ation 'tandard Cell ased &ayout

    .lace and Route

    .arasitic Extraction .ost &ayout $erification

    Data=path ased &ayout

    'lice .lanning .arasitic Extraction .ost &ayout $erification

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    Floorplanning Does the design fit the chip

    area budgeted Esti#ates area of #a or units

    and defines their relati)eplace#ent

    Esti#ate 2ire lengths Esti#ate 2iring congestion

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    Area Estimation 'o#e cell library )endor specify cell layout densities in FgatesB##4

    Co#pare to another block you already designed or esti#ate fro#transistor counts

    udget roo# for large 2iring tracks

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    Example of Layout

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    CAD ToolsDesigners rely increasingly on design auto#ation soft2are tools toseek producti)ity gains and to cope 2ith increased co#plexity

    6 Design *ntr"6 c&e#atic ca t re

    6 Har ,are Descri tion Lang ages6 Logic "nt&esis6 -re la"o t verification

    6 . nctional si# lation6 .or#al #et&o s6 Ti#ing Anal"sis

    6 .loor lanning6 -lace#ent6 Ro ting6 */traction6 -ost la"o t verification

    !ogicDesign

    PhysicalDesign

    $ypical Design %low

    Verification

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    Verification >abrication is slo2 @ expensi)e

    -('I' , 7 # #asks< +,,,1 5 #onths 'tate of art #asks !+5,n#"< +-1 + #onth Debugging chips is )ery hard &i#ited )isibility into operation .ro)e design is right before buildingH 'yste# si#ulation @ perfor#ance Assess#ent !CBC " &ogic 'i#ulation B for#al )erification B 'TA Circuit si#ulation &ayout )s sche#atic co#parison !&$'" Design @ electrical rule checks !DRC1 ERC"

    $erification is * 9,: of effort on #ost chips H

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    Fabrication

    Tapeout final layout >or#ats for #ask descriptions !acade#ia" and GD' II !industry" >abrication

    71 31 +4J 2afers !bare 2afer costs +,,,= 9,,," (pti#i8ed for throughput1 not latency

    !turnaround ti#es up to +, 2eeks H"

    Cut into indi)idual dice >abs cost billions of dollars and beco#e obsolete in a fe2 years

    >abless se#iconductor co#panies -anufacturing Co#panies< T'-'1 -C1 I -

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    Testing

    Test that chip operates as expected Design errors -anufacturing errors

    A single dust particle or 2afer defect kills a die %ields fro# 6,: to K +,: Depends on die si8e1 #