2.CMOS Transistor Theory - .CMOS VLSI Design 2.CMOS Transistor Theory Fu yuzhuo School of microelectronics,SJTU

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  • Digital IC 2: DeviceIntroduction

    CMOS VLSI Design

    2.CMOS Transistor Theory

    Fu yuzhuo

    School of microelectronics,SJTU

  • Digital IC 2: Device

    outline

    PN junction principle

    CMOS transistor introduction

    Ideal I-V characteristics under static conditions

    Velocity Saturation

    Dynamic Characteristics

    Nonideal I-V effects

    2/41

  • Digital IC 2: Device

    Capacitance

    Any two conductors separated by an insulator

    have capacitance

    Gate to channel capacitor is very important

    Creates channel charge necessary for

    operation

    Source and drain have capacitance to body

    Across reverse-biased diodes

    Called diffusion capacitance because it is

    associated with source/drain diffusion

    3/41

  • Digital IC 2: Device

    Diffusion Capacitance

    Csb, Cdb

    Undesirable, called parasitic capacitance

    Capacitance depends on area and perimeter

    Use small diffusion nodes

    Comparable to Cg

    for contacted diff

    Cg for uncontacted

    Varies with process

    4/41

  • Digital IC 2: Device

    Capacitance components

    MOS structure capacitances

    Overlap cap.

    Channel capacitances

    Gate-body cap.

    Gate-source cap.

    Gate-drain cap.

    Junction/diffusion capacitances

    Bottom-plate cap.

    Side-well cap.

    DS

    G

    B

    CGDCGS

    CSB CDBCGB

    5/41

  • Digital IC 2: Device

    The Gate Capacitance

    WCWxCCC odoxGDOGSO

    tox

    n+ n+

    Cross section

    L

    Gate oxide

    xd xd

    L d

    Polysilicon gate

    Top view

    Gate-bulkoverlap

    Source

    n+

    Drain

    n+W

    6/41

  • Digital IC 2: Device7/41

    Gate channel Capacitance

    S D

    G

    CGC

    S D

    G

    CGC

    S D

    G

    CGC

    Cut-off Resistive Saturation

    Most important regions in digital design: saturation and cut-off

  • Digital IC 2: Device8/41

    Gate Capacitance

    WLCox

    WLCox

    2

    2WLCox

    3

    CGC

    CGCS

    VDS /(VGS-VT)

    CGCD

    0 1

    CGC

    CGCS = CGCDCGC B

    WLCox

    WLCox

    2

    VGS

    Capacitance as a function of VGS(with VDS = 0)

    Capacitance as a function of

    the degree of saturation

  • Digital IC 2: Device

    Measuring the Gate Cap

    2 1.52 1 2 0.5 0

    3

    4

    5

    6

    7

    8

    9

    103 102 16

    2

    VGS (V)

    VGS

    Ga

    te C

    ap

    acita

    nce

    (F

    )

    0.5 1 1.5 22 2

    I

    dt

    dVIVC

    dt

    dVVCI

    GSGSG

    GSGSG

    )(

    )(

    9

  • Digital IC 2: Device

    Diffusion Area Capacitance

    Bottom

    Side wall

    Side wall

    Channel

    SourceND

    Channel-stop implantNA1

    Substrate NA

    W

    xj

    DS

    )2( WLCC

    PERIMETERCAREACCCC

    SjswjLSW

    jswjswbottomdiff

    10/41

  • Digital IC 2: Device

    An example of Diffusion

    Capacitance

    Cgc=WLCox=0.24*0.36*5.7=0.49fF

    Coverlap=2*Co*W=2*0.3*0.36=0.216fF

    Cdiff-s=WDs*Cj+(W+2Ds)Cjsw=

    0.36*0.625*2+(0.36+0.625*2)*0.275=0.44fF

    NMOS:tox=6nm,L=0.24um,W=0.36um,LD=LS=0.625um, COX=5.7X10-3F/m2,

    CO=3X10-10F/m,Cj0=2X10

    -3F/m2, and Cjsw0=2.75X10-10F/m, determine the

    zero-bias value of relevant capacitances

    11/41

    1F=1015fF

  • Digital IC 2: Device

    Detail Diffusion Capacitance

    jM-

    0

    sb

    0jjs )

    V+(1C=C )

    n

    NNln(0.026=)

    n

    NNln(

    q

    kT= 2

    i

    AD

    2

    i

    AD

    0

    j swM-

    0

    sb

    0jswjsw )

    V+(1C=C

    Cdiff-s=WDs*Cjs+(W+2Ds)Cjsw

    12/41

  • Digital IC 2: Device

    Junction capacitance comes from

    DDA

    DAsiDj V

    NN

    NNqAQ

    02

    DA

    DAsiDj

    NN

    NNqAC

    020

    DDA

    DAsij V

    NN

    NN

    qWWW

    012

    2

    DDA

    DA

    si

    j VNN

    NNqE

    0

    2

    Depletion-region charge

    Maximum electric field

    Depletion-region width

    Zero-bias conditons

    5.000

    1

    011

    2

    00

    D

    j

    D

    j

    D

    DA

    DAsiD

    D

    j

    jV

    C

    V

    CV

    NN

    NNqA

    dV

    dQC

    13/41

  • Digital IC 2: Device

    AD=20unit2=20*0.081=0.162um2

    PD=10+4=14unit=14*0.09=1.26um

    Cdb(0)=0.162*0.98+1.26*0.22=

    Cdb(1.8)=0.162*0.98*(1+1.8/0.75)-0.36

    +1.26*0.22*(1+1.8/0.75)-0.10

    Another example

    Calculate the diffusion parasitic Cdb of the drain of a unit-sized

    contacted nMOS transistor in a 0.18um process when the drain is at 0

    and at Vdd=1.8V, assume the substrate is grounded, the transistor

    characteristic are Cj=0.98fF/um2,Mj=0.36, CJSW=0.22fF/um,MJSW=0.10,

    and 0=0.75V at room temperature

    14/41

  • Digital IC 2: Device

    More detail Capacity

    0

    )()(jeq

    lowhigh

    lowjhighj

    D

    j

    eq CKVV

    VQVQ

    V

    QC

    DDA

    DAsiDj V

    NN

    NNqAQ

    02

    DA

    DAsiDj

    NN

    NNqAC

    020

    mlowmhighlowhigh

    m

    eq VVmVV

    K

    10

    1

    00 )()(

    )1)((

    Cdiff-s=KeqWDs*Cjs+Keqsw(W+2Ds)Cjsw15/41

  • Digital IC 2: Device

    Capacitance model

    DS

    G

    B

    CGDCGS

    CSB CDBCGB

    DdiffDB

    SdiffSB

    GCBGB

    GCDGDOGD

    GCSGSOGS

    CC

    CC

    CC

    CCC

    CCC

    16/41

  • Digital IC 2: Device17/41

    The Transistor as a Switch

    VGS VT

    RonS D

    ID

    VDS

    VGS = VDD

    VDD/2 VDD

    R0

    Rmid

  • Digital IC 2: Device18/41

    The Transistor as a Switch

    0.5 1 1.5 2 2.50

    1

    2

    3

    4

    5

    6

    7x 10

    5

    VDD

    (V)

    Req (

    Ohm

    )

    The resistance is inversely proportional to

    the W/L ratio of the device

    For Vdd>>Vt+Vdsat/2, the resistance

    becomes independent of the supply voltage

    Once the supply voltage approaches Vt,

    the resistance dramatically increases

  • Digital IC 2: Device19/41

    The Transistor as a Switch

  • Digital IC 2: Device

    W

    LD

    Drain

    Draincontact

    Polysilicon gate

    DS

    G

    RS RD

    VGS,eff

    Source-Drain Resistance

    Co

    DS

    DS RRW

    LR ,,

    Low-resisitivity material

    Careful layout

    20/41

  • Digital IC 2: Device

    outline

    PN junction principle

    CMOS transistor introduction

    Ideal I-V characteristics under static conditions

    Velocity Saturation

    Dynamic Characteristics

    Nonideal I-V effects

    21/41

  • Digital IC 2: Device

    Nonideal characteristics

    Velocity saturation

    Channel length modulation

    Body effect

    Threshold Variations

    Parasitic Resistances

    Subthreshold Conduction

    Hot-carrier effects

    Latchup

    Process variations

    22/41

  • Digital IC 2: Device

    Channel length modulation

    Increasing VDS decreases the effective channel length

    is an empirical channel length, should not be confuse

    with the symbol used in layout design rules

    Channel length modulation is very important to analog

    designers because it reduces the gain of amplifiers, it is

    generally unimportant for qualitatively understanding the

    behavior of digital circuit

    )1(' DSDD VII

    23/41

  • Digital IC 2: Device

    Nonideal characteristics

    Velocity saturation

    Channel length modulation

    Body effect

    Threshold Variations

    Parasitic Resistances

    Subthreshold Conduction

    Hot-carrier effects

    Latchup

    Process variations

    24/41

  • Digital IC 2: Device

    Body effect

    )2-+V+2-(+V=V FSBF0tt

    )n

    Nln(60.02=)

    n

    Nln(

    q

    kT=

    i

    D

    i

    A

    F

    ox

    A

    A

    ox

    ox

    C

    q2=q2

    t=

    NN

    25/41

  • Digital IC 2: Device

    An example of Body effect

    )2-V+2-(+V=V FSBF0tt

    )n

    Nln(60.02=)

    n

    Nln(

    q

    kT=

    i

    D

    i

    A

    F ox

    A

    A

    ox

    ox

    C

    q2=q2

    t=

    NN

    If nominal threshold voltage of 0.4V and doping level of 8*1017cm-3, the

    body is tied to ground with a substrate contact. how much does the

    threshold change at room temperature if the source is at 1.1V instead of

    0,note,ni= 1.45*1010cm-3

    V46.0=F

    6.0=10*6

    10*8*10*8.85*(11.7*)10*6.1(*2

    10*8.85*3.9

    10*40= 6

    1741-19-

    14-

    -8

    68.0=)93.0-1.1+93.0(*6.0+4.0=Vt26/41

  • Digital IC 2: Device

    Nonideal characteristics

    Velocity saturation

    Channel length modulation

    Body effect

    Threshold Variations

    Parasitic Resistances

    Subthreshold Conduction

    Hot-carrier effects

    Latchup

    Process variations

    27/41

  • Digital IC 2: Device

    Threshold Variations

    VT

    L

    Long-channel threshold Low VDS threshold

    Threshold as a function of the length (for lo