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Digital IC 2: DeviceIntroduction
CMOS VLSI Design
2.CMOS Transistor Theory
Fu yuzhuo
School of microelectronics,SJTU
Digital IC 2: Device
outline
• PN junction principle
• CMOS transistor introduction
• Ideal I-V characteristics under static conditions
• Velocity Saturation
• Dynamic Characteristics
• Nonideal I-V effects
2/41
Digital IC 2: Device
Capacitance
• Any two conductors separated by an insulator
have capacitance
• Gate to channel capacitor is very important
• Creates channel charge necessary for
operation
• Source and drain have capacitance to body
• Across reverse-biased diodes
• Called diffusion capacitance because it is
associated with source/drain diffusion
3/41
Digital IC 2: Device
Diffusion Capacitance
• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
• Use small diffusion nodes
• Comparable to Cg
for contacted diff
• ½ Cg for uncontacted
• Varies with process
4/41
Digital IC 2: Device
Capacitance components
• MOS structure capacitances
• Overlap cap.
• Channel capacitances
• Gate-body cap.
• Gate-source cap.
• Gate-drain cap.
• Junction/diffusion capacitances
• Bottom-plate cap.
• Side-well cap.
DS
G
B
CGDCGS
CSB CDBCGB
5/41
Digital IC 2: Device
The Gate Capacitance
WCWxCCC odoxGDOGSO
tox
n+ n+
Cross section
L
Gate oxide
xd xd
L d
Polysilicon gate
Top view
Gate-bulkoverlap
Source
n+
Drain
n+
W
6/41
Digital IC 2: Device7/41
Gate channel Capacitance
S D
G
CGC
S D
G
CGC
S D
G
CGC
Cut-off Resistive Saturation
Most important regions in digital design: saturation and cut-off
Digital IC 2: Device8/41
Gate Capacitance
WLCox
WLCox
2
2WLCox
3
CGC
CGCS
VDS /(VGS-VT)
CGCD
0 1
CGC
CGCS = CGCDCGC B
WLCox
WLCox
2
VGS
Capacitance as a function of VGS
(with VDS = 0)Capacitance as a function of
the degree of saturation
Digital IC 2: Device
Measuring the Gate Cap
2 1.52 1 2 0.5 0
3
4
5
6
7
8
9
103 102 16
2
VGS (V)
VGS
Ga
te C
ap
acita
nce
(F
)
0.5 1 1.5 22 2
I
dt
dVIVC
dt
dVVCI
GSGSG
GSGSG
)(
)(
9
Digital IC 2: Device
Diffusion Area Capacitance
Bottom
Side wall
Side wall
Channel
SourceND
Channel-stop implantNA1
Substrate NA
W
xj
DS
)2( WLCC
PERIMETERCAREACCCC
SjswjLSW
jswjswbottomdiff
10/41
Digital IC 2: Device
An example of Diffusion
Capacitance
• Cgc=WLCox=0.24*0.36*5.7=0.49fF
• Coverlap=2*Co*W=2*0.3*0.36=0.216fF
• Cdiff-s=WDs*Cj+(W+2Ds)Cjsw=
0.36*0.625*2+(0.36+0.625*2)*0.275=0.44fF
NMOS:tox=6nm,L=0.24um,W=0.36um,LD=LS=0.625um, COX=5.7X10-3F/m2,
CO=3X10-10F/m,Cj0=2X10-3F/m2, and Cjsw0=2.75X10-10F/m, determine the
zero-bias value of relevant capacitances
11/41
1F=1015fF
Digital IC 2: Device
Detail Diffusion Capacitance
jM-
0
sb
0jjs )ψ
V+(1C=C )
n
NNln(0.026=)
n
NNln(
q
kT=ψ 2
i
AD
2
i
AD
0
j swM-
0
sb
0jswjsw )ψ
V+(1C=C
Cdiff-s=WDs*Cjs+(W+2Ds)Cjsw
12/41
Digital IC 2: Device
Junction capacitance comes from…
D
DA
DAsiDj V
NN
NNqAQ
0Φ2
DA
DAsiDj
NN
NNqAC
0Φ20
D
DA
DAsij V
NN
NN
qWWW
012 Φ
2
D
DA
DA
si
j VNN
NNqE
0Φ
2
Depletion-region charge
Maximum electric field
Depletion-region width
Zero-bias conditons
5.0
00
1
0Φ1Φ1
Φ2
00
D
j
D
j
D
DA
DAsiD
D
j
jV
C
V
CV
NN
NNqA
dV
dQC
13/41
Digital IC 2: Device
• AD=20unit2=20*0.081=0.162um2
• PD=10+4=14unit=14*0.09=1.26um
• Cdb(0)=0.162*0.98+1.26*0.22=
• Cdb(1.8)=0.162*0.98*(1+1.8/0.75)-0.36
+1.26*0.22*(1+1.8/0.75)-0.10
Another example
Calculate the diffusion parasitic Cdb of the drain of a unit-sized
contacted nMOS transistor in a 0.18um process when the drain is at 0
and at Vdd=1.8V, assume the substrate is grounded, the transistor
characteristic are Cj=0.98fF/um2,Mj=0.36, CJSW=0.22fF/um,MJSW=0.10,
and Ψ0=0.75V at room temperature
14/41
Digital IC 2: Device
More detail Capacity
0
)()(jeq
lowhigh
lowjhighj
D
j
eq CKVV
VQVQ
V
QC
D
DA
DAsiDj V
NN
NNqAQ
0Φ2
DA
DAsiDj
NN
NNqAC
0Φ20
m
low
m
high
lowhigh
m
eq VVmVV
K
1
0
1
00 )()(
)1)((
Cdiff-s=KeqWDs*Cjs+Keqsw(W+2Ds)Cjsw
15/41
Digital IC 2: Device
Capacitance model
DS
G
B
CGDCGS
CSB CDBCGB
DdiffDB
SdiffSB
GCBGB
GCDGDOGD
GCSGSOGS
CC
CC
CC
CCC
CCC
16/41
Digital IC 2: Device17/41
The Transistor as a Switch
VGS VT
Ron
S D
ID
VDS
VGS = VDD
VDD/2 VDD
R0
Rmid
Digital IC 2: Device18/41
The Transistor as a Switch
0.5 1 1.5 2 2.50
1
2
3
4
5
6
7x 10
5
VDD
(V)
Req (
Ohm
)
The resistance is inversely proportional to
the W/L ratio of the device
For Vdd>>Vt+Vdsat/2, the resistance
becomes independent of the supply voltage
Once the supply voltage approaches Vt,
the resistance dramatically increases
Digital IC 2: Device19/41
The Transistor as a Switch
Digital IC 2: Device
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
Source-Drain Resistance
Co
DS
DS RRW
LR
,
,•Low-resisitivity material
•Careful layout
20/41
Digital IC 2: Device
outline
• PN junction principle
• CMOS transistor introduction
• Ideal I-V characteristics under static conditions
• Velocity Saturation
• Dynamic Characteristics
• Nonideal I-V effects
21/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Hot-carrier effects
• Latchup
• Process variations
22/41
Digital IC 2: Device
Channel length modulation
• Increasing VDS decreases the effective channel length
• Λ is an empirical channel length, should not be confuse
with the symbol used in layout design rules
• Channel length modulation is very important to analog
designers because it reduces the gain of amplifiers, it is
generally unimportant for qualitatively understanding the
behavior of digital circuit
)1('
DSDD VII
23/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Hot-carrier effects
• Latchup
• Process variations
24/41
Digital IC 2: Device
Body effect
)Φ2-+V+Φ2-γ(+V=V FSBF0tt
)n
Nln(60.02=)
n
Nln(
q
kT±=Φ
i
D
i
A
F ±
ox
A
A
ox
ox
C
qε2=qε2
ε
t=γ
NN
25/41
Digital IC 2: Device
An example of Body effect
)Φ2-V+Φ2-γ(+V=V FSBF0tt
)n
Nln(60.02=)
n
Nln(
q
kT±=Φ
i
D
i
A
F ±ox
A
A
ox
ox
C
qε2=qε2
ε
t=γ
NN
If nominal threshold voltage of 0.4V and doping level of 8*1017cm-3, the
body is tied to ground with a substrate contact. how much does the
threshold change at room temperature if the source is at 1.1V instead of
0,note,ni= 1.45*1010cm-3
V46.0=ΦF
6.0=10*6
10*8*10*8.85*(11.7*)10*6.1(*2
10*8.85*3.9
10*40=γ 6±
1741-19-
14-
-8
68.0=)93.0-1.1+93.0(*6.0+4.0=Vt
26/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Hot-carrier effects
• Latchup
• Process variations
27/41
Digital IC 2: Device
Threshold Variations
VT
L
Long-channel threshold Low VDS threshold
Threshold as a function of the length (for low VDS)
Drain-induced barrier lowering (for low L)
drain-induced barrier lowering-DIBL
VT
28/41
Digital IC 2: Device
Hot-carrier effects
• Device dimensions have been scaled
down continuously, while power
supply and the operating voltages
have not scaled accordingly
• Electron become hot which lead to a
long-term reliability problem
29/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Hot-carrier effects
• Latchup
• Process variations
30/41
Digital IC 2: Device
Sub-Threshold Conduction
0.0 1.0 2.0 3.0VGS (V)
1012
1010
108
106
104
102
ln(I
D)
(A)
Subthreshold exponential region
Linear region
VT
31/41
Digital IC 2: Device
Sub-Threshold Conduction
0 0.5 1 1.5 2 2.510
-12
10-10
10-8
10-6
10-4
10-2
VGS(V)
I D(A
)
VT
Linear
Exponential
Quadratic
Typical values for S:60 .. 100 mV/decade
The Slope Factor
ox
DnkT
qV
DC
CneII
GS
1 ,~ 0
S is DVGS for ID2/ID1 =10
32/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Junction Leakage
• Latchup
• Process variations
33/41
Digital IC 2: Device
Junction leakage
• Is depends on doping levels and on the area and
perimeter of the diffusion region
• Vd is the diode voltage(Vsb and Vdb)
• Generally in the 0.1-0.01fA/um2
• With low threshold voltages, subthreshold
conduction far exceeds junction leakage
1)-(eI=I T
d
v
V
sd
34/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Junction Leakage
• Latchup
• Process variations
35/41
Digital IC 2: Device
Latchup
External voltages can ring below GND or above VDD
36/41
Digital IC 2: Device
Tunneling
• There is a finite probability that carriers will tunnel
through the gate oxide
• Gate leakage current flowing into the gate
• The probability of tunneling drops off exponentially with
oxide thickness
37/41
Digital IC 2: Device
Temperature dependence• Carrier mobility decreases with temperature
• Magnitude of the threshold voltage decrease withtemperature
• Junction leakage increases with temperature
38/41
Digital IC 2: Device
Nonideal characteristics
• Velocity saturation
• Channel length modulation
• Body effect
• Threshold Variations
• Parasitic Resistances
• Subthreshold Conduction
• Junction Leakage
• Latchup
• Process variations
39/41
Digital IC 2: Device
Process variations
• Variations in the process parameters
• Impurity concentration densities,Oxide
thicknesses,Diffusion depths
• Sheet resistances, threshold voltage
diverging.
• Variations in the dimensions of the
devices
• Deviations in the W/L ratios
• Tradeoff between economic and yield
40/41
Digital IC 2: Device
Some questions
• Vt trend
• Low Vt? High Vt?
• Low for high speed, high for low leakage
• VDD
• High voltage result in fast transistor?
• velocity saturation limit
• Delay
• Two nMOS in series deliver half the current of a
single nMOS of the same width?
• Velocity saturation benefit
41/41
Digital IC 2: Device
Summary of general MOSFET scaling trends
42/41
Digital IC 2: Device
Is there life after CMOS?
43/41
Digital IC 2: Device
outlook
• Copper has replaced aluminum as interconnect material
• Low-permittivity interlevel dielectrics are replacing
silicon dioxide
• High-permittivity gate dielectrics to replace silicon
dioxide
• Strained silicon and SiGe technology
• Metal gates bound to come back
• Silicon-on-insulator (SOI) technology
• The search for new device topologies
44/41
Digital IC 2: Device
Copper has replaced aluminum
as interconnect material
45/41
The search for a lower-resistivity conductor and a lower-
permittivity interlevel dielectric has prompted industry to
replace Al and SiO2 with new materials
Digital IC 2: Device
Copper has replaced aluminum
as interconnect material
46/41
measurements indicated that the effective resistance of Cu interconnect
was 30% to 45% lower than that of traditional Al alloys. Cu also supports
significantly higher current densities. In electromigration tests conducted by
IBM, reliability was found to improve by more than two orders of magnitude.
Digital IC 2: Device
Low-permittivity interlevel dielectrics are
replacing silicon dioxide
47/41
Intel’s 65 nm process combined up to eight levels of copper interconnect
with a low-permittivity carbon-doped oxide (CDO) ILD (r = 2.9). Tungsten
plugs are used for contacts to poly and diffusion. Metal pitches increase
gradually from bottom to top for optimum density vs. performance.
Digital IC 2: Device
High-permittivity gate dielectrics
to replace silicon dioxide• Intel reports that 45 nm MOSFETs with a Hafnium-
based oxide provide either a 25% increase in driveability
at the same subthreshold conduction or more than
fivefold reduction in leakage for the same drive current
when compared to 65 nm transistors with their
traditional gate stacks . At the same time, gate oxide
tunneling has been reduced by more than a factor of ten
48/41
A material of low permittivity is desirable for interlevel dielectrics where the lowest
possible parasitic capacitances are being sought. Exactly the opposite is true for the
gate dielectric in order to minimize gate leakage while maximizing MOSFET drivability
and, hence, the switching speed of logic circuits.
Digital IC 2: Device
Strained silicon and SiGe
technology
49/41
Electron mobility in Si augments when the crystal lattice is subjected to tensile stress,
whereas compressive stress tends to improve hole mobility
Digital IC 2: Device
Metal gates bound to come back
50/41
A number of undesirable phenomena are associated with polysilicon as a
gate material
Digital IC 2: Device
Silicon-on-insulator (SOI)
technology• The inherent electrical insulation of MOSFETs does
away with the need for wells.
• No parasitic BJTs and, no exposure to latch-up.
• No need for body ties and, superior layout density.
• Reduced sensitivity to radiation effects and higher
operating temperatures.
• The poor thermal conductivity of the insulating layer
impedes heat removal.
51/41
Digital IC 2: Device
New devicesIn a planar double-gate device (DG-MOSFET), a horizontal inversion channel is
sandwiched between a pair of electrically connected gate electrodes in such a way as
to steer the channel from both sides at the same time
52/41
• The search for better semiconductor
materials
• Vertical integration
Digital IC 2: Device
The search for new device
topologies• Non-CMOS data storage
• Phase-change RAM (PRAM)
• Ferroelectric RAM (FeRAM)
• Magnetic RAM (MRAM)
53/41
Digital IC 2: Device
The search for new device topologies
____Non-CMOS data processing• Carbon nanotubes
• Philip G. Collins and Phaedon Avouris. Nanotubes for
Electronics. Scientific American, 283(48):38–45, December
2000.
• Nanojunctions
• Yu Huang et al. Logic Gates and Computation from Assembled
Nanowire Building Blocks. Science, 294(5545):1313–1317,
November 9, 2001.
• Molecular electronics
• A. J. Heinrich, C. P. Lutz, J. A. Gupta, and D. M. Eigler.
Molecule Cascades. Science,298(5597):1381–1387, November
2002. Carbon monoxide, two-input sorter, molecular electronics.
• Crossbar logic
• Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams.
Crossbar Nanocomputers. Scientific American, 293(5):50–55,
November 2005.54/41
Digital IC 2: Device
The search for new device topologies
____Non-CMOS data processing
• Magnetic flux quantum device
• Darren K. Brock, Elie K. Track, and John M. Rowell.
Superconductor ICs: the 100-GHz second generation. IEEE
Spectrum, 37(12):40–46, September 2000.
• Quantum cellular arrays
• John Baliga. QCA Devices may take over when CMOS is done.
Semiconductor International, 22(12):48, October 1999.
• Quantum devices
• Ralph Cavin and Victor Zhirnov. Generic device abstractions for
information processing technologies. Solid-State Electronics,
50(4):520–526, 2006.
55/41