EPC2108 – Enhancement-Mode GaN Power Transistor Half

eGaN® FET DATASHEET EPC2108

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EPC2108 – Enhancement-Mode GaN Power Transistor Half-Bridge with Integrated Synchronous BootstrapVDS , 60 V RDS(on) , 240 mΩ ID , 1.7 A

EPC2108 eGaN® ICs are supplied only inpassivated die form with solder bumps Die Size: 1.35 mm x 1.35 mm

Applications • High Frequency DC-DC Conversion • Class-D Audio • Wireless Power (Highly Resonant and Inductive)

Benefits• Ultra High Efficiency• Ultra Low RDS(on)• Ultra Low QG• Ultra Small Footprint

EFFICIENT POWER CONVERSION

HAL

SBTST

DGrev

Q1

Q2

1 7

4

5

8

Q3

23

6

9

GBTST

DBTST Gupper Positive

GroundGlower

Out2

Out1

EPC2108 – Detailed Schematic

Maximum Ratings

DEVICE PARAMETER VALUE UNIT

Q1 &

Q2

VDS

Drain-to-Source Voltage (Continuous) 60V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 72

ID

Continuous (TA = 25˚C, RθJA = 60°C/W) 1.7A

Pulsed (25°C, TPULSE = 300 µs) 5.5

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage –4

TJ Operating Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Q3

VDS

Drain-to-Source Voltage (Continuous) 100V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120

ID

Continuous (TA = 25°C, RθJA= 100°C/W) 0.5A

Pulsed (25°C, TPULSE = 300 µs) 0.5

VGS

Gate-to-Source Voltage 6V

Operating Temperature –40 to 150

TJ Storage Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 6

°C/WRθJB Thermal Resistance, Junction-to-Board 33

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 81

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details

http://epc-co.com/epc

https://www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2108.aspx

https://www.epc-co.com

https://www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2108.aspx

https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf



Static Characteristics (TJ= 25˚C unless otherwise stated)DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Q1 & Q2

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.3 mA 60 VIDSS Drain-Source Leakage VDS = 48 V, VGS = 0 V 0.05 0.25 mA

IGSS

Gate-to-Source Forward Leakage VGS = 5 V 0.1 1 mAGate-to-Source Reverse Leakage VGS = -4 V 0.05 0.25 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.2 mA 0.8 1.6 2.5 VRDS(on) Drain-Source On Resistance VGS = 5 V, ID = 2.5 A 150 240 mΩVSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 2.6 V

Q3

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.125 mA 100 VIDSS Drain-Source Leakage VDS = 80 V, VGS = 0 V 0.02 0.1 mAIGSS Gate-to-Source Forward Leakage VGS = 5 V 0.1 1 mAVF Source-Gate Forward Voltage IF = 0.2 mA, VDS = 0 V 2.7 VVGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.1 mA 0.8 1.7 2.5 VRDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.05 A 2100 3300 mΩVSD Source-Drain Forward Voltage IS = 0.1 A, VGS = 0 V 2.9 V

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Q1

CISS Input CapacitanceVDS = 30 V, VGS = 0 V

26 31

pF

CRSS Reverse Transfer Capacitance 0.4COSS Output Capacitance 12 18COSS(ER) Effective Output Capacitance, Energy Related (Note 2)

VDS = 0 to 30 V, VGS = 0 V 20

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 24RG Gate Resistance 0.6 ΩQG Total Gate Charge VDS = 30 V, VGS = 5 V, ID = 2.5 A 240 310

pC

QGS Gate to Source ChargeVDS = 50 V, ID = 2.5 A

106QGD Gate to Drain Charge 47QG(TH) Gate Charge at Threshold 71QOSS Output Charge VDS = 30 V, VGS = 0 V 710 1070QRR Source-Drain Recovery Charge 0

Q2


26 31

pF

CRSS Reverse Transfer Capacitance 0.4COSS Output Capacitance 16 24COSS(ER) Effective Output Capacitance, Energy Related (Note 2)

VDS = 0 to 30 V, VGS = 0 V 25

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 31RG Gate Resistance 0.6 ΩQG Total Gate Charge VDS = 30 V, VGS = 5 V, ID = 2.5 A 240 310

pC



Q3


7 8.4

pF

CRSS Reverse Transfer Capacitance 0.02COSS Output Capacitance 1.6 2.4COSS(ER) Effective Output Capacitance, Energy Related (Note 2)

VDS = 0 to 50 V, VGS = 0 V 2.2

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 2.7RG Gate Resistance 4.8 ΩQG Total Gate Charge VDS = 50 V, VGS = 5 V, ID = 0.05 A 44 55

pC



Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(ER) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.




R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 3.0 2.5 3.5 4.0 4.5 5.0

Figure 3b (Q3): RDS(on) vs. VGS for Various Drain Currents

ID = 0.05 AID = 0.10 AID = 0.15 AID = 0.20 A

8000

6000

4000

2000

0

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 3.0 3.5 4.0 4.5 5.0

Figure 3a (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents

ID = 1.0 AID = 1.5 AID = 2.0 AID = 2.5 A

600

500

400

300

200

100

0

I D –

Drai

n Cu

rrent

(A)

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

25˚C125˚C

VDS = 3 V

VGS – Gate-to-Source Voltage (V)

Figure 2a (Q1 & Q2): Transfer Characteristics

25˚C125˚C

VDS = 3 V

5

4

3

2

1

0

I D –

Drai

n Cu

rrent

(A)

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

25˚C125˚C

VDS = 3 V


Figure 2b (Q3): Transfer Characteristics

25˚C125˚C

VDS = 3 V

0.5

0.4

0.3

0.2

0.1

0

I D –

Drai

n Cu

rrent

(A)

VDS – Drain-to-Source Voltage (V)

Figure 1a (Q1 & Q2): Typical Output Characteristics at 25°C

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V

5

4

3

2

1

00 0.5 1.0 1.5 2.0 2.5 3.0

0.5

0.4

0.3

0.2

0.1

0 0 0.5 1.0 1.5 2.0 2.5 3.0

I D –

Drai

n Cu

rrent

(A)


Figure 1b (Q3): Typical Output Characteristics at 25°C

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V




Capa

citan

ce (p

F)

100

10

1

0.1

Figure 5d (Q2): Capacitance (Log Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

0 10 20 30 40 50 60

Capa

citan

ce (p

F)

0 10 20 30 40 50 60

Figure 5c (Q2): Capacitance (Linear Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

60

50

40

30

20

10

0

Capa

citan

ce (p

F)

0 10 20 30 40 50 60

Figure 5a (Q1): Capacitance (Linear Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

50

40

30

20

10

0

Capa

citan

ce (p

F)

100

10

1

0.10 10 20 30 40 50 60

Figure 5b (Q1): Capacitance (Log Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

600

500

400

300

200

100

03.0 3.5 4.0 4.5 5.0

Figure 4a (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures

25˚C125˚C

ID = 2.5 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)


8000

6000

4000

2000

03.02.5 3.5 4.0 4.5 5.0

Figure 4b (Q3): RDS(on) vs. VGS for Various Temperatures

25˚C125˚C

ID = 0.05 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)





Figure 6a: Output Charge and COSS Stored Energy

Q OSS

– O

utpu

t Cha

rge (

nC)

E OSS

– C O

SS St

ored

Ener

gy (μ

J)

0.25

0.20

0.15

0.10

0.05

0.00

10

8

6

4

2

00 20 40 60 10080


Figure 6c (Q3): Output Charge and COSS Stored Energy

Figure 6a: Output Charge and COSS Stored Energy

Q OSS

– O

utpu

t Cha

rge (

nC)

E OSS

– C O

SS St

ored

Ener

gy (μ

J)1.0

0.8

0.6

0.4

0.2

0.0

25

20

15

10

5

00 10 20 30 40 50 60


Figure 6a (Q1): Output Charge and COSS Stored Energy Figure 6a: Output Charge and COSS Stored Energy

Q OSS

– O

utpu

t Cha

rge (

nC)

E OSS

– C O

SS St

ored

Ener

gy (μ

J)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

40

35

30

25

20

15

10

5

00 10 20 30 40 50 60


Figure 6b (Q2): Output Charge and COSS Stored Energy

Capa

citan

ce (p

F)

0 20 40 60 80 100

Figure 5e (Q3): Capacitance (Linear Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

8

7

6

5

4

3

2

1

0

Capa

citan

ce (p

F)

100

10

1

0.1

0.01

0.0010 20 40 60 80 100

Figure 5f (Q3): Capacitance (Log Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD




Figure 9b (Q3):Normalized On-State Resistance vs. Temperature

ID = 0.05 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6 0 25 50 75 100 125 150 TJ – Junction Temperature (°C)

Figure 9a (Q1 & Q2):Normalized On-State Resistance vs. Temperature

ID = 2.5 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150

TJ – Junction Temperature (°C)

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 8a (Q1 & Q2): Reverse Drain-Source Characteristics

5

4

3

2

1

0

25˚C125˚C

VDS = 3 V

25˚C125˚C

VGS = 0 V

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 8b (Q3): Reverse Drain-Source Characteristics0.5

0.4

0.3

0.2

0.1

0

25˚C125˚C

VDS = 3 V

25˚C125˚C

VGS = 0 V

0 50 100 150 250200

Figure 7a (Q1 & Q2): Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (pC)

ID = 2.5 AVDS = 30 V

5

4

3

2

1

00 10 20 30 5040

Figure 7b (Q3): Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (pC)

ID = 0.05 AVDS = 50 V

5

4

3

2

1

0




Single Pulse

tp, Rectangular Pulse Duration, seconds

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.050.02

Single Pulse

0.01

0.1

Duty Cycle:

(Q1/Q2/Q3) Junction-to-Board

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

PDM

t1

t2

10-5 10-4 10-3 10-2 10-1 1 101

1

0.1

0.01

0.001

tp, Rectangular Pulse Duration, seconds

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.1

0.02

0.05

Single Pulse

0.01

0.2

Duty Cycle:

(Q1/Q2/Q3) Junction-to-Case

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

PDM

t1

t2

10-6 10-5 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

Figure 10a (Q1 & Q2):Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.600 25 50 75 100 125 150


ID = 0.2 mA

Figure 10b (Q3):Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.600 25 50 75 100 125 150


ID = 0.1 mA

Figure 11a Transient Thermal Response Curves

Figure 11b Transient Thermal Response Curves




0.08

0.06

0.04

0.02

0.00

-0.5

-1.0

-1.5

-2.0-2 -1 0 1 2 3 4 5 6

Figure 13 (Q3): Gate-Source Characteristics

25˚C125˚C

I G –

Gate

Curre

nt (m

A)


10

1

0.10.1 1 10 100

I D – D

rain

Curre

nt (A

)

VDS – Drain-Source Voltage (V)TJ = Max Rated, TC = +25°C, Single Pulse

Limited by RDS(on)

100 ms 10 ms 1 ms 100 µs

Pulse Width

25 µs

100 µs 50 µs

Figure 12 (Q1 & Q2): Safe Operating Area

Output

Q2

Q1

Q3

CBus

Gate Driver

Leve

l Shi

ft

5 V

Figure 14: Typical Application Circuit




DIE MARKINGS

YYYY2108

ZZZZ

TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel

7” reel

a

d e f g

c

b

Dimension (mm) EPC2108 (note 1)

target min max a 8.00 7.90 8.30 b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6

Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Pin 1 isunder thiscorner

Die is placed into pocketsolder bump side down(face side down)

Loaded Tape Feed Direction

Pin 1 is under this corner

2108YYYYZZZZ EPC2108 2108 YYYY ZZZZ

Die orientation dotPart #

Marking Line 1Lot_Date CodeMarking Line 2

Lot_Date CodeMarking Line 3

PartNumber

Laser Markings




RECOMMENDEDLAND PATTERN (measurements in µm)

DIE OUTLINESolder Bump View

Side View

B

A

d c c dc

c Pad 1 is Gate1 (Q1) Pad 2 is Gate2 (Q2)Pad 3 is Gate 3 (Q3)Pad 7 is Drain1 (Q1)Pad 5 is Drain2 (Q2)Pad 6 is Drain3 (Q3)Pad 4 is Source1 (Q1)Pad 8 is Source2 (Q2)Pad 9 is Source3 (Q3)

3 6 9

2 5 8

1 4 7

165

+/-

17

815

Max

(625

)

Seating Plane

RECOMMENDEDSTENCIL DRAWING (measurements in µm)

DIM

Micrometers

MIN Nominal MAX

A 1320 1350 1380B 1320 1350 1380c 450 450 450d 210 225 240e 187 208 229

Information subject to change without notice.

Revised August, 2019

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

The land pattern is solder mask definedSolder mask is 10 μm smaller per side than bump

X9

1350

1350 2 5 8

3 6 9

1 4 7

225 225

450 450

450

450

200 +20 / - 10 (*)

* minimum 190

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Intended for use with SAC305 Type 4 solder, reference 88.5% metals content.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

250

1350

1350

225 225

450 450

450

450

R60


http://epc-co.com/epc/AboutEPC/Patents.aspx

http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

Documents

EPC2108 – Enhancement-Mode GaN Power Transistor Half