EPC2111 – Enhancement-Mode GaN Power Transistor Half-Bridge · 2020-07-20 · egan® fet datasheet epc2111 2111

eGaN® FET DATASHEET EPC2111

EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1

VDS , 30 VRDS(on) , 19 mΩ (Q1), 8 mΩ (Q2)ID , 16 A (Q1), 16 A (Q2)

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

EPC2111 eGaN® ICs are supplied only inpassivated die form with solder bumps Die Size: 3.5 mm x 1.5 mm

Applications

• High Frequency DC-DC

• Point-of-Load (POL) Converters

Benefits

• High Frequency Operation (up to 10 MHz)

• Low Inductance Package

• High Density Footprint

EFFICIENT POWER CONVERSION

HAL

Maximum Ratings

DEVICE PARAMETER VALUE UNIT

Q1

VDS

Drain-to-Source Voltage (Continuous) 30V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 36

ID

Continuous (TA = 25°C, RθJA = 15°C/W) 16A

Pulsed (25°C, TPULSE = 300 µs) 50

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Q2

VDS

Drain-to-Source Voltage (Continuous) 30V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 36

ID

Continuous (TA = 25°C, RθJA = 36°C/W) 16A

Pulsed (25°C, TPULSE = 300 µs) 140

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJ Operating Temperature –40 to 150°C

TSTG Storage Temperature –40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 1.3

°C/W RθJB Thermal Resistance, Junction-to-Board 6.6

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 58Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details

EPC2111 – Enhancement-Mode GaN Power Transistor Half-Bridge

https://www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2111.aspx

https://www.epc-co.com

https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf

https://www.epc-co.com/epc/Products/eGaNFETsandICs/EPC2111.aspx



Dynamic Characteristics

DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Q1

CISS Input Capacitance

VDS = 15 V, VGS = 0 V

190 230

pF

CRSS Reverse Transfer Capacitance 8

COSS Output Capacitance 170 255

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 15 V, VGS = 0 V

204

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 217

RG Gate Resistance 0.5

QG Total Gate Charge VDS = 15 V, VGS = 5 V, ID = 15 A 1.7 2.2

nC

QGS Gate-to-Source Charge

VDS = 15 V, ID = 15 A

0.6

QGD Gate-to-Drain Charge 0.3

QG(TH) Gate Charge at Threshold 0.4

QOSS Output Charge VDS = 15 V, VGS = 0 V 3.3 5

QRR Source-Drain Recovery Charge 0

Q2

CISS Input Capacitance

VDS = 15 V, VGS = 0 V

495 595

pF

CRSS Reverse Transfer Capacitance 21

COSS Output Capacitance 490 735

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 15 V, VGS = 0 V

590

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 637

RG Gate Resistance 0.4

QG Total Gate Charge VDS = 15 V, VGS = 5 V, ID = 15 A 4.5 5.8

nC

QGS Gate-to-Source Charge

VDS = 15 V, ID = 15 A

1.4

QGD Gate-to-Drain Charge 0.8

QG(TH) Gate Charge at Threshold 1

QOSS Output Charge VDS = 15 V, VGS = 0 V 9.6 15

QRR Source-Drain Recovery Charge 0

Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

Static Characteristics

DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Q1

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.25 mA 30 V

IDSS Drain-Source Leakage VDS = 24 V, VGS = 0 V 0.002 0.15 mA

IGSSGate-to-Source Forward Leakage VGS = 5 V 0.004 2 mA

Gate-to-Source Reverse Leakage VGS = -4 V 0.002 0.15 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 2 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 15 A 14 19 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V

Q2

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.4 mA 30 V

IDSS Drain-Source Leakage VDS = 24 V, VGS = 0 V 0.005 0.3 mA

IGSSGate-to-Source Forward Leakage VGS = 5 V 0.01 4.5 mA

Gate-to-Source Reverse Leakage VGS = -4 V 0.005 0.3 mA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 5 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 15 A 6 8 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V



R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 3.0 2.5 3.5 4.0 4.5 5.0

Figure 3b (Q2): RDS(on) vs. VGS for Various Drain Currents

ID = 5 AID = 10 AID = 15 AID = 20 A

20

15

10

5

0

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 3.0 2.5 3.5 4.0 4.5 5.0

Figure 3a (Q1): RDS(on) vs. VGS for Various Drain Currents

ID = 5 AID = 10 AID = 15 AID = 20 A

50

40

30

20

10

0

I D –

Drai

n Cu

rrent

(A)

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

25˚C125˚C

VDS = 3 V

VGS – Gate-to-Source Voltage (V)

Figure 2a (Q1): Transfer Characteristics

25˚C125˚C

VDS = 3 V

50

40

30

20

10

0

I D –

Drai

n Cu

rrent

(A)

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

25˚C125˚C

VDS = 3 V


Figure 2b (Q2): Transfer Characteristics

25˚C125˚C

VDS = 3 V

120

80

40

0

50

40

30

20

10

0 0 0.5 1.0 1.5 2.0 2.5 3.0

I D –

Drai

n Cu

rrent

(A)

VDS – Drain-to-Source Voltage (V)

Figure 1a (Q1): Typical Output Characteristics at 25°C

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V

120

80

40

00 0.5 1.0 1.5 2.0 2.5 3.0

I D –

Drai

n Cu

rrent

(A)


Figure 1b (Q2): Typical Output Characteristics at 25°C

VGS = 5 V

VGS = 4 V

VGS = 3 V

VGS = 2 V



Capa

citan

ce (p

F)

0 5 10 2015 25 30

Figure 5a (Q1): Capacitance (Linear Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

300

200

100

0

Capa

citan

ce (p

F)

1000

800

600

400

200

00 5 10 15 3020 25

Figure 5b (Q2): Capacitance (Linear Scale)


COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

50

40

30

20

10

03.02.5 3.5 4.0 4.5 5.0

Figure 4a (Q1): RDS(on) vs. VGS for Various Temperatures

25˚C125˚C

ID = 15 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)


20

15

10

5

03.02.5 3.5 4.0 4.5 5.0

Figure 4b (Q2): RDS(on) vs. VGS for Various Temperatures

25˚C125˚C

ID = 15 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)


Figure 6a: Output Charge and COSS Stored Energy

Q OSS

– O

utpu

t Cha

rge (

nC)

E OSS

– C O

SS St

ored

Ener

gy (n

J)

20

15

10

5

0

200

150

100

50

00 5 10 252015 30


Figure 6b (Q2): Output Charge and COSS Stored EnergyFigure 6a: Output Charge and COSS Stored Energy

Q OSS

– O

utpu

t Cha

rge (

nC)

E OSS

– C O

SS St

ored

Ener

gy (n

J)

70

60

50

40

30

20

10

00 5 10 15 20 25 30


Figure 6a (Q1): Output Charge and COSS Stored Energy7

6

5

4

3

2

1

0



0 1 2 3 4 5

Figure 7b (Q2): Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (nC)

ID = 15 AVDS = 15 V

5

4

3

2

1

00 0.5 1.0 1.5 2.0

Figure 7a (Q1): Gate ChargeV G

S –

Gate

-to-S

ourc

e Vol

tage

(V)

QG – Gate Charge (nC)

ID = 15 AVDS = 15 V

5

4

3

2

1

0

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 8a (Q1): Reverse Drain-Source Characteristics50

40

30

20

10

0

25˚C125˚C

VDS = 3 V

25˚C125˚C

VGS = 0 V

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 8b (Q2): Reverse Drain-Source Characteristics

120

80

40

0

25˚C125˚C25˚C125˚C

VGS = 0 V

Figure 9a (Q1):Normalized On-State Resistance vs. Temperature

ID = 15 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150

TJ – Junction Temperature (°C)

Figure 9b (Q2):Normalized On-State Resistance vs. Temperature

ID = 15 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150




Figure 10b (Q2):Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.60 25 50 75 100 125 150


ID = 5 mA

Figure 10a (Q1):Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.60 25 50 75 100 125 150


ID = 2 mA

100

10

1

0.10.1 1 10 100

I D – D

rain

Curre

nt (A

)

VDS – Drain-Source Voltage (V)TJ = Max Rated, TC = +25°C, Single Pulse

Limited by RDS(on)

100 ms 10 ms 1 ms

Pulse Width 1 ms 250 µs

100 µs

Figure 11a (Q1): Safe Operating Area1000

100

10

1

0.10.1 1 10 100

I D – D

rain

Curre

nt (A

)

VDS – Drain-Source Voltage (V)TJ = Max Rated, TC = +25°C, Single Pulse

Limited by RDS(on)

Pulse Width

100 µs

1 ms 250 µs

Figure 11b (Q2): Safe Operating Area

Figure 12 Typical Application Circuit

SW

Positive

Ground

Q2

Q1

G1

G2



tp, Rectangular Pulse Duration, seconds

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.05

0.02

Single Pulse

0.01

0.10.2

Duty Cycle:

(Q1 & Q2) Junction-to-Board

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

PDM

t1

t2

10-5 10-4 10-3 10-2 10-1 1 101

1

0.1

0.01

0.001

tp, Rectangular Pulse Duration, seconds

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.1

0.02

0.05

Single Pulse

0.01

0.2

Duty Cycle:

(Q1 & Q2) Junction-to-Case

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

PDM

t1

10-6 10-5 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

Figure 13a Transient Thermal Response Curves

Figure 13b Transient Thermal Response Curves



DIE MARKINGS

TAPE AND REEL CONFIGURATION4mm pitch, 12mm wide tape on 7” reel

7” reel

Die is placed into pocketsolder ball side down(face side down)

Loaded Tape Feed Direction

2111

YYYY

ZZZZ

Dieorientationdot

Gate bumps are along this edge of the die

a

d e f g

c

b

DIM Dimension (mm)EPC2111 (Note 1) Target MIN MAX

a 12.00 11.90 12.30b 1.75 1.65 1.85c (Note 2) 5.50 5.45 5.55d 4.00 3.90 4.10e 4.00 3.90 4.10f (Note 2) 2.00 1.95 2.05g 1.50 1.50 1.60

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking Line 2

Lot_Date CodeMarking Line 3

EPC2111 2111 YYYY ZZZZ

Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.

Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

2111

YYYY

ZZZZDie orientation dot

Pin 1 is under this corner



Information subject to change without notice.

Revised June, 2020

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

RECOMMENDED LAND PATTERN (measurements in µm)

Pad 1 is G1; Pad 3 is G2;Pads 4, 7, 10, 13, 16, 19 are VIN;Pads 2, 5, 8, 11, 14, 17, 20 are SN;Pads 6, 9, 12, 15, 18, 21 are GND

The land pattern is solder mask defined.Solder mask is10 µm smaller per side than bump.

DIE OUTLINESolder Bump View

Side View

DIM MIN Nominal MAX

A 3470 3500 3530B 1470 1500 1530c 500 500 500d 500 500 500e 238 264 290

RECOMMENDED STENCIL DRAWING (measurements in µm)

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. The corner has a radius of R60.

Intended for use with SAC305 Type 4 solder, reference 88.5% metals content.

Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx

A

B

500

500230

19

21

20

16

18

17

13

15

14

10

12

11

7

9

8

4

6

5

1

3

2

3500

1500

500275

275

19

21

20

16

18

17

13

15

14

10

12

11

7

9

8

4

6

5

1

3

2R60

(685

)

(885

)

200+

/−20

A

B

e

c

d

Seating plane

19

21

20

16

18

17

13

15

14

10

12

11

7

9

8

4

6

5

1

3

2

https://epc-co.com/epc/AboutEPC/Patents.aspx

https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

Documents

EPC2111 – Enhancement-Mode GaN Power Transistor Half-Bridge · 2020-07-20 · egan® fet datasheet epc2111 2111