CprE 588 Embedded Computer Systemshome.engineering.iastate.edu/~zambreno/classes/cpre588/lectures/… · Mar 3-5, 2009 CprE 588 – Embedded Computer Systems Lect-08.2 Outline •

CprE 588

Embedded Computer Systems

Prof. Joseph Zambreno

Department of Electrical and Computer Engineering

Iowa State University

Lecture #8 – Architectural Specialization

CprE 588 – Embedded Computer SystemsMar 3-5, 2009 Lect-08.2

Outline

• Motivation

• Related Work

• Design Flow

• Basic Concepts

• Multi-Metrics

• Experimental Results

• Conclusion

L. Cai, A. Gerstlauer, and D. Gajski, “Retargetable Profiling for Rapid, Early System-Level Design Space Exploration”, In Proceedings of the Design Automation Conference (DAC), 2004.


Motivation

Time-to-market

↓↓↓↓

SoC Complexity

↑↑↑↑

Higher levels of abstraction

ExplorationEstimationModelinglevel n

Verification Refinementn+1


System Level Estimation

• Fast

• Accurate � Fidelity

• Different abstraction levels

• Wide range of metrics

• Wide variety of target implementation


Related Work

• Static analysis-based approaches

• Examples

• WCET (Y. Li), scheduling analysis (G. Buttazzo)

• Memory size estimation (Y. Zhao)

• Limitations

• Time-consuming, manual interference

• Dynamic simulation-based approaches

• Examples

• Profiling tools (GNU profiler)

• Instruction-set simulators

• Multi-processor, multi-level co-simulation (P. Gerin)

• Trace-based simulation (K. Lahir, P. Lieverse)

• Limitations

• A simulation is required for each design alternative

• Target/host machine-dependent characteristics

• Operation-related data


Spec

modelSimulation

Profiling

Spec

characteristics

GUIEstimationRefinement

Pro

filin

g

Design Flow


Design Flow (cont.)

Spec

model

Back

annotation

Refining

Simulation

Profiling

Retargeting

Spec

characteristics

Implt

Characteristics


Design

decision

Pro

filin

gR

eta

rge

tin

g


Design Flow (cont.)

Spec

model

Refined

model

Back

annotation

Refining

Instru-

menting

Profiling

Retargeting

Simulation/

estimation

Spec

characteristics

Implt

Characteristics

Implt.

Estimates


Design

decision

Pro

filin

gR

eta

rge

tin

g

Sim

ula

tio

n-

es

tim

ati

on


Explore and Trim

Exploration

Space

Design

TimeProfiling

stage

Retargeting

stage

Simulation-

estimation

stage

...

...

One-time

retargeting Implt

dependent

simulation

/estimation

Implt

independent

simulation

Profiling


Profiling

• Instrumentation-based profiling

• Bb: The execution counts of basic block b

• Cb,i,d: No. of computed characteristics for item type i

and data type d in the block b

• Data type i: float, int, ..

• Item type d: metric dependant

• Ri,d = ΣbC b,i,d Bb

• R = ΣiΣdRi,d

int b,c;

if( a = 0){

b++;

}

else{

b++;

c++;

}

R++,int= Σ i [ Bi * Ci,++,int ]

=1 x 1 + 3 x 2

= 7

B1 = 1

B3 = 3

C1,++,int = 1

C3,++,int = 2


Retargeting

• Impl. characteristics

• Ri,d: Spec. characteristics

• Wi,d : weights of components which the entity mapped to

• Manual

• Simulation

• E = ΣiΣd(Ri,d X Wi,d )

• Time complexity: O(n)

vcB1 B2

B

PE1 PE2

Mem

R(B1)++,int= 7

W(PE1)++,int= 1

E(B1,PE1)++,int= 7 x 1 = 7


• Separating dynamic and

static analysis

Challenges



static analysis

• Supporting complex models

• Hierarchy

• Recursion

Challenges (cont.)

v

cB1 B2

B



static analysis


• Hierarchy

• Recursion

• Multi-dimensional analysis

Challenges (cont.)

v

cB1 B2

B

Traditional approach



static analysis


• Hierarchy

• Recursion


• Multi-entities

• Behavior, channel, port,

variable

Challenges (cont.)

v

cB1 B2

B

Entities


• Separating dynamic and static analysis


• Hierarchy

• Recursion


• Multi-entities• Behavior, channel, port,

variable

• Multi-metrics• Operation, traffic, storage

• Static, dynamic

Challenges (cont.)

v

cB1 B2

B

Entities

Metrics


• Separating dynamic and static analysis


• Hierarchy

• Recursion


• Multi-entities• Behavior, channel, port, variable

• Multi-metrics• Operation, traffic, storage

• Static, dynamic

• Multi-levels• Application, transaction, bus-

functional

Challenges (cont.)

Entities

Metrics

Levels

v

cB1 B2

B


Operation Metrics

• Entities: behavior

• Item types

• 84 basic types: ‘+’.., ‘=‘.., ‘if’..

• Special operation types: global function

• Specification characteristics

• Mapping: behavior � PE

• Implementation characteristics

Static Dynamic

Def. No. of operations in spec No. of executed Oper. during simulation Rep. Code complexity Computational complexity

Static Dynamic

Rep. Code Size: Program memory size(SW) Custom hardware controller(HW)

No. of executed clock cycles: Execution time; power consumption


Traffic Metrics

• Entities: port, variable, channel, behavior

• Item types: in, out


• Mapping:

• Port � PE

• Variable/channel � bus


Bus Communication delay

PE Data preparation time

Static Sequential behaviors

Dyn. Parallel behaviors

Static Dynamic

Def. No. of connected ports No. of P/V/C accessed during simulation

Rep. Connectivity complexity. Access complexity.

Application level Traffic between behaviors.

Bus functional level Fan-in/fan-out, bus capacity, traffic over pin


Deriving Traffic Metrics

• Profiling for the hierarchically instantiated behaviors and recursively called functions

• A.p1 � B.p2 � B.F1.p3 � B.F2.P4

B

A

p2

p1

F1 F2

Main

F1(P2);

p3 p4

F2(p3); v1 = p4;

PE1 PE2 PE2PE1Beh1 Beh2

v1

• Different abstraction levels

• Beh.port → Var • Beh.port → Chan

• Chan in Chan

• Beh.port → Pin

• Chan.port � Chan


Storage Metrics

• Entity: variable, behavior

• Item types: local, global


• Mapping:

• Variable � local/global memory


Static Dynamic

Rep. Static memory size Stack/heap size

Static Dynamic

Def. No. of static variables No. of dynamic allocated memory

Rep. Static memory requirement

Stack requirement (local) Heap requirement (global)


Table 1: Computational complexity of top-level Vocoder behaviors

Table 2: Codebook operation mix

LP_Analysis Open_Loop Closed_Loop Codebook Update 377.0 MOp 337.1MOp 478.7 Mop 646.4 Mop 43.6 Mop

(x, int) (+, int) (-, int) (/,int) (others,int) 46.2% 33.5% 9.1% 7.1% 4.1%

HW

acceleration

Floating –point not

required

Dedicated hardware

multipliers

Exp. Result: Vocoder Profiling


• 8 behaviors � 3 PEs

• Total 38 =6561 design alternatives

• Evaluation time: 3:15 hour

• 1 simulation (2.23s)

• 1 profiling (8.41s)

• 6561 retargeting (0.8s)

• 6561mapping (0.97s)

Exp. Result: Vocoder Profiling (cont.)

1500

2500

3500

4500

10 30 50 70 90 110 130 150 170

u

Timing constraint (2990)

Tim

e (

ms)

Cost

B (73, 2980)


• Map 4 behaviors � 2 PEs: 24 design alternatives

• Accuracy: 12.5%, fidelity = 100%

Exp. Result: JPEG Encoder

Implementation characteristics vs implementation estimates

0

50

100

150

200

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Design alternatives

Execu

tio

n t

ime (

ms))

Estimates

Char.


Conclusion

• Dynamic profiling + static retargeting

• Profiling: helps completely comprehend the specification

• Retargeting: ultra-fast (linear time), enables initial,

exhaustive exploration of design space.


• Multi-entities

• Behavior, channel, variable, port

• Multi-abstraction levels

• Application level, transaction level, bus-functional level

• Multi-metrics

• Operation, traffic, storage

• Static, dynamic

Documents

CprE 588 Embedded Computer Systemshome.engineering.iastate.edu/~zambreno/classes/cpre588/lectures/… · Mar 3-5, 2009 CprE 588 – Embedded Computer Systems Lect-08.2 Outline •