CPRE 583 Reconfigurable Computing Lecture 6: Wed 10/21/2009 (Design Patterns)

1 - CPRE 583 (Reconfigurable Computing): Design Patterns Iowa State University (Ames)

CPRE 583Reconfigurable ComputingLecture 6: Wed 10/21/2009

(Design Patterns)

Instructor: Dr. Phillip Jones([email protected])

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ee.iastate.edu/cpre583/


• Class Projects

• Common Design Patterns

Overview


Project Grading Breakdown

• 60% Final Project Demo• 30% Final Project Report

– 30% of your project report grade will come from your 5 project updates. Friday’s midnight

• 10% Final Project Presentation


Initial Project Proposal Slides (5-10 slides)

• Project team list: Name, Responsibility (who is project leader)• Project idea

• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product

• High-level Plan– Break project into mile stones

• Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.

– System block diagrams– High-level algorithms (if any)– Concerns

• Implementation• Conceptual

• Research papers related to you project idea


Project Update

• The current state of your project write up– Even in the early stages of the project you

should be able to write a rough draft of the Introduction and Motivation section

• The current state of your Final Presentation– Your Initial Project proposal slides (Due Fri

10/23). Should make for a starting point for you Final presentation

• What things are work & not working• What roadblocks are you running into


• Expectations– Working system– Write up that can potentially be submitted to

a conference• Will use DAC format as write up guide line

– 15-20minute PowerPoint Presentation

• DAC (Design Automation Conference)– http://www.dac.com/46th/index.aspx

– Due Date: 5pm (MT) Monday 12/8/2008?– Cash Prizes

Projects


• FPL• FPT• FCCM• DAC• ICCAD• Reconfig• RTSS• RTAS

Projects: Relevant conferences


• Teams Formed and Idea: Wed 10/21– Project idea in Power Point 3-5 slides

• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product

– Project team list: Name, Responsibility• High-level Plan: Fri 10/23 (9pm)

– Power Point 5-10 slides• System block diagrams• High-level algorithms (if any)• Concerns

– Implementation– Conceptual

Projects: Target Timeline


• Work on projects: 10/27 - 12/12– Weekly update reports

• More information on updates will be given• Presentations: Last Wed Fri of class

– Present / Demo what is done at this point– 15-20 minutes (depends on number of projects)

• Final write and HW turn in: Day of final (TBD)

Projects: Target Timeline


• Introduction to common Design Patterns & Compute Models

What you should learn


• Design patterns– Why are they useful?– Examples

• Compute models– Why are they useful?– Examples

Outline


• Design patterns– Why are they useful?– Examples

• Compute models– Why are they useful?– Examples

Outline


References

• Reconfigurable Computing (2008) [1]– Chapter 5: Compute Models and System

Architectures• Scott Hauck, Andre DeHon

• Design Patterns for Reconfigurable Computing [2]– Andre DeHon (FCCM 2004)

• Type Architectures, Shared Memory, and the Corollary of Modest Potential [3]– Lawrence Snyder: Annual Review of Computer

Science (1986)


• Design patterns: are a solution to reoccurring problems.

Design Patterns


• “Building good reconfigurable designs requires an appreciation of the different costs and opportunities inherent in reconfigurable architectures” [2]

• “How do we teach programmers and designers to design good reconfigurable applications and systems?” [2]

• Traditional approach:– Read lots of papers for different applications– Over time figure out ad-hoc tricks

• Better approach?:– Use design patterns to provide a more systematic way

of learning how to design– It has been shown in other realms that studying

patterns is useful• Object oriented software [93]• Computer Architecture [79]

Reconfigurable Hardware Design


• Provides a means to organize and structure the solution to a problem

• Provide a common ground from which to discuss a given design problem

• Enables the ability to share solutions in a consistent manner (reuse)

Common Langue


• 10 attributes suggested by Gamma (Design Patters, 1995)– Name: Standard name– Intent: What problem is being addressed?, How?– Motivation: Why use this pattern– Applicability: When can this pattern be used– Participants: What components make up this pattern– Collaborations: How do components interact– Consequences: Trade-offs– Implementation: How to implement– Known Uses: Real examples of where this pattern

has been used.– Related Patterns: Similar patterns, patterns that can

be used in conjunction with this pattern, when would you choose a similar pattern instead of this pattern.

Describing a Design Pattern [2]


• Coarse-grain Time-multiplexing

• Template Specialization

Example Design Pattern


Coarse-grain Time-Multiplexing

M2

M1 A B M3

A

M1 M2

M3 Temp

B

M1 M2

M3 Temp

Configuration 1 Configuration 2


• Name: Coarse-grained Time-Multiplexing

• Intent: Enable a design that is too large to fit on a chip all at once to run as multiple subcomponents

• Motivation: Method to share limited fixed resources to implement a design that is too large as a whole.



• Applicability: – Configuration can be done on large time scale– No feedback loops in computation– Feedback loop only spans the current

configuration– Feedback loop is very slow

• Participants:– Computational graph– Control algorithm

• Collaborations: Control algorithm manages when sub-graphs are loaded onto the device



• Consequences: Often platforms take millions of cycles to reconfigure– Need an app that will run for 10’s of millions of

cycles before needing to reconfigure– May need large buffers to store data during a

reconfiguration• Known Uses:

– Video processing pipeline [Villasenor]• “Video Communications using Rapidly

Reconfigurable Hardware”, Transactions on Circuits and Systems for Video Technology 1995

– Automatic Target Recognition [[Villasenor]• “Configurable Computer Solutions for Automatic

Target Recognition”, FCCM 1996



• Implementation: – Break design into multiple sub graphs that can

be configured onto the platform in sequence– Design a controller to orchestrate the

configuration sequencing– Take steps to minimize configuration time

• Related patterns:– Streaming Data– Queues with Back-pressure




M2

M1 A B M3

A

M1 M2

M3 Temp

B

M1 M2

M3 Temp

Configuration 1 Configuration 2


Template SpecializationEmpty LUTs

C(3)

----

LUT

C(2)

----

LUT

C(1)

----

LUT

C(0)

----

LUT

A(1)A(0)

Mult by 3

C(3)

0001

LUT

C(2)

0010

LUT

C(1)

0110

LUT

C(0)

0101

LUT

A(1)

A(0)

Mult by 5

C(3)

0011

LUT

C(2)

0101

LUT

C(1)

0011

LUT

C(0)

0101

LUT

A(1)

A(0)

0369

051015


• Name: Template Specialization

• Intent: Reduce the size or time needed for a computation. (note primary difference from Template pattern is this pattern aims to minimize run-time reconfiguration)

• Motivation: Use early-bound data and slowly changing data to reduce circuit size and execution time.

Template Specialization


• Applicability: When circuit specialization can be adapted quickly– Example: Can treat LUTs as small memories

that can be written. No interconnect modifications

• Participants: – Template cell: Contains specialization

configuration– Template filler: Manages what and how a

configuration is written to a Template cell• Collaborations: Template filler manages

Template cell



• Consequences: Can not optimize as much as when a circuit is fully specialize for a given instance. Overhead need to allow template to implement several specializations.

• Known Uses:– Multiply-by-Constant– String Matching

• Implementation: Multiply-by-Constant– Use LUT as memory to store answer– Use controller to update this memory when a

different constant should be used.



• Related patterns:– CONSTRUCTOR– EXCEPTION– TEMPLATE



Template SpecializationEmpty LUTs

C(3)

----

LUT

C(2)

----

LUT

C(1)

----

LUT

C(0)

----

LUT

A(1)A(0)

Mult by 3

C(3)

0001

LUT

C(2)

0010

LUT

C(1)

0110

LUT

C(0)

0101

LUT

A(1)

A(0)

Mult by 5

C(3)

0011

LUT

C(2)

0101

LUT

C(1)

0011

LUT

C(0)

0101

LUT

A(1)

A(0)

0369

051015


Next Lecture

• Compute Models


Slides in Progress

• Need to revise this lecture with figures, and useful animations

• Add some non-FPGA systems, maybe not since GARP, and PipeRench were discussed in last lecture. Perhaps just mention again– Main reason other archs are not used is

economy of scales. Lots of FPGAs are manufacture, thus lowing cost and enable the use of state of the art fab technology (given high performance


Reducing Configuration Transfer Time

• Arch approach– Partial reconfiguration

• Compression


Configuration Security• Arch approach

– Partial reconfiguration

• Compression

Documents

CPRE 583 Reconfigurable Computing Lecture 6: Wed 10/21/2009 (Design Patterns)