CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )

1 - CPRE 583 (Reconfigurable Computing): VHDL overview 1 Iowa State University (Ames)

CPRE 583Reconfigurable Computing

Lecture 2: 8/26/2011(VHDL Overview 1 )

Instructor: Dr. Phillip Jones([email protected])

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/


• VHDL review 1– Highly recommend VHDL tutorial

• 120 pages with a LOT of examples• http://courseware.ee.calpoly.edu/~bmealy/shock_awe_vhdl_adobe.pdf

– Quick reference• http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)

– Some links other VHDL tutorials• http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html• http://www.vhdl-online.de/tutorial/

• HW 1 overview

Overview


VHDL basics• VHDL: (V)HSIC (H)ardware (D)escription (L)anguage

– VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit

• It is NOT a programming language!!!

• It is a Hardware Description Language (HDL)

• Conceptually VERY different form C,C++


Some Key Differences from C

• C is inherently sequential (serial), one statement executed at a time

• VHDL is inherently concurrent (parallel), many statements executed at a time


Some Key Differences from CC example VHDL example

A = B + CX = Y + ZAns = A + X

Initially: A,B,C,X,Y,Z,Ans =1

A <= B + CX <= Y + ZAns <= A + X

Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1




A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X





A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X





A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X





A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X



“Simulates in parallel ever delta time step”



A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X




Snap shot after input change



A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X






A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X




Different



A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X




Snap shot after input change



A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X






A = B + CX = Y + ZAns = A + X


A <= B + CX <= Y + ZAns <= A + X






Ans = A + XA = B + CX = Y + Z


Ans <= A + XA <= B + CX <= Y + Z



Change order ofstatements


Corresponding circuitVHDL example


A <= B + CX <= Y + ZAns <= A + X





A <= B + CX <= Y + ZAns <= A + X


+

+

B(1)C(1)

Y(1)Z(1)

+A(1)

X(1)

Ans(1)




A <= B + CX <= Y + ZAns <= A + X


+

+

B(1)C(1)

Y(1)Z(1)

+A(2)

X(2)

Ans(2)




A <= B + CX <= Y + ZAns <= A + X


+

+

B(1)C(1)

Y(1)Z(1)

+A(2)

X(2)

Ans(4)


Corresponding circuit (More realistic)VHDL example


A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns


+

+

B(1)C(1)

Y(1)Z(1)

+A(1)

X(1)

Ans(1)2ns

2ns

2ns


VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1


+

+

B(1)C(1)

Y(1)Z(1)

+A(2)

X(2)

Ans(2)

Corresponding circuit (More realistic)

2ns

2ns

2ns



VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1


+

+

B(1)C(1)

Y(1)Z(1)

+A(2)

X(2)

Ans(4)

Corresponding circuit (More realistic)

2ns

2ns

2ns



Typical Structure of a VHDL FileLIBRARY ieee;

ENTITY test_circuit IS PORT(B,C,Y,Z,Ans);END test_circuit;

ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0);

BEGIN

A <= B + C; X <= Y + Z; Ans <= A + X;

END

Include Libraries

Define component name andInput/output ports

Declare internalsignals, components

Implement components functionality


Process• Process provide a level serialization in VHDL (e.g.

variables, clocked processes)

• Help separate and add structure to VHDL design


Process ExampleBEGIN

My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1;

My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2;

END;

Sensitivity list: specify inputs to theprocess. Process is updated when a specified input changes


Process Example (Multiple Drivers)BEGIN


My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2;

END;

A signal can only be Driven (written) by one process. But can be readby many

Compile or simulator may give a “multiple driver” Erroror Warning message


Process Example (Multiple Drivers)BEGIN


My_process_2 : process (B,X,Y,Ans1) Begin A1 <= B + 1; X1 <= B + Y; Ans2 <= Ans1 + X; End My_process_2;

END;

Maybe A,X were suppose to be A1,X1. Cutand paste error. Or may need to rethink Hardware structure to remove multiple driverissue.


Process Example (if-statement)BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin

if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if;

End My_process_1;END;


Clock Process ExampleBEGIN

My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1;

END;

or

or

A()B()

X()Y()

and

C()

Z()

Ans()

circuit not clocked


Clock Process ExampleBEGIN

My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1;

END;

or

or

A()B()

X()Y()

and

C()

Z()

Ans()

circuit with clock

clk

D Flip-FlopDFF

Register


Clock Process ExampleBEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1;END;

or

or

A()B()

X()

Y()

and

C()

Z()

Ans()

circuit with clock

clk


Clock Process Example 2BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1;END;

xor

or

A()B()

X()

Y()

xor

C()

Z()

Ans()

circuit with clock

clk


Clock Process Example 2 (Answer)BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1;END;

xor

or

A()B()

X()

Y()

xor

C()

Z()

Ans()

circuit with clock

clk


VHDL Constructs

• Entity• Process• Signal, Variable, Constants, Integers• Array, Record

VHDL on-line tutorials:http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.htmlhttp://www.vhdl-online.de/tutorial/


Signals and Variables• Signals

– Updated at the end of a process– Have file scope

• Variables– Updated instantaneously– Have process scope


std_logic, std_logic_vector• Very common data types

• std_logic– Single bit value– Values: U, X, 0, 1, Z, W, H, L, -– Example: signal A : std_logic;

• A <= ‘1’;• Std_logic_vector: is an array of std_logic

– Example: signal A : std_logic_vector (4 downto 0);• A <= x“00Z001”


Std_logic values• Std_logic values

– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)

• I have never used this value– L : weak ‘0’

Time step 0


• Std_logic values– U : Uninitialized (signal has not been assigned a value yet)– X : Unknow (2 drivers one ‘0’ one ‘1’)– H : weak ‘1’ (example: model pull-up resister)


Time step 0

1 U U U

Std_logic values




Time step 1

0 1 U U

Std_logic values




Time step 2

1 0 1 U

Std_logic values




Time step 3

1 1 0 1

Std_logic values




Time step 3

1 1 0 1

0 1

X

Std_logic values




Time step 3

1 1 0 1

0 1

X

1

0

Std_logic values




Time step 3

1 1 1 X

0 0

X

1

X

Std_logic values




Time step 0

‘1’ Pull-up resistor

Std_logic values




Time step 0

0 U H U


Std_logic values




Time step 1

1 0 H 1


Std_logic values




Time step 2

0 1 0 1


Resolution(H,0) = 0

Std_logic values


• mysignal’event (mysignal changed value)• mysignal’high (highest value of mysignal’s type)• mysignal’low• Many other attributes

– http://www.cs.umbc.edu/help/VHDL/summary.html

Pre-defined VHDL attributes


• Signal: global to file• Variable: local to process

Singal vs Varible scope

My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1;

My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2;


• Signal: global to file• Variable: local to process

Singal vs Varible scope

My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1;

My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2;

Each varZ are local to their process. Completely independent


Arrays and Records• Arrays: Group signals of the same type together

• Records: Group signal of different types together

VHDL on-line tutorials:http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.htmlhttp://www.vhdl-online.de/tutorial/


Array Example (Delay Shift Register)flag_in flag_1 flag_2 flag_3 flag_out

BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1; flag_3 <= flag_2; END IF; End My_process_1; flag_out <= flag_3END;


Array Example (Delay Shift Register)flag_in flag_1 flag_20 flag_out

BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_1 <= flag_in; flag_2 <= flag_1;

flag_20 <= flag_19; END IF; End My_process_1; flag_out <= flag_20END;


Array Example (Delay Shift Register)flag_in flag_1 flag_20 flag_out

BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN flag_reg(flag_reg'high downto 0) <= flag_reg(flag_reg'high-1 downto 0) & flag_in; END IF; End My_process_1; flag_out <= flag_reg(flag_reg'high);END;

type flag_reg_array is array (DELAY-1 downto 0) of std_logic;signal flag_reg : flag_reg_array;


Array Example (Delay Shift Register)

flag_reg(flag_reg'high downto 0)<= flag_reg(flag_reg'high-1 downto 0) & flag_in;

flag_in flag(0) flag(1) flag(2) flag_out

0 0 11


1 0 0


0 0 11


Detailed in class design next Friday


HW1


Questions/Comments/Concerns

Documents

CPRE 583 Reconfigurable Computing Lecture 2: 8/26/2011 (VHDL Overview 1 )