1 - ECpE 583 (Reconfigurable Computing): Tools overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing (Tools overview) Instructor: Dr

1 - ECpE 583 (Reconfigurable Computing): Tools overview Iowa State University (Ames)

CPRE 583Reconfigurable Computing

(Tools overview)

Instructor: Dr. Phillip Jones([email protected])

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/


Outline• NX: For remotely accessing Linux machines from off campus• Very basic Linux

– Some on-line tutorials and quick reference cards• http://trinity.senecac.on.ca/cadence-tutorial/Unix.pdf• http://www.fsid.cvut.cz/cz/U201/linux.html • https://www.cfa.harvard.edu/~jbattat/computer/linuxReferenceCard.

pdf

• Creating a new ISE project

• Running simulation from within ISE

• Generating a bitfile

• Downloading a bitfile to the FPGA board (impact)


NX• NX is an application that allows you to access Linux machines from off campus.

– It is very lightweight and can be typically installed in less than 5 minutes

• You can download NX from the following links– For Windows: http://www.nomachine.com/download-client-windows.php– For Linux: http://www.nomachine.com/download-client-linux.php– For MAC OS: http://www.nomachine.com/download-client-macosx.php– For Solaris: http://www.nomachine.com/download-client-solaris.php

• After you install the NX client, make sure to install any additional fonts that are available for your platform type. If you do not some application will not display properly

• You can login to the following ISU Linux machines using your userID & password– Those listed here: http://www.it.eng.iastate.edu/remote

• Note: These machine do NOT have access to FPGA hardware– xilnx-1, xilinx-2, xilinx-3.ece.iastate.edu

• Note 1: the xilinx machines should only be used when testing a circuit using the FPGA hardware.

• Note 2: the xilinx machines are primarily for distance students to test hardware. On campus students should use a machine in Coover 2050


Very basic Linux• How to unpack a .zip or .tar.gz file

– .zip• unzip my_file.zip

– .tar.gz• gunzip my_file.gz.tar• tar -xvf my_file.tar

• How do I know where I am– pwd (tells you your current location, use this command often)

• What is in my current location– ls (list all the files and directors at this location)

• Changing directories– cd directory_name

• cd .. (takes you up one directory level)• cd ~ (takes you to your home directory)

• Making a new directory– mkdir new_directory_name


Creating a new ISE project• cd to where you want to make a directory for your project• mkdir the directory for you project• cd into the directory you made• pwd to check that you are indeed in that directory

• source ./Xilinx_12_4_src.txt– This command tells the computer where to find the tools (e.g.

ise). You must run this command any time you open a new Linux terminal. In this case, I’m assuming you are running the “source” command where your “Xilinx_12_4_src.txt” file is located.

• start ise: ise &

• Note: If you already have a project: ise project_name.xise &


Creating a new ISE project

Note you already have a project for the AND gate. Use these directions to get you going for the OR gate.





Browse to the location of the directory you created



Give your project a name



• Make your setting match this

• click Next



You project summary should look something like this. Click finish



You have no files!

Here are your choices. Very rarely do I start a VHDL file from scratch.

Lets create a new source files. Then use some existing VHDL to fill it.

For example for the ORgate. Add new source files for the testbench and OR gate. Then copy/pastefrom the given AND exampleto get you going.



Right click to pop up options



In this case we will add two source files. One for the testbench (AND_TB) to test the AND gate (AND_2bit).

Indicate you areAdding a VHDL file



You can add the port names, direction and width here. Since we are going to copy VHDL source code form somewhere else we will skip this step.

Note: This is a step for convince for when you do not have code to start from.





The tool tries to be helpful by adding some VHDL for you. I would suggest deleting this and copying from the AND gate example, until you get more comfortable with the tools.



Now let’s add a source file for the 2-bit AND gate component.









You have some files

Note: The Hierarchy window should show the strutural relationship between your files. At this point it shows AND_TB and AND_2bit at the same level



After updating your VHDL files with the appropriating “entity” and “component” names. ISE will figure out the hierarchy.

The 2-bit AND gate is a subcomponent ofAND_TB.



If you see a question mark,this could mean ISE lost track of your file when youwere editing it.

If your file is indeed in the project directory, then just tell ISE



Remind ISE where it is

Note: The “?” can also appear if you incorrectly named you entity in the VHDL




Simulating your design

Set “View” to Simulation

Select at what level you want to compile or simulate. In this case the whole design



Set simulation properties. For example how long to run for



For this case I’ve set the simulation to run for 1000 ns



Now simulate



Modelsim compiles your VHDL before simulating it. In this case it caught a syntax error.

Missing semicolon



It looks like this version of ISE does syntax checking every time you save a file. So this error could have been caught earlier.



Now that you can run simulation. You need to add signals and dividers.Right click in the “Wave” window to Insert a Divider



To add signals for the AND gate. 1) select it in “Instance”, this instance of theAND gate is called “my_dut”, 2) select the signals in the “Objects window,3) Drag and drop the signals into the “Wave” window

1 2 3



Typically you will want ALL of your signal in “Hexadecimal”. To do this 1) select all of the signals, 2) right in wave window, 3) Radix->Hexadecimal


Simulating your design: Saving wave formats

To keep from having to reformat you signals EVERY time for the same Design, save you wave format



For this project I have named the wave format HW1_3_a_AND_wave.do

Next we will look at how to tell ISE to use this wave format when it launches Modelsim.

Note: there are a number of ways of doing this, and even different versions of ISE support different methods. Often this is something you need to play around with and figure out yourself.



Contents of your project directory

Wave format youjust created

ISE file that will call your wave format

Tell ISE to only call your wave format file

“cat” prints the contents of a file

This is how I modifiedAND_TB_wave.fdo

After you make this updates, restart Modelsim from ISE to see if it worked


Simulating your design: Saving datasets

Some times you want to save the dataset (.wlf) for a simulation run. Often this is used to compare the behavior of one version of a design to another while debugging. And for this class you will save datasets so that I can review the behavior of your circuits without needed your source code.


Simulating your design: Saving datasets

1. Modelsim typically saves the current dataset as “vsim.wlf”

2. Rename it to the name you want. In this case HW1_2_a_AND_dat.wlf


Simulating your design: Loading Dataset

• To check if your dataset saved correctly open Modelsim standalone (vsim &), and load the wave dataset (.wlf), and then the associated wave format


Simulating your design: Loading Datasets

Open a wave window, then readjust/resize the windows of Modelsim



Find and open the dataset



1

2

2

4

56

Find and open the dataset



Now load the wave format (.do) associated with this dataset



Browse to find the correct wave format (.do)



Your dataset and associated waveform should appear


Simulating your design: Useful Buttons

Useful Buttons in Modelsim

Toggle between short and full signal names

Zoom in

Zoom out

Zoom full

Select mode

Zoom mode (VERY useful!!)

Jump to previous or next signal value transition (VERY useful!!)


Generating a bitfile

View can be set to simulation or Implementation. Implementation only shows those files that will go on the hardware. Simulation typically shows files that will be simulated and/or put on the hardware



Any source file that will only be simulated should have its properties set to reflect this. In this case AND_TB will be set to Simulation. And my_dut (AND_2bit) will be set to ALL (i.e. both simulation and implementation)



Any source file that will only be simulated should have its properties set to reflect this. In this case AND_TB will be set to Simulation. And my_dut (AND_2bit) will be set to ALL (i.e. both simulation and implementation)



Now when the view is switch to “Implementation” only VHDL that will be put on the hardware is shown. Also note in the “Processes” we have new options. One of which is “Generate Programming File”



One typically selects the top level component and runs “Generate Programming File” to generate a bitfile to download to the FPGA. Note we’ve switched to MP1 because the AND_2bit example does not have a user constraint file (.ucf) defined to tell the tools how to connect the design to the FPGA I/O pins



If all goes well, then after some time you should get a GREEN check next the “Generate Programming File”. And a file called <top_level>.bit, in this case MP1_top.bit, should be placed in your project directory.


Downloading a bitfile to the FPGA

Go to the directory where your bitfile is located and start impactNote: You must be on a machine that has an FPGA board connected to it.



Yes should be fine as well







Bypass until youget to the FX70



FX 70 is nowselected (GREEN)










Generating a bitfile: Fixing a locked cable• For various reasons “impact” will have an issue downloading your bitfile. This can be

caused by more than one person trying to run impact to connect to the board, or impact crashing, or power being turned off to the board.

• In the worst case one as to reboot the machine. We like to avoid this because you do not have administrative rights to reboot the machine. Though one campus students can power cycle.

• Some things to try– In impact: output -> cable reset– From the command line > impact -batch > setMode -bscan > cleancablelock > quit– From the command line > xmd > xclean_cablelock– Send me an email, and/or a “wall” message

Documents

1 - ECpE 583 (Reconfigurable Computing): Tools overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing (Tools overview) Instructor: Dr