CPRE 583 Reconfigurable Computing Lecture 18: Wed 10/26/2011 (CoreGen Overview)

1 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames)

CPRE 583Reconfigurable ComputingLecture 18: Wed 10/26/2011

(CoreGen Overview)

Instructor: Dr. Phillip Jones([email protected])

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/

http://class.ece.iastate.edu/cpre583/


•MP3: Due 11/4– IT should have resolved the issue that was causing problems

running MP3 on some of the linux-X and research-X remote machines

•Weekly Project Updates due: Friday’s (midnight)

•Will post ML507 ucf for quick reference

Announcements/Reminders


Project Grading Breakdown

• 50% Final Project Demo• 30% Final Project Report

– 20% of your project report grade will come from your 5-6 project updates. Friday’s midnight

• 20% Final Project Presentation


• FPL• FPT• FCCM• FPGA• DAC• ICCAD• Reconfig• RTSS• RTAS• ISCA

Projects Ideas: Relevant conferences• Micro• Super Computing• HPCA• IPDPS


• Teams Formed and Topic: Mon 10/10– Project idea in Power Point 3-5 slides

• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product

– Project team list: Name, Responsibility• High-level Plan/Proposal: Fri 10/14

– Power Point 5-10 slides (presentation to class Wed 10/19)• System block diagrams• High-level algorithms (if any)• Concerns

– Implementation– Conceptual

• Related research papers (if any)

Projects: Target Timeline


• Work on projects: 10/19 - 12/9– Weekly update reports

• More information on updates will be given• Presentations: Finals week

– Present / Demo what is done at this point– 15-20 minutes (depends on number of projects)

• Final write up and Software/Hardware turned in: Day of final (TBD)

Projects: Target Timeline


Initial Project Proposal Slides (5-10 slides)• Project team list: Name, Responsibility (who is project leader)

– Team size: 3-4 (5 case-by-case)• Project idea

• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product

• High-level Plan– Break project into mile stones

• Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.

– System block diagrams– High-level algorithms (if any)– Concerns

• Implementation• Conceptual

• Research papers related to you project idea


Weekly Project Updates

• The current state of your project write up– Even in the early stages of the project you

should be able to write a rough draft of the Introduction and Motivation section

• The current state of your Final Presentation– Your Initial Project proposal presentation

(Due Wed 10/19). Should make for a starting point for you Final presentation

• What things are work & not working• What roadblocks are you running into


Common Questions


Common Questions


CoreGen• A tool for generating/customizing components made

available from Xilinx.

• A wide range of component families available– Basic FPGA components (Block RAM, multipliers)– More advanced components (Clock Managers)– Math cores– Communication protocol cores– Signal processing cores


CoreGen• BlockRAM

• DCM (Digital Clock Manger)


CoreGen• BlockRAM

– 18/36-Kbit size memory block distributed throughout the FPGA

– Can be combined to create lager effective memory blocks– Important: See data sheet for the amount of memory

resources available on a give FPGA

• DCM (Digital Clock Manger)


CoreGen (Block RAM)

LUT

BlockRAM

FPGA


CoreGen (Block RAM)

Block RAM(36-Kbit)

10-bitAddress_A

36-bitData_in_A

36-bitData_out_A

36-bit

Address 1023

Address 0


CoreGen (Block RAM)

Block RAM(36-Kbit)

12-bitAddress_A

36-bitData_in_A

36-bitData_out_A

9-bit

Address 4096

Address 0

Can configure to change size of each word


CoreGen (Block RAM)

Block RAM(36-Kbit)

10-bitAddress_A

72-bitData_in_A

72-bitData_out_A

72-bit

Address 1023

Address 0

Can configure to change size of each word

Block RAM(36-Kbit)

Address 1023

Address 0


CoreGen (Block RAM)

Block RAM(36-Kbit)

10-bitAddress_A

36-bitData_in_A

36-bitData_out_A

36-bit

Address 1023

Address 0

Can be 2-ported (dual-ported)

10-bitAddress_B

36-bitData_in_B

36-bitData_out_B


CoreGen (Block RAM)• Declare and Instantiate a core generated by coregen like any other component• Example: RAM_1K_36bit

-- Declare

-- Instantiate


CoreGen (Block RAM)


CoreGen (Block RAM)


CoreGen (Block RAM)• Target the 70FX FPGA (what we use for class)


CoreGen (Block RAM)• Select type of core you want to build. In this case

a RAM block

Double-click


CoreGen (Block RAM)• Set parameters

Name


CoreGen (Block RAM)• Set parameters

Set size


CoreGen (Block RAM)


CoreGen (Block RAM)

Check Resources used

Generate Core


CoreGen• BlockRAM

• DCM (Digital Clock Manger)– Takes an input clock an multiplies by a factor (M/D)

• M is the multiplier• D is the divider

– Can generate multiple clock– Can set phase relation between clock– Can be change dynamically at run-time (Advanced usage)– Also a Phase Locked-Loop version of the DCM exists


CoreGen (DCM)

LUT

BlockRAM

FPGA

DCM


CoreGen (Block RAM)

DCMM=?D=?

CLK_in CLK_out_1xCLK_out_2x

CLK_out_1x_180deg

CLK_out_FX

FX = M/D

e.g. M= 8, D=2: thenFX = 8/2 = 4

Lock

Lock: Indicates when the outputClock of the DCM are stable and Read for use.

reset <= reset_extern OR not(Lock)


Next Class

• Design Patterns and Compute Models– Chapter 5.1, Reading 7


Questions/Comments/Concerns

• Write down– Main point of lecture

– One thing that’s still not quite clear

– If everything is clear, then give an example of how to apply something from lecture

OR

Documents

CPRE 583 Reconfigurable Computing Lecture 18: Wed 10/26/2011 (CoreGen Overview)