Chap4 Mano

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4-1

Inputs Combinational circuit Next state Storage elements

Outputs Present state

Fig. 4-1 Block Diagram of a Sequential Circuit

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-2

0 tpd tpd (a) 1 tpd (c) (b)

0

1t 2 pd (d)

1t 2 pd

1

Fig. 4-2 Logic Structures for Storing Information

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-3

Inputs Combinational circuit Flip-flops Clock pulses (a) Block diagram

Outputs

(b) Timing diagram of clock pulses Fig. 4-3 Synchronous Clocked Sequential Circuit

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-4

R (Reset)

Q

S 1 0 0 0

R 0 0 1 0 1

Q 1 1 0 0 0

Q 0 0 1 1 0 Reset state Undefined Set state

S (Set)

(a) Logic diagram

Q

1

(b) Function table

Fig. 4-4 SR Latch with NOR Gates

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-5

0.0

10ns

20ns

30ns

40ns

50ns

60ns

70ns

80ns

i S Cs i R Cs o Q Cs o Q_BFig. 4-5 Logic Simulation of SR Latch Behavior

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-6

S (Set)

Q

S 0 1 1 1

R 1 1 0 1 0

Q 1 1 0 0 1

Q 0 0 1 1 1 Reset state Undefined Set state

R (Reset)

(a) Logic diagram

Q

0

(b) Function table

Fig. 4-6 S R Latch with NAND Gates

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-7

S

C

S X 0 0 1 1

R X 0 1 0 1

Next state of Q No change No change Q = 0; Reset state Q = 1; Set state Undefined

Q

0 1

C

1 1

R

(a) Logic diagram

Q

1

(b) Function table

Fig. 4-7 SR Latch with Control Input

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-8

D

S

Q

C

(a) Logic diagram

R

Q

C 0 1 1

D X 0 1

Next state of Q No change Q = 0; Reset state Q = 1; Set state (b) Function table Fig. 4-8 D Latch

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-9

C

TG

D

TG

Fig. 4-9 D Latch with Transmission Gates

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

Q

Q

4-10

S C R

S

Y

S C

Q

C R

Y

R

Q

Fig. 4-10 SR Master-Slave Flip-Flop

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-11

0.0

50ns

100ns

150ns

200ns

iC iS iR oY oQ

Cs Cs Cs

Fig. 4-11 Logic Simulation of a Master-Slave Flip-Flop

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-12

J C K

S

S C

Q

C R

(a) Next State of Q Q 0 1 Q (b)

R

Q

J 0 0 1 1

K 0 1 0 1

Fig. 4-12 Master-Slave JK Flip-Flop 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-13

D

D

S C

Q

C

C

R

Q

Fig. 4-13 D-Type Positive Edge-Triggered Flip-Flop

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-14

J C K

D

S C

Q

C

R

Q

Fig. 4-14 Positive Edge-Triggered JK Flip-Flop

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-15

S

SR

S

D

D

R

R SR

(a) Latches

C

C

D with 1 Control

D with 1 Control

S C R

S

J C

J

C R

K

Triggered JK

C K

Triggered SR

Triggered SR

Triggered JK

(b) Master-Slave Flip-Flops

D

D

J C

J

C

C Triggered D

K

K

C

Triggered D

Triggered JK

Triggered JK

(c) Edge-Triggered Flip-Flops

Fig. 4-15 Standard Graphic Symbols for Latch and Flip-Flops 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-16

TABLE 4-1 Flip-Flop Characteristic Tables(a) JK Flip-Flop J K (b) SR Flip-Flop S R

Q (t

1)

Operation

Q (t

1)

Operation

0 0 1 1

0 1 0 1

Q(t ) 0 1 Q(t )

No change Reset Set Complement

0 0 1 1

0 1 0 1

Q(t ) 0 1 ?

No change Reset Set Undefined

(c) D Flip-Flop D

(d) T Flip-Flop T

Q (t

1)

Operation

Q (t

1)

Operation

0 1

0 1

Reset Set

0 1

Q(t) Q ( t)

No change Complement

Table 4-1 Flip-Flop Characteristic Tables

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-17

S 1J C1 1K R Q

Q

S 0 1 0 1 1 1 1

R 1 0 0 1 1 1 1

C X X X

J X X X 0 0 1 1

K X X X 0 1 0 1

Q Q 1 0 0 1 Undefined No change 0 1 1 0 Complement

(a) Graphic symbols

(b) Function table

Fig. 4-16 JK Flip-Flop with Direct Set and Reset

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-18

X B Y

J

C

A

C

Clock Fig. 4-17 Implementing Input Equations

K

A

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-19

X

D C

A A

D

Clock

C

B B

Y

Fig. 4-18 Example of a Sequential Circuit 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-20

TABLE 4-2 State Table for Circuit of Figure 4-18Present State A B Input X Next State A B Output Y

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 0 1

0 1 0 1 0 0 0 0

0 0 1 0 1 0 1 0

Table 4-2 State Table for Circuit of Figure 4-18

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-21

TABLE 4-3 Two-Dimensional State Table for the Circuit in Figure 418Next state Present state A B A X B 0 X A 1 B X Y Output 0 X Y 1

0 0 1 1

0 1 0 1

0 0 0 0

0 0 0 0

0 1 1 1

1 1 0 0

0 1 1 1

0 0 0 0

Table 4-3 Two-Dimensional State Table for the Circuit in Figure 4-18

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-22

X Y

D C

A

Z

Clock (a) Present state A 0 0 0 0 1 1 1 1 Next state A 0 1 1 0 1 0 0 1

Inputs X Y 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

Output Z 0 0 0 0 1 1 1 1

(b) State table Fig. 4-19 Logic Diagram and State Table for D A = A X Y 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-23

TABLE 4-4 State Table for Circuit with JK Flip-FlopsPresent state A B Input X Next state A B Flip-flop inputs JA KA J B KB

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 1 1 1 1 0 1

1 0 1 0 1 0 0 1

0 0 1 1 0 0 1 1

0 0 1 0 0 0 1 0

1 0 1 0 1 0 1 0

0 1 0 1 1 0 1 0

Table 4-4 State Table for Circuit with JK Flip-Flops

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-24

0/0 00 0/1 0/1

1/0 01

0/1

1/0 00,11

01,10 0/0 01,10 (b) Fig. 4-20 State Diagrams 1/1 00,11

1/0

10

1/0 (a)

11

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-25

1/0 A (a) 1/0 A B (c) 0/0 1/0 B A

1/0 B (b) 0/0 C

1/0 C

1/1 D

1/0

1/0 A B

1/0 C 1/1

0/0 D

0/0 0/0 (d) Fig. 4-21 Construction of a State Diagram 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-26

TABLE 4-5 State Table for State Diagram in Figure 4-21Next State Present State X 0 X 1 X Output Z 0 X 1

A B C D

A A D A

B C C B

0 0 0 0

0 0 0 1

Table 4-5 State Table for State Diagram in Figure 4-21

2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMP