47
© 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated. 4-1 Inputs Combinational circuit Next state Storage elements Outputs Present state Fig. 4-1 Block Diagram of a Sequential Circuit

Chap4 Mano

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Page 1: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-1

Inputs

Combinationalcircuit

Nextstate Storage

elements

Outputs

Presentstate

Fig. 4-1 Block Diagram of a Sequential Circuit

Page 2: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-2

•tpd

(b)

0 0

•tpd

(c)

1 1

tpd

(a)

•••

(d)

tpd12 tpd

12

Fig. 4-2 Logic Structures for Storing Information

Page 3: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-3

(a) Block diagram

(b) Timing diagram of clock pulses

InputsCombinational

circuit

Clock pulses

Flip-flops

Outputs

Fig. 4-3 Synchronous Clocked Sequential Circuit

Page 4: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-4

(a) Logic diagram

••

R (Reset)

S (Set)

Q

Q

(b) Function table

S

1

0

0

0

1

R

0

0

1

0

1

Q

1

1

0

0

0

Q

0

0

1

1

0

Set state

Reset state

Undefined

Fig. 4-4 SR Latch with NOR Gates

Page 5: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-5

10ns0.0 20ns 30ns 40ns 50ns 60ns 70ns

ii

oo

SRQQ_B

CsCsCs

80ns

Fig. 4-5 Logic Simulation of SR Latch Behavior

Page 6: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-6

(a) Logic diagram

•R (Reset)

S (Set)Q

Q

(b) Function table

S

0

1

1

1

0

R

1

1

0

1

0

Q

1

1

0

0

1

Q

0

0

1

1

1

Set state

Reset state

Undefined

Fig. 4-6 Latch with NAND Gates

S R

S R

Page 7: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-7

••

••

(a) Logic diagram

S

C

R

Q

Q

(b) Function table

C

0

1

1

1

1

S

X

0

0

1

1

R

X

0

1

0

1

Next state of Q

No change

No change

Q = 0; Reset state

Q = 1; Set state

Undefined

Fig. 4-7 SR Latch with Control Input

Page 8: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-8

(b) Function table

C

0

1

1

D

X

0

1

Next state of Q

No change

Q = 0; Reset state

Q = 1; Set state

(a) Logic diagram

••

••

D

C

Q

Q

S

R

Fig. 4-8 D Latch

Page 9: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-9

• •

• •

•••

••

C

D TG

TG Q

Q

Fig. 4-9 D Latch with Transmission Gates

Page 10: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-10

•• •

QY

S

C

R

QY

S

C

R

S

C

R

Fig. 4-10 SR Master-Slave Flip-Flop

Page 11: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-11

50ns0.0 100ns 150ns 200ns

ii

o

CSRY

CsCsCs

Qo

i

Fig. 4-11 Logic Simulation of a Master-Slave Flip-Flop

Page 12: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-12

Next Stateof Q

Q01Q

J0011

K0101

(b)

•••

Q

(a)

JCK

QS

C

R

S

C

R

Fig. 4-12 Master-Slave JK Flip-Flop

Page 13: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-13

•• •

• Q•

D

C

QS

C

R

D

C

Fig. 4-13 D-Type Positive Edge-Triggered Flip-Flop

Page 14: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-14

••

•• •

D

C •

S

C

R•

J

C

KQ

Q

Fig. 4-14 Positive Edge-Triggered JK Flip-Flop

Page 15: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-15

(a) Latches

(b) Master-Slave Flip-Flops

(c) Edge-Triggered Flip-Flops

SR

S

R ••

Triggered SR

S

R

C

Triggered D

D

C •

SR

S

R •

Triggered SR

S

R

C

Triggered D

D

C •

D with 1 Control

D

C •

Triggered JK

J

K

C

Triggered JK

J

K

C

D with 1 Control

D

C •

Triggered JK

J

K

C

••

Triggered JK

J

K

C

Fig. 4-15 Standard Graphic Symbols for Latch and Flip-Flops

Page 16: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-16

(a) JK Flip-Flop (b) SR Flip-Flop

J K Q (t � 1) Operation S R Q (t � 1) Operation

0 0 Q(t) No change 0 0 Q(t) No change0 1 0 Reset 0 1 0 Reset1 0 1 Set 1 0 1 Set1 1 Complement 1 1 ? Undefined

(c) D Flip-Flop (d) T Flip-Flop

D Q (t � 1) Operation T Q (t � 1) Operation

0 0 Reset 0 Q(t) No change

1 1 Set 1 Complement

Q t( )

Q t( )

TABLE 4-1Flip-Flop Characteristic Tables

Table 4-1 Flip-Flop Characteristic Tables

Page 17: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-17

(b) Function table

S0101111

R1001111

CXXX

JXXX0011

KXXX0101

Q10UndefinedNo change01Complement

Q01

10

��

��

••

S

1J

C1

1K

R

Q

Q

•(a) Graphic symbols

Fig. 4-16 JK Flip-Flop with Direct Set and Reset

Page 18: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-18

••

• •

J

C

K

A

A

XB

Y

C

Clock

Fig. 4-17 Implementing Input Equations

Page 19: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-19

D

C

A

A

D

C

B

B

X

Clock

Y

••

••

Fig. 4-18 Example of a Sequential Circuit

Page 20: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-20

TABLE 4-2State Table for Circuit of Figure 4-18

Present State Input Next State Output

A B X A B Y

00001111

00110011

01010101

00010101

01010000

00101010

Table 4-2 State Table for Circuit of Figure 4-18

Page 21: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-21

TABLE 4-3Two-Dimensional State Table for the Circuit in Figure 4-

Presentstate

Next state Output

X � 0 X � 1 X � 0 X � 1

A B A B A B Y Y

0011

0101

0000

0000

0111

1100

0111

0000

Table 4-3 Two-Dimensional State Table for the Circuit in Figure 4-18

18

Page 22: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-22

(b) State table

Z00001111

OutputA01101001

NextstateInputs

X00110011

Y01010101

A00001111

Presentstate

Clock

D

C

ZX

Y

(a)

A

Fig. 4-19 Logic Diagram and State Table for DA A X Y⊕ ⊕=

Page 23: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-23

TABLE 4-4State Table for Circuit with JK Flip-Flops

Present state Input Next state Flip-flop inputs

A B X A B JA KA JB KB

00001111

00110011

01010101

00111101

10101001

00110011

00100010

10101010

01011010

Table 4-4 State Table for Circuit with JK Flip-Flops

Page 24: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-24

(b)(a)

0/0 1/0

0/1

0/1 0/1

1/01/0

1/0

00 01

10 11

00,11

01,10

01,10

00,110/0 1/1

Fig. 4-20 State Diagrams

Page 25: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-25

(a) (b)

(c)

(d)

A B1/0

C1/0

D0/0 1/1

A B1/0

C1/0

D0/0

1/0

1/1

0/0

0/0

0/0

A B1/0

A B1/0

C1/0

Fig. 4-21 Construction of a State Diagram

Page 26: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-26

TABLE 4-5State Table for State Diagram in Figure 4-21

Present State

Next State Output Z

X � 0 X � 1 X � 0 X � 1

ABCD

AADA

BCCB

0000

0001

Table 4-5 State Table for State Diagram in Figure 4-21

Page 27: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-27

TABLE 4-6Sequence Tables for Code Converter Example

Sequences in Order of Digits Represented Sequences in Order of Common Prefixes

BCD Input Excess-3 Output BCD Input Excess-3 Output

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

0101010101

0011001100

0000111100

0000000011

1010101010

1001100110

0111100001

0000011111

0000011111

0001100011

0010100101

0100001000

1111100000

1110000011

0011011010

0100101101

Table 4-6 Sequence Tables for Code Converter Example

Page 28: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-28

(b)

0/0 or 1/1

0/1

B1=0

Init

B1=1

1/0

(a)

0/1

B1=0

Init

B1=1

1/0

B2=1B2=0

0/1 1/0

B2=X

0/1

B1=0

Init

B1=1

1/0

B2=1B2=0

0/1 1/0 0/0 or 1/1

B2=X

B3=0 B3=1

0/0 or 1/1

0/1 or 1/10/1

B1=0

Init

B1=1

1/0

B2=1B2=0

0/1 1/0 0/0 or 1/1

B2=X

B3=0 B3=1

0/0 or 1/1

0/1 or 1/1 0/1

B1=0

Init

B1=1

1/0

B2=1B2=0

0/1 1/0 0/0 or 1/1

B2=X

B3=0 B3=1

0/0 or 1/1

0/1 or 1/1

(c) (d)

0/0 or 1/10/1

1/01/0

0/1

Fig. 4-22 Construction of a State Diagram

Page 29: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-29

TABLE 4-7Table 4-5 with Names Replaced by Binary Codes

Present State

Next State Output Z

X � 0 X � 1 X � 0 X � 1

00011110

00001000

01111101

0000

0001

Table 4-7 Table 4-5 with Names Replaced by Binary Codes

Page 30: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-30

TABLE 4-8State Table for Design Example

Present State Input Next State Output

A B X A B Y

00001111

00110011

01010101

00101110

01010110

01000100

Table 4-8 State Table for Design Example

Page 31: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-31

0/0

00

1/0 010/0

11

0/0

10

0/0

1/1

1/1

1/0

Fig. 4-23 State Diagram for Design Example

Page 32: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-32

DA = AB + BX

BXA

1

10

1

B

X

A 1 1

00 01 11 10

DB = AX + BX + ABX

1

11

1

Y = BX

1

1

BXA

0

1

B

X

A

00 01 11 10BX

A

0

1

B

X

A

00 01 11 10

Fig. 4-24 Maps for Input Equations and Output Y

Page 33: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-33

••• •

•D

C

•D

C

Clock

A

A

B

B

Y

X

Fig. 4-25 Logic Diagram for Sequential Circuit with D Flip-Flops

Page 34: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-34

TABLE 4-9State Table for Second Design Example

Present State Input Next State

A B C X A B C

0000001111

0011110000

1100110011

0101010101

0001011101

0110000000

1010101010

Table 4-9 State Table for Second Design Example

Page 35: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-35

00

01

00 01CX

AB

C

X

A

11 10

11

10

B

XX

1 1

X XX X

1 11

DA = AX + BX + BC DB = ACX + ABX

XX

1

1

X XX X

DC = X

XX

1

X XXX

1

1

1

1

Fig. 4-26 Maps for Simplifying Input Equations

Page 36: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-36

TABLE 4-10Flip-Flop Excitation Tables

(a) JK Flip-Flop (b) SR Flip-Flop

Q (t ) Q (t � 1) J K Q (t ) Q (t � 1) S R

0011

0101

01XX

XX10

0011

0101

010X

X010

(c) D Flip-Flop (d) T Flip-Flop

Q (t) Q (t � 1) D Q (t) Q (t � 1) T

0011

0101

0101

0011

0101

0110

Table 4-10 Flip-Flop Excitation Tables

Page 37: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-37

TABLE 4-11State Table with JK Flip-Flop Inputs

Present State Input Next State Flip-Flop Inputs

A B X A B JA KA JB KB

00001111

00110011

01010101

00101110

01010110

0010XXXX

XXXX0001

01XX01XX

XX10XX01

Table 4-11 State Table with JK Flip-Flop Inputs

Page 38: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-38

JA = BX

BXA

X

10

1

B

X

A X X

00 01 11 10

X

JB = X

BXA

X10

1

B

X

A

X

X

00 01 11 10

X1

KA = BX

BXA

X

1

0

1

B

X

A

X X

00 01 11 10

X

BXA

X 10

1

B

X

A

X

X

00 01 11 10

X 1

KB = AX + AX = A X

Fig. 4-27 Maps for J and K Input Equations

Page 39: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-39

FJKC

FJKC

AND2

AND2

AND2

INV

XNOR2

INV

X

CLK

R

Y

A

B

Fig. 4-28 Logic Diagram for Sequential Circuit with JK Flip-Flops

Page 40: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-40

(b) Simulation results

R:

X:

A:

B:

Y:

0

0

X

X

0

0

0

X

X

0

0

1

0

0

1

0

1

0

1

0

0

0

0

1

0

0

0

1

0

0

0

1

1

0

1

0

0

1

1

0

0

1

1

1

0

0

1

0

0

1

0

0

0

1

0

0

1

1

0

1

0

0

1

1

0

1

0

0*

0*

0*

0

0

0

0

0

* These responses are asynchronous with the clock and thus do not w ait for the next positiveclock edge.

(a) Circuit test and expected results

1

0

0*

0*

0*

20ns0.0 40ns 60ns 80ns

ii

o

CLKRXA

CsCsCs

Bo

i

Yo

100ns 120ns 140ns 160ns 180ns 200ns 220ns 240ns 260ns 280ns

Fig. 4-29 Logic Simulation Verification for the Circuit in Figure 4-28

Page 41: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-41

-- Positive Edge-Triggered D Flip-Flop with Reset:-- VHDL Process Descriptionlibrary ieee;use ieee.std_logic_1164.all;entity dff is port(CLK, RESET, D : in std_logic; Q : out std_logic);end dff;

architecture pet_pr of dff is-- Implements positive edge-triggered bit state storage-- with asynchronous reset.

beginprocess (CLK, RESET) begin if (RESET = '1') then Q <= '0'; elsif (CLK'event and CLK = '1') then Q <= D; end if; end if; end process;end;

Fig. 4-30 VHDL Process Description of Positive Edge-Triggered Flip-Flop with Reset

Page 42: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-42-- Sequence Recognizer: VHDL Process Description-- (See Figure 4-21 for state diagram)library ieee;use ieee.std_logic_1164.all;entity seq_rec is port(CLK, RESET, X: in std_logic; Z: out std_logic);end seq_rec;

architecture process_3 of seq_rec is type state_type is (A, B, C, D); signal state, next_state : state_t ype;begin

-- Process 1 - state_register: implements positive edge-triggered-- state storage with asynchronous reset. state_register: process (CLK, RESET) begin if (RESET = '1') then state <= A; elsif (CLK’event and CLK = '1') then state <= next_state; end if; end if;end process;

-- Process 2 - next_state_function: implements next state as-- a function of input X and state. next_state_func: process (X, state) begin case state is when A =>

if X = '1' then next_state <= B; else next_state <= A;

end if; when B =>

if X = '1' then next_state <= C; else next_state <= A;

end if;

Fig. 4-31 VHDL Process Description of a Sequence Recognizer

Page 43: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-43-- Sequence Recognizer: VHDL Process Description (continued)

when C =>

if X = '1' then next_state <= C; else next_state <= D;

end if; when D =>

if X = '1' then next_state <= B; else next_state <= A;

end if; end case; end process;

-- Process 3 - output_function: implements output as function-- of input X and state. output_func: process (X, state) begin case state is when A =>

Z <= '0'; when B => Z <= '0'; when C => Z <= '0';

when D => if X = '1' then Z <= '1'; else Z <= '0';

end if; end case; end process;end;

Fig. 4-32 VHDL Process Description of a Sequence Recognizer (continued)

Page 44: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-44

TABLE 4-12Illustration of generation of storage in VHDL

Inputs Action

RESET = 1 CLK = 1 CLK’event

FALSE FALSE FALSE Unspecified

FALSE FALSE TRUE Unspecified

FALSE TRUE FALSE Unspecified

FALSE TRUE TRUE Q <= D

TRUE — — Q <= '0'

Table 4-12 Illustration of generation of storage in VHDL

Page 45: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-45

// Positive Edge-Triggered D Flip-Flop with Reset:// Verilog Process Description

module dff_v(CLK, RESET, D, Q); input CLK, RESET, D; output Q; reg Q;

always @(posedge CLK or posedge RESET)begin if (RESET) Q <= 0; else Q <= D;endendmodule

Fig. 4-33 Verilog Process Description of Positive Edge-Triggered Flip-Flop with Reset

Page 46: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-46// Sequence Recognizer: Verilog Process Description// (See Figure 4-21 for state diagram)module seq_rec_v(CLK, RESET, X, Z);

input CLK, RESET, X;output Z;reg [1:0] state, next_state;parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;reg Z;

// state register: implements positive edge-triggered// state storage with asynchronous reset.always @(posedge CLK or posedge RESET)begin

if (RESET == 1)state <= A;

elsestate <= next_state;

end// next state function: implements next state as funct ion// of X and statealways @(X or state) begin

case (state)A: if (X == 1)

next_state <= B;else

next_state <= A;B: if(X) next_state <= C;else next_state <= A;C: if(X) next_state <= C;else next_state <= D;D: if(X) next_state <= B;else next_state <= A;

endcaseend// output function: implements output as function// of X and statealways @(X or state)

(state) begin

caseA: Z <= 0;B: Z <= 0;C: Z <= 0;D: Z <= X ? 1 : 0;

endcaseendendmodule

Fig. 4-34 Verilog Process of a Sequence Recognizer

Page 47: Chap4 Mano

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

4-47

TABLE 4-13Illustration of generation of storage in Verilog

Inputs Action

posegdge RESET and RESET = 1 posedge CLK

FALSE FALSE Unspecified

FALSE TRUE Q <= D

TRUE FALSE Q <= 0

0TRUE TRUE Q <=

Table 4-13 Illustration of generation of storage in Verilog