3 Cmos Transistor p

W.Kucewicz VLSICirciuit Design 1

3.0CMOS Transitors

3.0CMOS Transitors


CMOS TransistorCMOS TransistorCMOS Transistor

CrossCross--section of NMOS Transistorsection of NMOS Transistor

Bulk (Body)

Source Drain

Gate

p

n+

WW

LL

G

S DB

G

S D

NMOS transistor symbol NMOS transistor symbol W W –– width of gatewidth of gateL L -- length of gatelength of gate


CMOS TransistorCMOS TransistorCMOS Transistor

CrossCross--section of PMOS Transistorsection of PMOS Transistor

Bulk (Body)

Source Drain

Gate

n

p+

G

S DB

G

S D

PMOS transistor symbol PMOS transistor symbol


Threshold VoltageThreshold Voltage


CMOS TransistorCMOSCMOS TransistorTransistor

Bulk

Source DrainGate

p

n+

- VGS +

n+

n n channelchannel


The Threshold VoltageThe Threshold VoltageThe Threshold Voltage

Bulk

Source DrainGate

p

n+

- VGS +

n+

nn--channelchannel


The Threshold VoltageThe Threshold VoltageThe Threshold Voltage

The Threshold Voltage The Threshold Voltage is function of several components: oxide thickness, is function of several components: oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosaFermi voltage, charge of impurities trapped at the surface, dosage of ge of implanted ions, etc.implanted ions, etc.

VVTT = V= VT0T0 + + γγ((√√||--22φφFF + V+ VSBSB| | -- √√||--22φφFF|)|)wherewhere

VVT0T0 is the is the threshold voltage at Vthreshold voltage at VSBSB = 0= 0 and is mostly aand is mostly a function of the manufacturing processfunction of the manufacturing process

φφFF = = -- φφTT ln(Nln(NAA /n/nii)) is the is the Fermi potentialFermi potentialφφTT = kT/q = 26mV at= kT/q = 26mV at 300K is the thermal voltage; N300K is the thermal voltage; NAA is the acceptor ion concentration;is the acceptor ion concentration; nnii ≈≈

1.5x101.5x101010 cmcm--33 at 300K is the intrinsic carrier concentration inat 300K is the intrinsic carrier concentration in pure silicon)pure silicon)

γγ = = √√(2q(2qεεsisi NNAA )/C)/Coxox is the is the bodybody--effect coefficienteffect coefficient (impact of(impact of changes in Vchanges in VSBSB ) )

εεsisi == 1.053x101.053x10--1010 F/m is the permittivity of silicon;F/m is the permittivity of silicon;

CCoxox = = εεoxox/t/toxox is the gate oxide capacitance withis the gate oxide capacitance with εεoxox == 3.5x103.5x10--1111 F/mF/m


The Body EffectThe The Body Body EffectEffect

VVBSBS(V)(V)

VVTT(V)(V)VVSBSB is the substrateis the substrate bias bias

voltage (normallyvoltage (normally positive positive for nfor n--channelchannel devices with devices with the bodythe body tied to ground)tied to ground)

A negative biasA negative bias on thesubstrate causes Vcauses VTT to to increaseincrease from 0.45V to from 0.45V to 0.85V0.85V


CharacteristicsCharacteristics


Transistor in Linear ModeTransistor in Linear ModeTransistor in Linear Mode

n+ n+

SourceDrain

Gate

p

- VGS + VDS +

ID

Bulk

- V(x) +

x

VGS > VTVVGSGS > V> VTT


Transistor in Linear ModeTransistor in Linear ModeTransistor in Linear ModeFor longFor long--channel devices (L > 0.25 micron)channel devices (L > 0.25 micron)

When VWhen VDSDS ≤≤ VVGSGS –– VVTT

IIDD = k’= k’nn W/L [(VW/L [(VGSGS –– VVTT )V)VDSDS –– VVDSDS22 /2]/2]

wherewhere

k’k’nn = = µµnn CCoxox = = µµnn εεoxox/t/toxox = is the = is the processprocess transconductance transconductance parameterparameter ((µµnn is the carrier mobilityis the carrier mobility (m(m22/Vsec))/Vsec))

kknn = k’= k’nn W/L is the W/L is the gain factorgain factor of the deviceof the device

For small VFor small VDSDS , there is a linear dependence between V, there is a linear dependence between VDSDS

and Iand IDD , hence the name , hence the name resistiveresistive or or linearlinear regionregion


Transistor in Saturation ModeTransistor in Saturation ModeTransistor in Saturation Mode

n+ n+

SourceDrain

Gate

p

- VGS +

+

ID

Bulk

VDS > VGS-VT

VGS - VT =VDS

PinchPinch--offoff


Transistor in Saturation ModeTransistor in Saturation ModeTransistor in Saturation Mode

For long channel devicesFor long channel devices

When VWhen VDSDS ≥≥ VVGSGS –– VVTT

IIDD = k’= k’nn/2 W/L [(V/2 W/L [(VGSGS –– VVTT))22]]since the voltage difference over the induced channelsince the voltage difference over the induced channel(from the (from the pinchpinch--offoff point to the source) remains fixed atpoint to the source) remains fixed atVVGSGS –– VVTT

However, the effective length of the conductive channelHowever, the effective length of the conductive channelis modulated by the applied Vis modulated by the applied VDSDS , so, so

IIDD‘ = I‘ = IDD (1 + (1 + λλVVDSDS ))

where where λλ is the is the channelchannel--length modulationlength modulation (varies with the(varies with theinverse of the channel length)inverse of the channel length)


ID Current ParametersIIDD Current ParametersCurrent Parameters

For a fixed VFor a fixed VDSDS and Vand VGSGS (> V(> VTT ), I), IDSDS is a function ofis a function of

the distance between the source and drain the distance between the source and drain –– LL

the channel width the channel width –– WW

the threshold voltage the threshold voltage –– VVTT

the thickness of the SiOthe thickness of the SiO22 –– ttoxox

the dielectric of the gate insulator (SiOthe dielectric of the gate insulator (SiO22 ) ) –– εεoxox

the carrier mobilitythe carrier mobilityfor for NMOSNMOS:: µµnn = 500 cm= 500 cm22/Vsec/Vsec

for for PMOSPMOS: : µµpp = 180 cm= 180 cm22/Vsec/Vsec


Short channel effect

Short channel effect


Short Channel EffectsShort Channel EffectsShort Channel EffectsBehavior of short channel device mainly due toBehavior of short channel device mainly due to

Velocity saturationVelocity saturation–– the velocity of the carriers the velocity of the carriers saturates due to scattering saturates due to scattering (collisions suffered by the carriers)(collisions suffered by the carriers)

-- the velocity can be express bythe velocity can be express by::

ConstantConstantvelocityvelocity

Constant mobilityConstant mobility

(slope = (slope = µµ))

For an NMOS device with L of 1For an NMOS device with L of 1µµm, only a couple of voltsm, only a couple of voltsdifference between D and S are needed to reach velocitydifference between D and S are needed to reach velocity

saturationsaturation

ξξ ≤≤ ξξc c υυ = = µµ •• ξξ/(1+ /(1+ ξξ//ξξcc))

ξξ ≥≥ ξξc c υυ = = υυSat Sat == µµ •• ξξcc/2/2


Velocity saturationVelocity saturationVelocity saturation

For short channel devicesFor short channel devices

Linear: When VLinear: When VDSDS ≤≤ VVGSGS –– VVTT

IIDD = k(V= k(VDSDS ) k’) k’nn W/L [(VW/L [(VGSGS –– VVTT )V)VDSDS –– VVDSDS22 /2]/2]

wherewhere

k(V) = 1/(1 + (V/k(V) = 1/(1 + (V/ξξcc L)) is a measure of the degree ofL)) is a measure of the degree of velocity saturationvelocity saturation

Saturation: When VSaturation: When VDSDS = V= VDSatDSat = = LL ξξcc == 2L2LυυSatSat// µµ

IIDSatDSat = = υυSatSat CCoxoxW [VW [VGSGS –– VVTT –– VVDsatDsat/2/2]]


Velocity Saturation EffectVelocity Saturation EffectVelocity Saturation EffectFor short channel devicesFor short channel devices and large enough Vand large enough VGSGS –– VVTT

VVDSatDSat < V< VGSGS –– VVTT soso the the device entersdevice enters saturation saturation before before VVDSDS reaches Vreaches VGSGS –– VVTTandand operates more often inoperates more often insaturationsaturation

IIDSatDSat has a has a linear dependencelinear dependence in function of Vin function of VGSGS so a so a reduced amount of current is delivered for a given control reduced amount of current is delivered for a given control voltagevoltage


Long Channel NMOSLong Channel Long Channel NMOSNMOS

LinearLinear SaturationSaturation

IIDD[A][A]

Qua

dQ

uad r

atic

rati

cde

pend

ence

depe

nden

ce

CutCut--offoff

VVDSDS [V][V]

NMOS transistor, 0.25um, NMOS transistor, 0.25um, LLdd = 10um= 10um, W/L = 1.5, V, W/L = 1.5, VDDDD = 2.5V, V= 2.5V, VTT = 0.4V= 0.4V


Short channel NMOS Short channel Short channel NMOS NMOS

IIDD[[AA]]

Line

arLi

near

depe

nden

cede

pend

ence

VVDSDS [[VV]]

NMOS transistor, 0.25um, NMOS transistor, 0.25um, LLdd = 0.25um= 0.25um, W/L = 1.5, V, W/L = 1.5, VDDDD = 2.5V, V= 2.5V, VTT = 0.4V= 0.4V


ID vs. VGS CharacteristicsIIDD vsvs. V. VGSGS CharacteristicsCharacteristicsLinear (shortLinear (short--channel)channel) versus quadratic (longversus quadratic (long--channel) channel)

dependence ofdependence of IIDD on Von VGSGS in saturationin saturation

VelocityVelocity saturationsaturationcauses the shortcauses the short--channel channel device todevice to saturate at saturate at substantiallysubstantially smaller smaller values of Vvalues of VDSDS resulting in resulting in a substantiala substantial drop in drop in current drivecurrent drive

(for V(for VDSDS = 2.5V,= 2.5V, W/L = 1.5)W/L = 1.5)

0 0.5 1 1.5 2 2.5VVGSGS [[VV]]

IIDD[m[mAA]]0.60.6

0.50.5

0.40.4

0.30.3

0.20.2

0.10.1

0.00.0


Short channel PMOS Short channel Short channel PMOS PMOS All polarities of all voltages and currents are reversedAll polarities of all voltages and currents are reversed

VVDSDS [[VV]]

IIDD[[AA]]

Due to the smaller Due to the smaller mobility, the maximummobility, the maximumcurrent is current is only 42%only 42% of of what is achieved by a what is achieved by a similarsimilar NMOS transistor.NMOS transistor.

PPMOS transistor, 0.25um, MOS transistor, 0.25um, LLdd = 0.25um= 0.25um, W/L = 1.5, V, W/L = 1.5, VDDDD = = --2.5V, V2.5V, VTT = = --0.4V0.4V


Subthreshold ConductanceSubthreshold ConductanceSubthreshold Conductance

Transition from ONTransition from ON to OFF to OFF is gradualis gradual (decays (decays exponentially)exponentially)

Current rollCurrent roll--off isoff is also also affected byaffected by increase in increase in temperaturetemperature

Has repercussions inHas repercussions indynamic circuits and fordynamic circuits and for power power consumptionconsumption


MOS ModelsMOS Models


MOS transistor First Order ModelMOS MOS transistor Firsttransistor First Order ModelOrder Model

The IThe Idsds current SPICE caclulation is based current SPICE caclulation is based on 6 on 6 parametersparameters: :

0.25µm0.25µmMOS channel lengthL

0.5-40µm0.5-20µmMOS channel widthW

0.4 V0.50.4 V0.5Bulk threshold parameterGAMMA (γ)

0.3V0.3VSurface potential at strong inversionPHI (ϕ)

120µA/V2300µA/V2Transconductance coefficientKP (KP)

-0.4V0.4VTheshold voltageVTO (VTO)

pMOSnMOS

TYPICAL VALUE 0.25µmDEFINITIONPARAMETER


MOS transistor First Order ModelMOS MOS transistor Firsttransistor First Order ModelOrder Model

Long channel Long channel ((1010µµmm) ) MeasuredSimulated

Simulation results ofSimulation results of nMOSnMOS transistor usingtransistor using model 1model 1

The MOS model 1 works The MOS model 1 works fine in fine in micron technologymicron technology


MOS transistor First Order ModelMOS MOS transistor Firsttransistor First Order ModelOrder ModelSimulation results ofSimulation results of nMOSnMOS transistor usingtransistor using model 1model 1

Short channel Short channel (0.(0.2525µµmm) )

Measured

Simulated

150% error150% error

The The MOS model 1 MOS model 1 is is far a far a way in submicron technologyway in submicron technology


MOS transistor Third Order ModelMOS MOS transistor Thirdtransistor Third Order ModelOrder Model

The IThe Idsds current SPICE calcurrent SPICE calcculation take into account a set ulation take into account a set of physical limitations in semiof physical limitations in semi--empirical way: empirical way:

0.07 V-10.07 V-1Substhreshold factorNSS

0.3 V-10.3 V-1Mobility degradation factorTHETA

100Km/s150Km/sMaximum drift velocityVMAX

0.01 V-10.01 V-1Saturation field factorKAPPA

0.01µm0.01µmLateral diffusion into channelLD

pMOSnMOS

TYPICAL VALUE 0.25µmDEFINITIONPARAMETER


MOS transistor Third Order ModelMOS MOS transistor Thirdtransistor Third Order ModelOrder ModelSimulation results ofSimulation results of nMOSnMOS transistor 10x0transistor 10x0..2525µµm m

using using model 3model 3

MOS level 3 includes short channel limitation effectsMOS level 3 includes short channel limitation effects


BSIM4 Berkeley MOS ModelBSIMBSIM4 4 BerkeleyBerkeley MOS ModelMOS ModelBBerkeley SShort-channel IIGFET MModel

20 Basic 20 Basic parametersparameters

60 secondary 60 secondary parametersparameters

2220 fitting 20 fitting parametersparameters


BSIM4 Berkeley MOS ModelBSIMBSIM4 4 BerkeleyBerkeley MOS ModelMOS Model

•• BSIM4 has been introduced BSIM4 has been introduced in in 20002000

•• Provides Provides a a perfect perfect continuity between lenear continuity between lenear ans ans saturated regionssaturated regions

•• Model gourousModel gourous

•• Model is becoming a serviceModel is becoming a service

Achieve good fit with static measurements using Achieve good fit with static measurements using a wide set of tricks and internal arrangementsa wide set of tricks and internal arrangements


MOS ModelMOS ModelMOS Model

BSIM4 thresholdBSIM4 threshold voltagevoltage modelmodel

DIBLNULDSCEss VtVtVtVbsKVbsKVTHOvth ∆+∆+∆+−Φ−−Φ+= .2)(.1

Short channel effects

Vth (V)

Channel length (µm)



BSIM4 BSIM4 IIDS DS modelmodel

)Lε

V(1

V)4.vt)(2V

VA(1VεεµeffLeffWeffIds0

effsat

dseff

dseff

gsteff

dseffbulkgsteff

r0

++−=

TOXE

Ids

Vgs (V)

Ids (Log)

Vds (V)


MOS transistor BSIM4 ModelMOS MOS transistor BSIM4transistor BSIM4 ModelModel

Simulation results ofSimulation results of nMOSnMOS transistor 10x0transistor 10x0..1212µµm using different modelsm using different models

Model1Model1 Model3Model3 BSIM4BSIM4



Poor fitPoor fitWidth (µm)100.0

10.0

0.0 2.5 5.0 10

1.0

7.5

The MOS model is reliable within its optimized rangeThe MOS model is reliable within its optimized range

Good fitGood fitLength (µm)


The MOS Current Source ModelThe The MOS MOS Current SourceCurrent Source ModelModel

IIDD = 0 for V= 0 for VGSGS –– VVTT ≤≤ 00

IIDD = k’ W/L [(V= k’ W/L [(VGSGS –– VVTT )V)Vminmin ––VVminmin22/2](1+/2](1+λλVVDSDS ))

for Vfor VGSGS –– VVTT ≥≥ 00

with Vwith Vminmin = min(V= min(VGSGS –– VVTT , V, VDSDS , V, VDSatDSat))

Determined by the voltages at the four terminals Determined by the voltages at the four terminals andand a set of five device parametersa set of five device parameters0.250.25µµmm


The MOS Model as a SwitchThe The MOS Model as a MOS Model as a SwitchSwitch

Resistance inverselyResistance inverselyproportional to W/L (doublingproportional to W/L (doublingW halves RW halves Ronon ))

For VFor VDDDD >>V>>VTT +V+VDSatDSat/2, R/2, Rononindependent of Vindependent of VDDDD

Once VOnce VDDDD approaches Vapproaches VTT ,,RRonon increases dramaticallyincreases dramatically

Modeled as a switch withModeled as a switch with infinite off resistance and ainfinite off resistance and afinite on resistance, Rfinite on resistance, Ronon


Switch Model of nMOS TransistorSwitchSwitch ModelModel ofof nMOSnMOS TransistorTransistor


Switch Model of nMOS TransistorSwitchSwitch ModelModel ofof nMOSnMOS TransistorTransistor

Input Logic signal

Output Logic signal

Switch

TheThe nMOSnMOS drives well drives well O but O but poorly high voltage poorly high voltage ((VVDDDD--VVTT))


Switch Model of pMOS TransistorSwitchSwitch MMoodeldel ofof pMOSpMOS TransistorTransistor


Switch Model of pMOS TransistorSwitchSwitch ModelModel ofof pMOSpMOS TransistorTransistor

Input Logic signal

Output Logic signal

Switch

TheThe pMOSpMOS drives well high voltagedrives well high voltage but but poorly poorly zero (zero (VVTT))


MOS CapacitancesMOS Capacitances


MOS Gate CapacitancesMOS MOS Gate CapacitancesGate Capacitances

Capacitance of Gate Capacitance of Gate to to ChannelChannel

CCGG = = CCGCGC + + CCGS0GS0 + + CCGD0GD0

= = CCGCGC ++ 2C2CoxoxxxddW W

CCGCGC = = CCGCBGCB+ + CCGCSGCS+ + CCGCDGCD

wherewhereCCoxox = = εεoxox//ttoxox

CCGCBGCB –– cap.cap. gategate to bodyto body

CCGCSGCS –– cap.cap. gategate to to sourcesource

CCGCDGCD –– cap.cap. gategate to to draindrain



CutCut--offoff LinearLinear SaturationSaturation



CutCut--offoff

2 CoxWL/3 + 2 CoxxdW2 CoxWL/302 CoxWL/30SaturationSaturation

CoxWL + 2 CoxxdWCoxWLCoxWL/2CoxWL/20LinearLinear

CoxWL + 2 CoxxdWCoxWL00CoxWLCutoffCutoff

CCGGCCGCGCCCGCDGCDCCGCSGCSCCGCBGCBOperationOperation

regionregion

LinearLinear SaturationSaturation


MOS Structure CapacitancesMOSMOS Structure CapacitancesStructure CapacitancesJunction CapacitancesJunction Capacitances

CCdiffdiff = = CCbottombottom + + CCside walls side walls = = CCjjLLSSW W + + CCjswjsw((2L2LSS+W)+W)


MOS Structure CapacitancesMOSMOS Structure CapacitancesStructure CapacitancesMOSFET capacitance model.MOSFET capacitance model.

CCGSGS = = CCGCSGCS + + CCGS0GS0

CCGDGD = = CCGCDGCD + + CCGD0GD0

CCGBGB = = CCGCBGCB

CCSBSB = = CCSdiffSdiff

CCDBDB = = CCDdiffDdiff


MOS Structure CapacitancesMOSMOS Structure CapacitancesStructure CapacitancesConsider an NMOS transistor with

the following parameters: tox = 6 nm, L = 0.24 µm, W = 0.36 µm, LD = LS = 0.625 µm, CO = 3 x10–10 F/m, Cj0 = 2 x10–3 F/m2 , Cjsw0 = 2.75 x10–10 F/m. Determine the zero-bias value of all

relevant capacitances.CCGBGB = εoxLW/tox = 0.5fF0.5fFCCGSGS = C= CGDGD= C0W = 0.1 0.1 fFfFCCSB SB = C= CDBDB = Cj0WLS,D+Cjsw0(W+2LD,S)=0.45fF+0.44fF= 0.89 0.89 fFfF

0.250.25µµmm


MOS Source-Drain ResistanceMOS MOS SourceSource--Drain ResistanceDrain Resistance


Other effectsOther effects


Other Submicron MOS Transistor Concerns

Other Submicron Other Submicron MOS MOS Transistor Transistor ConcernsConcerns

Velocity saturationVelocity saturation

Subthreshold conductionSubthreshold conductionTransistor is already partially conducting for voltages below VTransistor is already partially conducting for voltages below VTT

Parasitic resistancesParasitic resistances-- resistances associated with theresistances associated with the source source

and drain contactsand drain contacts




Threshold variationsThreshold variations-- In longIn long--channel devices, the threshold is a function of the lengthchannel devices, the threshold is a function of the length(for low V(for low VDSDS))-- In shortIn short--channel devices, there is a drainchannel devices, there is a drain--induced thresholdinduced thresholdbarrier lowering at the upper end of the Vbarrier lowering at the upper end of the VDSDS range (for low L)range (for low L)




LatchLatch--up.up.TheThe combination of wells and substratescombination of wells and substrates results in the formation of results in the formation of parasitic nparasitic n--pp--nn--p p structuresstructures ((thyristor thyristor !!)!!)

TTo avoid latchup, theo avoid latchup, the resistances resistances RRnwellnwell and and RRpsubspsubs should be minimized. should be minimized.

This can be achieved by providingThis can be achieved by providing numerous well and substrate contacts, numerous well and substrate contacts, placed close to the source connections of theplaced close to the source connections of the NMOS/PMOS devices.NMOS/PMOS devices.




HotHot--Carrier EffectsCarrier EffectsCause the Cause the II--V V Characteristics of an Characteristics of an NMOS NMOS transistor transistor to to degrade degrade from extensive usagefrom extensive usage


ConclusionsConclusionsConclusions

The MOS(FET) transistor is a voltage-controlled device, where the controlling gate terminal is insulated from the conducting channel by a SiO2 capacitor.

Based on the value of the gate-source voltage with respect to a threshold voltage VT , three operationregions have been identified: cut-off, linear, and saturation.

The MOS transistor, approximates a voltage-controlled switch: when the control voltage is low, the switch is nonconducting (open); for a high control voltage, a conducting channel is formed, and the switch can be considered closed. This two-state operation matches the concepts of binary digital logic.


ConclusionsConclusionsConclusionsThe continuing reduction of the device dimensions to

the submicron range has introduced some substantial deviations from the traditional long-channel MOS transistor model.

The most important one is the velocity saturation effect, which changes the dependence of the transistor current with respect to the controlling voltage fromquadratic to linear.

One particular effect that is gaining in importance is the sub-threshold conduction, which causes devices to conduct current even when the control voltage drops below the threshold.


ConclusionsConclusionsConclusions

The dynamic operation of the MOS transistor is dominated by the device capacitors. The main contributors are the gate capacitance and the capacitance formed by the depletion regions of the source and drain junctions. The minimization of thesecapacitances is the prime requirement in high-performance MOS design.

The MOS transistor is expected to dominate the digital integrated circuit scene for the next decade. Continued scaling will lead to device sizes of approximately 0.07 micron by the year 2010, and logic circuits integrating more than 1 billion transistors on a die.

Documents

3 Cmos Transistor p