02 Integrated Circuit Fundamentalsstaff.utar.edu.my/limsk/Integrated Circuit Design/02 Integrated Circuit... · Integrated Circuit Fundamentals 2.0 Introduction In this chapter, we

Chapter 2 UEEA2223/UEEG4223

Integrated Circuit Design

Integrated Circuit Fundamentals

Prepared by Dr. Lim Soo King 02 Jan 2011.

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Chapter 2 Integrated Circuit Fundamentals .................................. 17 2.0 Introduction .............................................................................................. 17 2.1 Effects of Bias Voltage ............................................................................. 17 2.2 Threshold Voltage .................................................................................... 17 2.3 MOSFET ................................................................................................... 25

2.3.1 Current-Voltage Characteristics ....................................................................... 28 2.3.2 Linear Region ..................................................................................................... 30 2.3.3 Saturation Region ............................................................................................... 30 2.3.4 Drain Conductance and Transconductance ..................................................... 32 2.3.5 Cut-off Frequency .............................................................................................. 33

2.4 Non-Ideal Effects ...................................................................................... 33 2.4.1 Sub-Threshold Conduction ............................................................................... 33 2.4.2 Channel Length Modulation ............................................................................. 35 2.4.3 Mobility Variation .............................................................................................. 36 2.4.4 Velocity Saturation ............................................................................................. 38 2.4.5 Ballistic Transport .............................................................................................. 39 2.4.6 Short-Channel Effects ........................................................................................ 40 2.4.7 Narrow-Channel Effects .................................................................................... 43 2.4.8 Drain-Induced Barrier Lowering ..................................................................... 44 2.4.9 Gate-Induced Drain Leakage ............................................................................ 45

2.5 Threshold Adjustment by Ion Implantation ......................................... 46 Exercises .......................................................................................................... 47 Bibliography ................................................................................................... 49

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Figure 2.1: The energy band diagrams of three biased voltage conditions of an ideal p-

type MOS capacitor ......................................... Error! Bookmark not defined. Figure 2.2: The energy band diagram of p-type MOS device at inversion condition ........ 21 Figure 2.3: Charge density, electric field, and electrostatic potential of MOS in inversion

mode ................................................................................................................. 22 Figure 2.4: A 2-D structure of an n-MOSFET ................................................................... 26 Figure 2.5: Channel geometry showing the flow of current IDS analysis ........................... 29 Figure 2.6: Characteristic curve of MOSFET .................................................................... 32 Figure 2.7: The ideal and experimental drain current of a MOSFET ................................ 34 Figure 2.8: Energy band diagrams of n-MOSFET showing accumulation and weak

inversion modes ............................................................................................... 35 Figure 2.9: Experimental results of electron mobility versus effective transverse electric

field at inversion .............................................................................................. 37 Figure 2.10: Comparison of drain-to-source current IDS for constant mobility condition and

electric field and saturation velocity dependence ............................................ 39 Figure 2.11: Charge sharing in short-channel threshold voltage model ............................... 41 Figure 2.12: Threshold voltage Vt versus channel length L for n-channel MOSFET .......... 42 Figure 2.13: Lightly doped drain design and corresponding doping profile LDD and non-

LDD drain ........................................................................................................ 43 Figure 2.14: Cross-section of an n-channel MOSFET showing depletion width along the

width W ............................................................................................................ 43 Figure 2.15: Potential energy of electron along channel surface and DIBL ........................ 45 Figure 2.16: Energy band diagram showing GIDL .............................................................. 45 Figure 2.17: Ion-implanted profile approximated by a step function ................................... 47

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Chapter 2

Integrated Circuit Fundamentals

2.0 Introduction In this chapter, we will discuss the theory of basic MOS which includes the effects of MOS with bias voltage and the theory of MOS transistor. The current-voltage characteristics and the threshold voltage are the main topics of discussion. The non-ideal effects of the MOS transistor due to scaled down issues are particularly discussed.

2.1 Effects of Bias Voltage There are three important regimes when the MOS capacitor is under gate voltage bias VG. These are accumulation, depletion, and inversion modes (refer to Fig. 2.1(b), Fig. 2.1(d), and Fig. 2.1(e)). The energy band diagram of a p-MOS without gate voltage bias is shown in Fig. 2.1(a). Owing to the difference in work function, and interface charge trapping, the valence band is bending toward the Fermi level at the interface, whist the conduction band is bending away from the Fermi level.

Flat-band Condition: If the negative bias voltage i.e. VG < 0 is applied to the metal with respect to the p-type semiconductor, the Fermi level of the metal is raised by an amount qVG. This would cause the reduction the bend of conduction and valence bands. Further increase of gate voltage will eventually cause the conduction and valence bands aligned with the Fermi level. This is the flat-band condition illustrated in Fig. 2.1(b).

Accumulation Mode: If the negative bias voltage i.e. VG < 0 is applied

between the metal and semiconductor, the Fermi energy level of the metal is raised by an amount qVG and the valence band of the semiconductor bends toward the Fermi level. This would cause the hole to accumulate at the surface near the oxide. The illustration is shown in Fig. 2.1(c).

Depletion Mode: If the positive bias voltage i.e. VG > 0 is applied to the

metal with respect to the p-type semiconductor, the Fermi level of the metal is lowered by an amount qVG. This would cause the valence band of the semiconductor to move away from the Fermi level of the metal. As a result, the

2 Integrated Circuit Fundamentals

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hole depletes into the bulk as such that the hole concentration near the interface falls below the concentration value in the bulk semiconductor. The illustration I shown in Fig. 2.1(d).

Inversion Mode: If the positive bias voltage i.e. VG >> 0 is further increased, eventually the conduction band of the semiconductor comes closer to the Fermi level. As a result, electron density near the interface surface starts to increase. Further increase of bias voltage would cause the conduction band of the semiconductor to bend further and crosses the Fermi level of the metal. In this condition, the density of electron increases very high and the semiconductor at the interface is inverted into n-type semiconductor. The illustration is shown in Fig. 2.1(e).

(a) No voltage bias at gate

(b) Flat-band condition


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(c) Negative voltage bias at gate – accumulation mode

(d) Positive voltage bias at gate – depletion mode


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(e) High positive voltage bias at gate - inversion mode Figure 2.1: The energy band diagrams of three biased voltage conditions of an ideal p-type

MOS capacitor When the surface potential qФS, which is potential difference of the intrinsic energy level at the interface with the intrinsic energy level in the bulk, is zero, it implies flat-band condition. For p-type MOS, when qФS is a positive, it implies depletion mode. When qФS is a positive value and larger than 2qφF then inversion occurs. When qФS is a negative value, it implies accumulation.

Similar explanation is applied to n-type MOS device. The energy band diagram of the p-type MOS device under inversion condition is shown in Fig. 2.2. Notice that inversion occurred when the surface potential is twice the Fermi potential, which follows equation (2.1).

FS q2)inv(q φ=Φ (2.1)

The Fermi potential at the bulk Fqφ is

=φ

i

AF

Nln

q

kT

n (2.2)

where NA is the acceptor doping concentration for p-type semiconductor, ni is the intrinsic carrier concentration and kT/q is the thermal voltage. Substituting equation (2.2) into equation (2.1) yields equation (2.3).


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i

AS

Nln

q

kT2)inv(

n=Φ = 2φF (2.3)

Figure 2.2: The energy band diagram of p-type MOS device at inversion condition

Besd on Fig. 2.2, the electron charge concentration n(z) is defined from

equation

Φ=kT

)z(qexpN)z( Dn , while the hole concentration p(z) is defined from

equation

Φ−=kT

)z(qexpN)z( Ap .

2.2 Threshold Voltage Threshold voltage Vt is defined as the gate voltage VG needed to induce sufficient number of charge carrier in the channel for conduction. It is the minimum applied gate voltage to induce inversion of the channel for conduction. To find the threshold voltage Vt, one needs to understand how the voltage is dropped across the MOS capacitor.

Fig. 2.3 shows the MOS structure with a voltage VG applied to its gate. Applying Kirchhoff’s voltage law, the gate voltage VG is


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VG = Vox + Vs (2.4)

Figure 2.3: Charge density, electric field, and electrostatic potential of MOS in inversion

mode Equation (2.4) is an ideal equation without considering the trapped charge within the oxide that alters the electric field and the differences in the electrical characteristics of the gate and substrate materials. Thus, a term flat-band voltage is used to account these effects, which is

Vfb = ( ) ( )oxox

SG QQC

1 +−φ−φ f (2.5)

where ( )SG φ−φ is the work function difference between gate and substrate and

is also approximately equal to ( )SG φ−φ ≈

−

2i

poly,DA NNln

q

kT

n for an n-type

polysilicon gate with p-substrate. If the poly gate is a p-type, then the work

function difference between gate and substrate is ( )SG φ−φ ≈

A

poly,A

N

Nln

q

kT . The

work function is derived from

+∆Φ=φ

i

A

n

Nln

q

kT for p-type material and

−∆Φ=φ

i

D

n

Nln

q

kT for n-type material. ∆Φ is a work function constant.


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Qf is the fixed surface charge density at the oxide-silicon interface and Qox is the trapped charge within the oxide. Re-writing equation (2.5), it becomes

Vfb = ox

ox

2i

poly,DA

C

QQ

n

NNln

q

kT +−

− f (2.6)

Equation (2.4) shall then be modified to VG = Vfb + Vox + VS (2.7) The voltage drops across oxide Vox is Vox = Eox.dox. At semiconductor-oxide interface, the surface charge QS is also equal to charge on oxide Qox, which is

εsEs = εoxEox. Qox is also equal to Qox = CoxVox = ox

oxox

d

V ε. Thus, Vox is equal to

Vox = ox

oxSS dE

εε

. Re-writing equation (2.7), it becomes

VG = Vfb + VS + εS S

ox

E

C (2.8)

For charge balancing, QS = Qox = Qdep, where depletion charge Qdep is equal to

Qdep = qNAddep. The depletion thickness ddep is equal to ddep = 2/1

A

SS

qN

V2

ε. At

inversion, VG = Vtn and VS = 2φF, ddep becomes maximum value. Thus, the maximum depletion charge Qdepmax is equal to ( ) 2/1

FASqN4 φε and surface electric

field ES is ES = S

FAS

S

maxdep Nq4Q

εφε

=ε

. Substituting expression ( ) 2/1FASqN4 φε to

replace εSES in equation (2.8), the threshold voltage equation becomes oxFASFtn C/qN42VV φε+φ+= fb (2.9)

or oxSFtn C/Q2VV +φ+= fb (2.10)

If the substrate of the MOS transistor is biased with a voltage VSUB then the threshold voltage Vtn is redefined as


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oxSUBFASFtn C/)V2(qN22VV +φε+φ+= fb (2.11)

The equation shows that the threshold voltage increases with positive VSUB bias since the surface potential is increased by a value VSUB.

Under normal processing conditions, the flat-band voltage is negative and usually yields a negative threshold voltage. For CMOS switching circuits that use a positive power rail, a positive threshold voltage is needed. This is accomplished by performing a threshold adjustment ion implant with a dose giving the number of implanted ion. This modifies the equation for the value of the threshold voltage. Implanting acceptor ions into the substrate is equivalent to introducing additional bulk charge at the surface; the implant thus induces a positive shift. The equation to follow for the ion implant adjustment is

( )ox

IoxSUBFASFtn C

qDC/V2qN22VV ±+φε+φ+= fb (2.12)

where DI is the dosage, the number implanted ion per unit area.

If there is no substrate voltage VSUB, in which sometime is called zero body bias then equation (2.11) becomes oxFASFtno C/)2(qN22VV φε+φ+= fb ,

where Vtno is the threshold voltage without the substrate voltage or body bias voltage. The equation (2.11) can be re-written in terms of Vtno and substrate voltage as

( )FSUBFOX

AStnotn 2)V2(

C

qN2VV φ−+φ

ε+= (2.13)

The term OX

AS

C

qN2ε is denoted as gamma γ, which is called bulk threshold

parameter. Equation (2.13) clearly shows that as the VSUB voltage increases the threshold voltage of the device increases. Rewriting equation (2.13), it becomes ( )FSUBFtot 2)V2(VV φ−+φγ±= (2.14)

The positive sign is used to denote n-MOS transistor and negative sign for p- MOS transistor.

In order to eliminate the effect of parasitic npn or pnp transistor of the n-MOS transistor and p-MOS transistor, the substrate of the p-MOS transistor,


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which is an n-type semiconductor, is usually biased with VDD voltage, whilst the substrate of n-MOS transistor, which is p-type semiconductor, is biased with VSS voltage i.e. zero volt.

By Kirchhoff’s voltage law, the source voltage VS and substrate voltage

VSUB relationship is –VS+VS-SUB+VSUB = 0. Equation (2.14) therefore can be written as one equation for p-MOS transistor and one for n-MOS transistor. They are ( )FSUBSSFtpotp 2)VV2(VV φ−−+φγ−= − (2.15)

( )FSUBSSFtnotn 2)VV2(VV φ−−+φγ+= − (2.16)

With substrate of p-MOS transistor biased with VDD, and source and substrate are tied together, the VSUB-S is equal to zero. Therefore, the threshold voltage of p-MOS transistor is ( )FDDFtpotp 2)V2(VV φ−+φγ−= (2.17)

With the substrate of n-MOS transistor biased with VSS and source and substrate are tied together, VS-SUB is equal to zero. Therefore, the threshold voltage of the n-MOS transistor is ( ) tnoFFtnotn V2)2(VV =φ−φγ+= (2.18) One can see that Vtp of p-MOS transistor is lower than Vtpo, whilst the Vtn of n-MOSFET is same as Vtno for the substrate biased condition mentioned above.

2.3 MOSFET A MOSFET is a MOS transistor and is essentially consist of a MOS capacitor and two diffused or implanted regions that serve as ohmic contacts to an inversion layer of free charge carriers with the semiconductor-silicon dioxide interface. Figure 2.4 illustrates the 2-D structure of an n-MOSFET.


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Figure 2.4: A 2-D structure of an n-MOSFET

Gradual Channel Approximation Model and Constant Mobility Approximation Model can be used to study the characteristics of MOSFET. The model is used to study how the conduction channel of the MOSFET is changed by the horizontal electric field generated by the drain to source voltage VDS and how the conducting channel is modulated by the vertical electric field generated by the gate to source voltage VGS. This is done by studying the drain to source current IDS versus drain to source voltage VDS characteristic for different applied gate to source voltage VGS and the transconductance of the device, which is the study of IDS current changes with the change of VGS voltage. These two studies are connected with the physical studies of the linear and saturation regions of the drain to source characteristics with various gate-to-source voltage VGS. Based on this understanding, one has to look at the two dimensional Poisson’s equation in order to understand the actual conduction mechanism of current from drain to source via the inverted channel.

There are two electric field components present in MOSFET when it is in operation. These fields can be represented by the two dimensional Poisson’s equation that has one horizontal field EX and one vertical field EY.

∂∂

∂∂

ρε

E

X

E

YX Y

S

+ = − (2.19)

Gradual Channel Approximation Model is true only if ∂∂E

XX is very small and

constant so that the Poisson’s equation can be approximated as


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∂∂

ρε

E

YY

S

≈ − (2.20)

The vertical electric potential of the conduction channel with thickness δd is

given as∂∂ δE

Y

E

dY Y= .

( )

q/kTd

VV

Y

E2ox

2tGS

2

s

oxY −

εε

=∂

∂ (2.21)

On the other hand, the variation of horizontal electric field can be approximated as

∂∂E

X

V

LX DS= 2 (2.22)

where L is the channel length and VDS is the voltage between drain and source of the MOS transistor. Here, it is assumed that the field strength changes gradually from a small value near the source to a value of the order VDS/L near the drain.

The mobilities of the electron and hole µn, µp of the MOS transistor are not the same as the mobility in the semiconductor bulk moving into the crystal lattice. Knowing the electrons or holes are moving on the surface between the semiconductor and oxide interface, their mobilities are very much depending on the surface impeding collision and ionized impurity scattering. However electrons and holes moving not closed to the interface would have a higher mobility. One also has to consider the influence of horizontal electric field resulted from drain to source voltage. Thus, there is an effective mobility µ for both hole and electron.

If the drain-to-source voltage is small, the effective channel length and

carrier charge will be more or less uniform from the source to drain and effective mobility will be essentially the same for all x values. However, one cannot ignore the effect of gate voltage on the mobility. As the gate-to-source voltage increases, the electron is moving closed to the interface. The effect of scattering will be more. Thus mobility decreases which can be observed from equation (2.23).


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)VV(1 tGS

0n −θ+

µ=µ (2.23)

where µ0 is constant and θ is the mobility degradation parameter. It can be shown that the effective mobility µn of electron is about 0.6 of the bulk mobility at (VGS – Vt) = 4V to about 0.5 for (VGS – Vt) = 13V. 2.3.1 Current-Voltage Characteristics The surface potential above threshold regime is equal to Vs(x) = ( ( ))2φF V x+ , where V(x) is the channel potential at position x along the channel in the direction from source to drain. However, from Gradual Channel Approximation Model, one can say that V(x) is equal to zero at the source side because the source and the substrate are normally shorted together and biased at VSS for an n-MOS transistor and biased at VDD for p-MOS transistor. Thus, V(x) is equal to the drain-to-source voltage VDS at the drain side. This shall mean that the gate voltage with respect to source VGS is equal to

)x(V2C

)x(QVV F

ox

sGS +φ++= fb (2.24)

Qs(x) is the surface charge, which is consisting of free electron charge Qn(x) and fixed charge acceptors in the depletion region QDEP(x). Therefore, the surface charge of is given by equation (2.25).

Qs(x) = Qn(x) + QDEP(x) (2.25)

From Constant Mobility Approximation Model, the electron mobility µn is constant and there is only drift and negligible diffusion, the drain-to-source current IDS can be calculated from current density Jn = qµnnE after ignoring the

diffusion portion qDndx

dn . Indeed drift current is only required to be considered

since the drain is reversed biased with respect to source.

Using the channel geometry of the current flow shown in Fig. 2.5, drain-to source-current IDS is made of summation of all small rectangular current elements with surface area Wdy across the channel of thickness dx for the whole channel length L.


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Figure 2.5: Channel geometry showing the flow of current IDS analysis

Thus drain to source current can be calculated equation (2.26).

∫∫∫ −=−=)x(y

0

nynyDS dyJWdydwJI

µ−

−= ∫ dy)y,x(n)y,x(qdx

)x(dVW

)x(y

0

sn

(2.26) where the second expression of equation (2.26) is equal to effective mobility of the electron µn , which is equation (2.23). Knowing that the threshold voltage is

Vt = 2φF +Vfb +ox

DEP

C

Q and nsOXFGS V)x(V)x(VV2V ++++φ= fb after inversion with

mobile ion density ns, the surface free charge density per unit area ns(x) in x-direction is

[ ] [ ]q

2)x(VN2)x(VV2V

q

C)x(n FAS

FGSox

S

φ+ε−−−φ−= fb (2.27)

Substituting equation (2.27) into IDSdx = qµnnsWdV(x) and integrating the equation with the boundary conditions for V x x( ) =0 = 0 and V x x L( ) = = VDS and x = 0 to x = L, IDS, it yields the drain to source equation (2.22).

DSDS

FGSoxn

DS V2

V2VV

L

CWI

−φ−−µ

= fb

( ) ( )[ ]

φ−φ+ε

− 2/3F

2/3FDS

ox

AS 22VC3

qN22 (2.28)


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At pinch-off condition where nS = 0 andV x x L( ) = = VDS = VDSSAT, equation (2.28) is equal zero for V(x) = VDS. Solving the quadratic equation for VDS shall yield,

ε+−φ−==

2ox

ASFGSDSSATDS C

qNV2VVV fb

ε−

+−AS

2oxGS

qN

C)VV(211 fb

(2.29) Beyond pinch-off, the drain current IDS essentially remain constant but it may be complicated by channel modulation and other effects. 2.3.2 Linear Region For very small drain to source voltage where VDS << (VGS-Vfb-2φF) and VDS F<< 2φ , equation (2.28) can be simplified to equation (2.30) and expanding the Taylor’s series for the second term.

−−

µ=

2

VV)VV(

L

CWI

2DS

DStGSoxn

DS (2.30)

This is the equation for the linear region of the MOSFET’s characteristics. 2.3.3 Saturation Region After pinch-off, IDS is assumed to be constant. It is true only if the doping concentration is low and the oxide thickness is thin. The term in equation (2.29) involving N CA ox/ 2 can be ignored and terms involving N CA ox/ can be retained. This gives the shall mean that

VDSSAT = ( ) 2/1GS

ox

ASFGS VV

C

qN22VV fbfb −

ε−φ−− (2.31)

If the voltage drops across the oxide is negligible, then at strong inversion the quantity (VGS – Vfb) is equal to VGS – Vfb ≅ 2φF. Based on the above assumption, equation (2.31) can be simplified as VDSSAT = tGS VV − (2.32) After substituting equation (2.31) into equation (2.29),


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( ){2

)VV()VV(2VV

L

CWI

2tGS

tGFGSoxn

DSSAT

−−−φ−−

µ= fb

( ) ( )[ ]

φ−φ+−ε

− 2/3F

2/3FtGS

ox

AS 22VVC3

qN22 (2.33)

Since the current does not change with VDS in this equation, further simplification can be done once pinch-off occurred. i.e. N CA ox/ is small such

that Vt ≅ Vfb + 2φF. The equation (2.33) shall be simplified to

( )

−

−−µ

=2

)VV(VV

L

CWI

2tGS2

tGSoxn

DSSAT (2.34)

= 2tGS

oxn )VV(L2

CW−

µ

This is the equation for the saturation region of the MOSFET characteristics.

A typical ideal characteristic curve of an n-MOS transistor is shown in Fig. 2.6. The curve shows three regions of the characteristic, which are the linear, saturation, and cut-off regions. The MOS transistor device will be turned off if the VGS voltage is less than the threshold voltage Vt. Note also that the dotted line is a line denotes that VDS = VGS – Vt. This is a dividing line that determines the operational condition of the MOS transistor. It is also the line showing the pinch-off the current. If the condition is VDS < VGS – Vt then the MOS transistor is in linear region or at time it is referred as triode region. This is the region that the MOS transistor device would work as a digital logic device. If the condition is such VDS > VGS – Vt then the MOS transistor is in saturation region. This is the region that the MOS transistor device works as an amplifier device.


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Figure 2.6: Characteristic curve of MOSFET

2.3.4 Drain Conductance and Transconductance Having defined the equations for linear and saturation regions of the MOS transistor, the next two important parameters of MOS transistor to be defined are the drain conductance and the transconductance. The drain conductance gD is defined as

gI

VDDS

DS V Cons tGS

==

∂∂

tan

)VV(L

CWtGS

oxn −µ

= (2.35)

Drain conductance is also equal to equation (2.30) if the term VDS is moved to the left-hand side of the equation as denominator.

The transconductance gm at saturation region is defined as

)VV(L

CW

V

Ig tGS

oxn

ttanconsVGS

DSSATm

DS

−µ=∂

∂==

(2.36)


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2.3.5 Cut-off Frequency The cut-off frequency fmax of the MOS transistor is defined as the maximum operating frequency of the MOS transistor when it is in saturation mode with the assumption that the mobility of the carrier is constant. Thus, the cut-off frequency for p-MOS transistor is defined as

fmax=g

Cm

GS2π (2.37)

where CGS is the gate to source capacitance, which estimated to be oxide capacitance per unit area multiplies by area WL. Thus, the gate-to-source capacitance is WLCC oxGS = .

fmax 2

tGSp

GS

m

L2

)VV(

C2

g

π−µ

=π

= (2.38)

For the short channel device, the cut-off frequency is assumed to depend on the transit time ttr of the carrier in the channel. Thus,

fmax L2t2

1 sat

tr π=

π= v (2.39)

where by ttr is also approximately equal to the channel length L divided by carrier saturation velocity vsat. i.e. trr = L/vsat.

2.4 Non-Ideal Effects Owing to scaling down of integration, many physical parameters of the material are no longer can be considered ideal parameters. Phenomenon such as hot electron, reaching saturation velocity, prominent interface scattering etc are dominating at small device structure. The non-ideal effects for MOS transistor to be considered in this lecture are sub-threshold, channel length modulation, mobility variation, velocity saturation, ballistic effect, short-channel effect, narrow channel effect etc. 2.4.1 Sub-Threshold Conduction The ideal current-voltage characteristic of MOS transistor shows that there is no conduction current when the gate to source voltage VGS is less than or equal to


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the threshold voltage Vt i.e. VGS ≤ Vt. However, in reality there is a sub-threshold current flows caused by the surface of semiconductor develops into a lightly doped n-type material joining the n-type drain and source for the case of n- MOS transistor. Owing to the way that drain is biased, there is also a small amount of drift current is being registered before the channel is switched on. The ideal and experimental current characteristics of MOS transistor are shown in Fig. 2.7.

Figure 2.7: The ideal and experimental drain current of a MOSFET

Upon the gate to source bias and when the surface potential ΦS is less than 2φF, the Fermi level is closer to conduction band. Thus, it causes the p-type material near the oxide interface turns into lightly doped n-type. This would expect some conduction between n+-source and drain through this inverted n-type substrate. The condition for φF <ΦS < 2φF is known as weak inversion.

The energy band diagrams of an n-MOS transistor during accumulation and weak inversion are shown in Fig. 2.8.

The sub-threshold current IDS-Sub is equal to

( )

−−

η−

µ=− kT

qVexp1

kT

VVqexp

q

kT

L

WCI DStGS

2

oxnSubDS (2.40)

where µn is the electron mobility, Cox is the gate capacitance per unit area, W is the channel width, L is the channel length, Vt is the threshold voltage of the


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MOS, and η is the sub-threshold parameter related to the sub-threshold swing S which is the gate voltage change needed to raise the sub-threshold current by one decade following the relation S = ηVt(ln 10). The sub-threshold parameter η is given by

η = +1C

CD

ox

(2.41)

where CD is the depletion channel capacitance per unit area.

Figure 2.8: Energy band diagrams of n-MOSFET showing accumulation and weak

inversion modes 2.4.2 Channel Length Modulation As the drain-to-source voltage VDS exceeds VDSSAT, the drain to source current IDS is independent of the VDS. In reality there is a shortening of the channel ∆L, which is supported by the excess voltage drain-to-source voltage ∆VDS = (VDS – VDSSAT).

The depletion width at drain WD is governed by equation

A

DSFSD qN

]V2[2W

+φε= . The incremental change in depletion length, which is also

equal to ∆L, is equal to


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[ ]DSSATFDSDSSATFA

S V2VV2qN

2L +φ−∆++φ

ε=∆ (2.42)

The drain current I DS

' with channel modulation taken in account shall be what is shown in equation (2.38).

IL

L LIDS DSSAT

' =−

∆ (2.43)

The result shows that there is an increase of output conductance of the device as the drain-to-source VDS exceeded the saturated drain-to-source voltage VDSSAT. 2.4.3 Mobility Variation In reality there are two factors influencing the mobility of carrier in MOS transistor. The increase of gate voltage forces the carrier to move closer to the interface whereby the roughness and oxide impurities cause higher degree of scattering on the carrier due to coulumbic interaction. The effective mobility of the carrier decreases as its drift velocity Vdrift approaches saturation limit. Figure 2.7 shows the results of deviation of ideal drain current characteristic due these effects.

For a small electric field, the mobility is constant with respect to drift velocity. At high electric field, the mobility is no longer constant and will be degraded until it reaches zero when the drift velocity of the carrier reaches its saturation velocity.

The relationship between the inversion charge mobility and transverse

electric field is usually measured experimentally. The effective transverse electric field Eeff for electron is defined as

E Q QeffS

DEP n= +

1 1

2ε (2.44)

However, for hole with mobile charge Qp, equation (2.44) has to be modified slightly to

E Q QeffS

DEP p= +

1 1

3ε (2.45)


- 37 -

The effective inversion mobility can be determined from the channel conductance as a function of gate voltage. The effective inversion mobility µeff is defined as

3/1

nDEP0S

0

3/1

0

eff0eff Q

m

1|Q|

E

1

E

E−−

+ε

µ=

µ=µ (2.46)

where µ0 and E0 are experimentally determined constants, and m is either 2 or 3. Based on equation (2.41), the experimentally results of electron mobility versus effective transverse electric field at inversion is shown in Fig. 2.9.

The linear drain-to-source current equation, which is equation (2.30)

−−

µ=

2

VV)VV(

L

CWI

2DS

DStGSoxn

DS , should then be modified to equation (2.47)

by adding in the scattering effect of mobility and transverse electric effect, which are equation (2.23) and (2.46) respectively.

[ ]

−−

⋅

−θ+µ

=−

2

VV)VV(

E

E

)VV(1L

CWI

2DS

DStGS

3/1

o

eff

tGS

oxoDS (2.47)

Figure 2.9: Experimental results of electron mobility versus effective transverse electric

field at inversion


- 38 -

Similarly, the saturation current equation shown in equation (2.34) can be modified to include the scattering effect of mobility and transverse electric effect.

2.4.4 Velocity Saturation In the ideal current-voltage analysis, the mobility of the electron is assumed to be constant which shall mean that the drift velocity increases without limit as the electric field increases. However, the velocity saturates with increase electric field. For short channel device, velocity saturation becomes more prominent since the horizontal electric field is generally large.

The current saturation for ideal current-voltage relationship occurred when inversion charge density ns at drain is equal zero. i.e. when VDS = VGS – Vt. For n-MOS transistor, the velocity saturation can cause the current saturation condition if the electric field is approximately 1.0x104Vcm-1. For drain-to-source voltage VDS of 5V and channel length L equals to 1.0µm, the average electric field shall be 1.0x105Vcm-1. This shall mean that saturation velocity is likely to occur for short channel device. The modified saturation current IDSSAT shall be

IDSSAT = WCox (VGS – Vt)vsat (2.48)

where the saturation velocity vsat is approximately 1.0x107cms-1 for electron in bulk and Cox is the oxide capacitance per cm2 and W is the gate width. Saturation velocity will decrease as gate voltage increases due to increase scattering effect. The saturation current IDSSAT is smaller for velocity saturation condition and it is having linear relation as shown in equation (2.48) rather square law dependence as shown in equation (2.34). Figure 2.10 shows the comparison of drain-to-source current IDS for constant mobility and electric field conditions and saturation velocity dependence.

There are several models of mobility versus electric field. One of commonly use equation is

µµ

µ=

+

eff

eff

sat

E1

2 1 2

v

/ (2.49)


- 39 -

From equation (2.48), the transconductance curve gm is found to be

gI

VWCm

DSSAT

GSox sat= =

∂∂

v . This shall mean that transconductance is independent of

gate-to-source VGS and drain-to-source VDS voltages.

From equation (2.38), the cutoff frequency fmax for constant mobility condition shall be given by equation (2.50), which is equation (2.39).

fv v

max = = =g

C

WC

C WL Lm

GS

ox sat

ox

sat

2 2 2π π π (2.50)

Figure 2.10: Comparison of drain-to-source current IDS for constant mobility and electric

field conditions and saturation velocity dependence

2.4.5 Ballistic Transport The average drift velocity vdrift is a function of mean time between collisions or mean distance l between scattering events. For long channel device, the channel L is greater than l. As the channel length L decreases, the average distance between collision l is comparable to channel length L. If channel length L is reduced to such that L < l, then large fraction of carrier could travel from source to drain without experience scattering event. This motion of carrier is called ballistic event. Ballistic transport means carriers travel faster than average drift


- 40 -

velocity or saturation velocity. This would lead to very fast device. Ballistic transport will occur for sub-micron device that has less than 1.0µm channel length. As the channel length of MOS transistor technology continues to shrink toward 0.1µm or less value, the ballistic transport phenomenon will become more important. 2.4.6 Short-Channel Effects As the channel length of the device decreases, the fraction of charge in the channel controlled by the gate decreases. The reverse bias depletion region at the drain side extends further into the channel area and the gate will control even less bulk charge.

As the channel becomes very short, the electric field across the channel is high. The carrier becomes "hot" because the kinetic energy of the carrier is very high. This can cause tunneling of the carrier into oxide layer that produces gate current because the breakdown of covalent bonds.

Radiation effect is more severe for short channel device than the long

channel device. A small change in the oxide charge or interface-state can cause serious effect especially from γ-ray radiation, which generates a burst of charges. This definitely will cause "soft error" for memory device.

The threshold voltage Vt of the device follows equation (2.10), which is

oxFASFt C/eN42VV φε+φ+= fb −Q

CSS

ox

when charge oxide QSS is assumed present.

The short-channel effect on the threshold voltage can be determined from the short-channel threshold model shown in Fig. 2.11.

rj is the diffused junction depth. The assumption for lateral diffused

distance under the gate is same as vertical diffused distance. This assumption is not quite true for ion-implanted drain and source. The analysis is based on trapezoidal region under the gate controlled by the gate.


- 41 -

Figure 2.11: Charge sharing in short-channel threshold voltage model

As it is shown in Fig. 2.3, the potential difference across the bulk depletion region is 2φF at threshold inversion point. The built-in potential barrier height of source and drain is approximately 2φF. This implies that the depletion width of the three regions are essential equal which is xs ≈ xd ≈ xDEP = xDEP. Using the geometrical approximation, the average bulk charge per unit area Qb

' in the trapezoid is

+=L2

LLqNQ DEPA

b x (2.51)

L L

L

+

'

2 can be shown, as equals to 1 1

21− + −

r

L rj DEP

j

x then equation (2.51)

shall be DEPA b qNQ x= 1 1

21− + −

r

L rj DEP

j

x. Qb

' shall be equal to FASqN4 φε .

Since QDEP is equal to qNAxDEP, for non short-channel effect, therefore, the change of threshold voltage ∆Vt caused by short-channel effect is

ox

DEPA

ox

DEP,b

t C

qN

C

QQV

x−=−=∆r

L rj DEP

j

12

1+ −

x (2.52)

Essentially it shows that the threshold voltage is lower by a value shown in equation (2.52) for short-channel device.

Short-channel effect for n-MOS transistor becomes more significant when the channel length L is less than 2.0µm as illustrated in Fig. 2.12.


- 42 -

As mentioned earlier, when channel becomes very short, the electric field

across the channel may be high because the applied voltage may not be scaled down according. As the result, the carrier becomes "hot" because the kinetic energy of the carrier is very high. This can cause tunneling of carrier into oxide and near punchthrough condition especially with the presence of parasitic bipolar device.

Figure 2.12: Threshold voltage Vt versus channel length L for n-MOS transistor

To overcome this problem is to alter the doping profile of the drain contact by Lightly Doped Drain LDD design approach. By introducing a lightly doped region, it reduces the peak electric field in the depletion region at drain and hence reduces the breakdown effect. The magnitude of the electric field at oxide-semiconductor interface in the LDD structure is less than in the conventional structure. Figure 2.13 shows the design and the corresponding doping profile LDD and non-LDD drain.

(a) Lightly doped design


- 43 -

(b) LDD doping profile

Figure 2.13: Lightly doped drain design and corresponding doping profile LDD and non- LDD drain

2.4.7 Narrow-Channel Effects Figure 2.14 shows the cross section of an n-MOS transistor showing the depletion region along the width W of the device.

Figure 2.14: Cross-section of an n-MOS transistor showing depletion width along the width There is an additional depletion region at each ends of channel width. The charges in the region are controlled by gate voltage, which is not included in earlier derivation of the ideal threshold voltage. If neglecting short-channel effects, the gate-controlled bulk channel can be written as QB = QB0 + ∆QB (2.53) where QB is the total bulk charge, QB0 is the ideal bulk charge and ∆QB is the additional bulk charge. For uniformly doped p-type semiconductor, the total bulk charge QB is QB = ( )DEPDEPADEPA LqNWLqN xxx ξ+ (2.54)


- 44 -

or

QB =

ξ+Z

1WLqN DEPDEPA

xx (2.55)

where ξπ

=2

for semi-circle end, a fitting parameter for lateral depletion width.

Thus, the change in threshold voltage ∆Vt is

ξ=∆WC

qNV DEP

ox

DEPAt

xx (2.56)

2.4.8 Drain-Induced Barrier Lowering If a short-channel length MOS transistor is not scaled properly, such as reducing channel length with reducing the applied drain-to-source voltage, the source/drain junctions are too deep or the channel doping concentration is too low, there can have electrostatic interaction between drain and source, which is known as Drain-Induced Barrier Lowering DIBL. This leads to punchtrough leakage or breakdown between source and drain. Figure 2.15 shows the potential energy of electron along the channel surface and DIBL. Once the source-channel barrier is lower by DIBL, there can be significant leakage current with gate being unable to shut off.

To overcome DIBL, the source and drain junctions must be made sufficiently shallow which is scaled properly as the channel length reduced. Secondly the channel doping concentration must be sufficiently high to prevent the drain from being able to control the source junction.

For short-channel MOS transistor, the DIBL is related to channel length modulation of pinch-off region ∆L. Therefore, the characteristic of saturation drain-to-source current follows equation (2.43).


- 45 -

Figure 2.15: Potential energy of electron along channel surface and DIBL

2.4.9 Gate-Induced Drain Leakage As you can see in Fig. 2.7, there is sub-threshold current when the gate voltage is below the threshold voltage Vt. As the gate voltage goes more negative, the sub-threshold current is indeed increasing. This on-state leakage is known as gate-induced drain leakage GIDL. The gate voltage is getting more negative is equivalent to the gate voltage is set at zero volt and voltage at drain is getting more positive. The drain doping concentration is high and a narrow depletion is normally formed. If the band bending is more than the band-gap EG across the narrow depletion region, then a condition of band-to-band tunneling of electron from valence band to conduction is exist. The electron flows to drain as gate-induced drain leakage GIDL current. Fig. 2.16 shows the energy band diagram of n+

poly SiO2 n+ -drain.

Figure 2.16: Energy band diagram showing GIDL


- 46 -

2.5 Threshold Adjustment by Ion Implantation As you know the threshold voltage of an MOS transistor is dependent on fixed oxide, metal-semiconductor work function difference, oxide thickness, and semiconductor doping concentration. The results of fabrication based on dependent variables may not be acceptable. The threshold voltage of the device needs to be adjusted which can be done by ion implantation. Ion implantation would adjust the doping concentration of substrate near the oxide. Ion implantation can precisely control the amount of dopant to be added. Adding acceptor ion into either p- or n-substrate would shift the threshold voltage more positive because the depletion region is thicker. Likewise, adding donor ion would shift threshold voltage more negative because the depletion region is thinner.

As the first approximation, if DI acceptor per cm2 of ion is to be implanted into p-type substrate, the shift of threshold voltage ∆Vt is

ox

It C

qDV =∆ (2.57)

If the ion implantation is a step junction, the threshold voltage after a step implant for case where xDEP > xi is

ox

iAStot C

x)NN(qVV

−+= (2.58)

whereby DI = (NS - NA)xi. NS is the implant doping concentration; xI is the induced depletion thickness by implanted ion on pre-implant depletion thickness xDEP. Vto is the pre-implant threshold voltage, which follows equation

oxFASFtno C/)2(qN22VV φε+φ+= fb . Figure 2.17 illustrates the ion-implanted

profile approximated by a step function.


- 47 -

Figure 2.17: Ion-implanted profile approximated by a step function

Exercises 2.1. Find the work function difference for an n-type polysilicon gate n-MOS

transistor that has poly gate doping concentration and substrate doping concentration of 1.5x1019cm-3 and 1.0x1015cm-3 respectively.

2.2. The work function difference between Al-SiO2-p-type silicon MOS

transistor is -0.15V given concentration of p-type is 1.0x1012cm-3 and the work function of Al is 4.28V. Calculate the value of the work function constant ∆Φ for the device.

2.3. If the thickness of the oxide for the Al-SiO2-p-type silicon MOS is 600A0

, the flat-band potential is -0.87V, and the concentration of p-type semiconductor is 5.0x1016cm-3, calculate the threshold voltage Vt of the MOS.

2.4. A MOS capacitor has an aluminum gate and p-type substrate with doping

concentration 5.0x1016cm-3. Its oxide thickness is 450Ao

and cross sectional area is 1x10-2cm2. Calculate the oxide capacitance.

2.5. Consider an n-MOS transistor with gate width W = 10µm and gate length

L = 1.5µm and oxide capacitance Cox = 10-7F/cm2. In the linear region for a fixed VDS = 0.1V, the drain current is found to be 40µA for VGS = 1.5V and 80µA for VGS = 2.5V respectively. Calculate the threshold voltage Vt and mobility µn of this MOS transistor.


- 48 -

2.6. An n-MOS transistor has effective mobility of 750cm2/V-s, channel length L of 1.0x10-4cm, threshold voltage Vt of 1.5V, and gate voltage VG 3.0V for a small signal application. Calculate the cut-off frequency using constant mobility model and the case of having short-channel effect where the saturation velocity of the carrier is 107cms-1.

2.7. Consider an n-MOS transistor has channel width W = 8µm and channel

length L = 0.5µm and is made of process where process transconductance K = 180µA/V2, Vtn = 0.7V and VDD = 3.3V. Calculate the linear drain to source resistance.

2.8. Consider an n-MOS transistor that is characterized by oxide thickness

80o

A , substrate doping concentration 1.2x1015cm-3, doping concentration of n-type poly gate 1x1019cm-3, fixed oxide 1x1011x1.602x10-19Ccm-2 and receiving acceptor ion implant dosage of 2x1012cm-2 for threshold adjustment.

(i) Calculate the threshold voltage of this MOS transistor at room

temperature. (ii) If the substrate of this MOS transistor is biased with 1.0V, what is

the ion implant dosage required to maintain same threshold voltage? 2.9. An n-MOS transistor has the following information: Oxide thickness dox

= 1000

A , substrate doping concentration NA = 8x1014cm-3, zero bias substrate threshold voltage Vtno = 0.6V and mobility µn = 580cm2/V-s. Calculate the process transconductance K and bulk-threshold parameter γ of the device.


- 49 -

Bibliography 1. John P. Uyemura, “Chip Design for Submicron VLSI: CMOS Layout and

Simulation”, Thomson, 2006. 2. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John

Wiley & Sons, Inc. 2002. 3. Etienne Sicard and Sonia Delmas Bendhia, “Basics of CMOS Cell

Design”, TATA McGraw Hill, 2006. 4. Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits

Analysis and Design”, third edition, McGraw Hill, 2005. 5. Jasprit Singh, “Semiconductor Device”, McGraw Hill Inc. 1994. 6. Robert F. Pierret, “Semiconductor Fundamentals”, Volume I Modular

Series on Solid State Devices, second edition, Addison-Wesley Publishing Co. 1989.

7. John P. Uyemura, “CMOS Logic Circuit Design”, Kluwer Academic Publishers, 2002.

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02 Integrated Circuit Fundamentalsstaff.utar.edu.my/limsk/Integrated Circuit Design/02 Integrated Circuit... · Integrated Circuit Fundamentals 2.0 Introduction In this chapter, we