CMOSCMOS INTEGRATED INTEGRATED CIRCUIT DESIGN TECHNIQUEStsiatouhas/CCD/Section_4-2p.pdf · 1 CMOSCMOS INTEGRATED INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina CMOS Logic

1

CMOSCMOS INTEGRATED CIRCUIT DESIGN TECHNIQUESINTEGRATED CIRCUIT DESIGN TECHNIQUES

University of University of IoanninaIoannina

CMOSCMOSLogic FamiliesLogic Families

CMOSCMOSLogic FamiliesLogic Families

Y. Tsiatouhas

Dept. of Computer Science and EngineeringDept. of Computer Science and Engineering

CMOS Integrated Circuit Design TechniquesCMOS Integrated Circuit Design Techniques

OverviewOverview

1.1. NonNon‐‐clocked CMOS logic familiesclocked CMOS logic families

2.2. Clocked CMOS logic familiesClocked CMOS logic families

VLSI Systemsand Computer Architecture Lab

2

NonNon‐‐Clocked CMOS Logic FamiliesClocked CMOS Logic Families

CMOS Logic Families 3

Full or Static Full or Static CMOSCMOS LogicLogic

))D)CBA((F

A

VDD

Full CMOS

Strengths Weaknesses

Low Static Power Overlap Currents

Good Yield/Defect Tolerance

High Fan‐Out LoadsD

A

B

C

D

F


Full‐CMOS Tolerance

High Test Coverage High Noise Generation

High Noise Immunity

Α Β C

Gnd

3

nMOSnMOS andand PseudoPseudo‐‐nMOSnMOS LogicLogic

))D)CBA((F VDD VDD

nMOS Pseudo‐nMOS

D

F

D

F

Gnd


Α Β C

Gnd

Α Β C

Gnd

Differential Differential CascCascοοde Voltage Switch Logic Ide Voltage Switch Logic I

DCVSDCVS

))D)CBA((FVDD VDD ))D)CBA((F

IN

DD

F F

nMOSff l

IN

D

DD

F

A

B D

F


Gnd

DifferentialNetwork

Α Β C

Gnd

C

4

DCVSDCVS Logic Logic IIII

Strengths WeaknessesStrengths Weaknesses

Good Logic Density Dual Rail Wiring

Complementary Output Availability

pMOS Strength vsLatching Hysterisis

High ReliabilityHigh Device Count

(depending on applic.)


High Noise Immunity

Differential SplitDifferential Split‐‐Level (Level (DSL) DSL) Logic Logic II

VDD

A

FF

nMOS A

VREF VREFN1 N2


tnDD

REF V2

VV Gnd

DifferentialNetwork

5

DSL DSL Logic Logic IIII


Low Switching Power Dissipation

High Static Power Dissipation

Complementary Output Availability

VREF Generation

High Reliability High Device Count


Pass Gate LogicPass Gate Logic

F G

Risk: possible violationof CMOS principles

Path 1

Path 2

A

B

C

D

E

Excessive fan out requirements

Noise PropagationBody effect

DC powerdissipation


Path n

Excessive fan‐out requirements by the driving structure

Limited fan‐out capability by the pass gate structure

6

Keeper Based Pass Gate LogicKeeper Based Pass Gate Logic

E GK

A

C D

F

VDD

Keeper


B

Full Full CMOSCMOS Transmission Gate Logic Transmission Gate Logic

AFull CMOS

B F

Transmission Gate

S h W k



High Speed Body Effect

Low Area Limited Logic Depth

Low Power

7

DCVSDCVS Logic with Pass GatesLogic with Pass Gates


VDD


Full SwingLimited Logic

Depth

Noise ImmunityLimited Load

Drive

Area‐Power Reduction

Body EffectΒ

F

B

FXOR XNOR


No Floating Nodes

Α A A A

Complementary Pass Gate Logic (CPL)Complementary Pass Gate Logic (CPL)

VVDD

F

B

F

XORXNOR


High Speed Operation

Α

Β

A A A

8

SwingSwing‐‐Restored Pass Gate Logic (Restored Pass Gate Logic (SRPLSRPL) I) I

VDD

FF

XORXNOR

Gnd


Α

Β

A

B

A A

SRPLSRPL Logic Logic IIII


Low Static Power Dissipation

Limited Output Load

Process Tolerance Overlapping Current

Sense Amplifier Speed Performance

Drive Strength vsPerformance


High Logic Depth

9

PushPush‐‐Pull Pass Transistor Logic (Pull Pass Transistor Logic (PPLPPL))

V FF


L PpMOS Logic

VDD

B

AND

NAND

Gnd


Low PowerpMOS Logic

Implementation

Hysterisis Elimination

Limited Sequential Usage

Limited Fun‐Out CapabilityΑ

Β

B AB

Double Pass Transistor Logic (DPL) IDouble Pass Transistor Logic (DPL) I

FF ANDNAND

Β

A

A


ΑVDDB

B

A B Gnd GndVDD

10

DPL DPL Logic Logic IIII


High Speed Operation Limited Logic Depth

No Vth Drops Limited Load Capability

Redundant Device Structure


ClockedClocked CMOS Logic FamiliesCMOS Logic Families


11

Dynamic Dynamic CMOSCMOS Logic Logic II

VDD VDD

Inputs

F

Φ

nMOSNetwork Α Β C

D

F

Φ


)D)CBA((F Gnd Gnd

Dynamic Dynamic CMOSCMOS Logic Logic IIII

Φ

precharge evaluationVDD VDD

F1

Race conditions

IN1

F1

Φ

nMOSNetwork

F2

nMOSnetwork


Erroneous logic state

F2

t

Gnd Gnd

12

4 Phase Dynamic 4 Phase Dynamic CMOSCMOS Logic Logic ΙΙ

Φ1

prechargeVDD

Φ2

Φ1evaluation

memory memory

Inputs

F

Φ1

nMOSNetwork

Φ2

Φ2


F

Gnd

4 Phase Dynamic 4 Phase Dynamic CMOSCMOS Logic Logic ΙΙII

VDD

Φ12 Φ23 Φ1

Gnd

nMOSδικτύωμα

Φ23

Φ12

VDD

Φ34 Φ41

VDD

Φ41


Φ12

Φ12

VDD

Φ23


Φ34

Φ34

Φ2

Φ3

Φ4

Φ12


Gnd

Φ34


Φ41

Φ41

Φ34

Gnd

Φ41

Gnd

Φ23

Φ23

Φ34

Φ41

13

ClockedClocked CMOSCMOS (C(C22MOS) MOS) LogicLogic

Φ

Active Tri‐StateVDD

A

Φ

A F

Φ

Φ


F

Gnd

DominoDomino CMOSCMOS Logic Logic II

VDD VDD

Φ

Inputs

F

Φ

nMOSδικτύωμα Α Β C

D

F

Φ


D)CBA(F

Optional transistor.Low power oriented design.This transistor is mandatory only at the first logic stage,which is driven by the

primary inputs!Gnd Gnd

14

DominoDomino CMOSCMOS Logic Logic IIII

precharge evaluationVDD

Α

Φ

Α

F

Φ


F

Gnd

DominoDomino CMOSCMOS Logic Logic IIIIII

Φ

prechargeevaluation

VDD VDD

F1

Φ

IN

F1

Φ

nMOSNetwork

F2

nMOSNetwork


F2

tGnd Gnd

15

DominoDomino CMOSCMOS Logic Logic IVIV


Logic DensityLogically Incomplete

Family

High Performance Low Noise Immunity

Very Low Noise Generation

High Switch Factor


Non‐Glitching OutputLimited Fail

Diagnosability

Domino and Charge SharingDomino and Charge Sharing

A=B=C=0

V V V

prechargeevaluationVDD

Φ

0 0 0

0 1

F΄VDD VDD‐V

F΄

Φ

Α Β C

D

F

Φ

C1

C Gnd


F

NoisetGnd

C2

16

Charge SharingCharge Sharing

S = ‘0’ then:

Q C V d Q C VS

VsVb

Cs

Gnd

Cb

Gnd

S Qb = Cb.Vb and Qs = Cs.Vs

Qtotal = Qb + Qs = Cb.Vb + Cs.Vs

S ‘1’ h di h h i i i l


S = ‘1’, then according to the charge retention principle:

sb

ssbb

total

totalR

CC

VCVC

C

QV

Ctotal = Cb + Cs

Enhanced Domino LogicEnhanced Domino Logic

Use of keepersVDD

Weak pMOSVDD

Weak pMOS

Inputs

F

Φ

nMOSNetwork

Gnd

Inputs

F

Φ

nMOSNetwork


Gnd Gnd

17

Multiple Multiple PrechargingPrecharging DominoDomino LogicLogic

VDD

Φ

C

Α Β C

D

F

Φ

C1

Gnd


Gnd

C2

Multiple Output Multiple Output DominoDomino Logic Logic II

prechargeevaluationVDD

Φ D)CBA(F

F

Φ

A=1 ή

D=0Α Β C

D

F

Φ

G

D)CBA(F

CBAG


G

A=1 ή B=1

ή C=1tGnd

18

Multiple Output Multiple Output DominoDomino Logic Logic IIII


Active Power ReductionLogically Incomplete

Family

Area, Device Count Reduction

Large Evaluate Capacitance

Low Noise Generation High Switching Factor


High Diagnosability

Compound Compound DominoDomino LogicLogic

VDD VDDStaticCMOS

Gate

Inputs

F

Φ

nMOSNetwork

1

Inputs

Φ

nMOSNetwork

2


Gnd Gnd

19

ClockClock‐‐lessless DominoDomino Logic Compatible StyleLogic Compatible Style

VDD

EΦ

VΑ

Β

Gnd

Φ

VDD

FΦ

Φ

VDD

C

HΦ

Domino AND

Gnd

G

FPDL AND


Gnd

ΦD

Gnd

ΦG F

Haniotakis et.al., ICECS, 1999

ClockClock‐‐Delayed Domino (Delayed Domino (CDDCDD) Logic ) Logic

VDD


Logically Complete Family

Timing Complexity

Reduced Clock Overhead

Low Noise Immunity

High Process Sensitivity

Inputs

F

Φ1

nMOSNetwork


Sensitivity

Limited Fail Diagnosability

Additional Clock PathGnd

Gnd

VDDΦ2

20

SelfSelf‐‐Resetting Domino (Resetting Domino (SRDSRD) Logic ) Logic

VDD ProperW/LStrengths Weaknesses

High PerformanceTime

Synchronization

Reduced Clock Overhead

Low Noise Immunity


High Process Sensitivity

N1

N4

A

Inputs

F

nMOSNetwork

ProperW/L


Family Sensitivity

Limited Fail Diagnosability

Additional Device Count

Gnd

Network

No Race (NORA)No Race (NORA) Logic Logic II

VDD VDD VDD

Outputs from apMOS network

ornDomino

N1

Φ

nMOSNetwork

N2

Φ

pMOSNetwork

N3

Φ

nMOSNetwork


Outputs to apMOS network

Outputs to anMOS network

Outputs to apMOS networkOutputs to a

nMOS network

Gnd Gnd Gnd

21

prechargeevaluation

S h W k

NORANORA Logic Logic IIII

N1

ΦStrengths Weaknesses

Reduced Delay Stages

pMOS Evaluation Devices

Low Fanout and Capacitance

Clocking Complexity

Low AreaLow FanoutCapability


N2

p y

Complete Logic Family

Zipper DominoZipper Domino Logic Logic ΙΙ

ΦΦV V (0, (0, VVDDDD––VVtptp))

VDD VDD VDD

Outputs from apMOS network

N1

ΦV

nMOSNetwork

ΦN2

Φ

pMOSNetwork

ΦV

N3

ΦV

nMOSNetwork

Φ


ΦΦV V (V(Vtntn, V, VDDDD))

Gnd

Φ

Gnd

ΦV

Gnd

Φ

22

Zipper DominoZipper Domino Logic Logic ΙΙΙΙ

prechargeevaluation

VDDΦΦV

ΦΦV

VDD–Vtp

VDD

Vtn

Gnd


Gnd

Differential Differential DominoDomino Logic (Logic (DDLDDL))

VDD

N1 N2

Α Β C

D

F

A

B D

F

Φ


Differential nMOS networkGnd

C

Φ

23

CrossCross‐‐Coupled DominoCoupled Domino ((CCDCCD) Logic) Logic

VDD

N1 N2

Α Β C

D

F

A

B D

F

Φ Φ


Differential nMOS networkGnd

C

Φ

DDLDDL and and CCDCCD LogicLogic



High Device Count, Area

Enhanced Noise Immunity

High Clock Load

Hi h P fHigh Power


High Performanceg

Consumption

24

SampleSample‐‐Set Differential Set Differential ((SSDSSD) ) Logic Logic

VDD

Φ ΦF

Φ

Gnd

Φ

Φ

F


Gnd

Differential nMOS network

Φ

EnableEnable‐‐Disable Disable CMOSCMOS DifferentialDifferential Logic Logic ((ECECDLDL))

ΦVDD

N1

F

Φ

F

GndGnd

Φ


Gnd


Gnd Gnd

25

ECDLECDL LogicLogic


DifferentialDifferential Current Switch Current Switch ((DCSDCS) ) Logic Logic

ΦVDD

F

Φ

F

Gnd


Gnd


26

SSDSSD and and DCSDCS LogicLogic



High Device Count, Area

High PerformanceHigh Clock Load,

Routing

High Logic DepthClock Generation


High Logic DepthConstrains

DifferentialDifferential Current Mirror Current Mirror ((DCMDCM) ) Logic I Logic I

Cross CoupledPair


Current Mirrors

Tsiatouhas et.al., ISCAS, 2006

27

DifferentialDifferential Current Mirror Current Mirror ((DCMDCM) ) Logic IILogic II


DynamicDynamic Complementary Pass Gate Complementary Pass Gate ((DCPDCP) ) Logic Logic

VDD

F

B

FANDNAND

Φ Φ


MOS E l iComplementary


Α

Β

B AB

nMOS EvaluationComplementary I/O Needed

Glitch‐Free Operation

Charge Redistribution

Added Clock Load

28

BibliographyBibliography

• “High Speed CMOS Design Styles,” K. Bernstein, K. Carring, C. Durham, P. Hansen, D.Hogenmiller, E. Nowak and N. Rohrer, Kluwer, 6th Edition, 2002.

• “Digital Integrated Circuits: A Design Perspective,” J. Rabaey, A. Chandrakasan and B.Nikoloc, Prentice Hall, 2003.

• “Design of High‐Performance Microprocessor Circuits,” A. Chandrakasan, W. Bowhill andF. Fox, IEEE Press, 2001.


Documents

CMOSCMOS INTEGRATED INTEGRATED CIRCUIT DESIGN TECHNIQUEStsiatouhas/CCD/Section_4-2p.pdf · 1 CMOSCMOS INTEGRATED INTEGRATED CIRCUIT DESIGN TECHNIQUES University of Ioannina CMOS Logic