Singh_Siddhartha_Anirban.pdf - e-scholar @ Ontario Tech

Design and Implementation of a SinglePhase Modified Z-source Inverter

Topology for Photovoltaic/GridInterconnected DC Charging Applications

by

Siddhartha Anirban Singh

A THESIS SUBMITTED IN PARTIAL FULFILMENT

OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

in

The Faculty of Engineering and Applied SciencesProgram

UNIVERSITY OF ONTARIO INSTITUTE OF TECHNOLOGY

MARCH 2018

©Siddharth Anirban Singh, 2018

ABSTRACT

Solar energy has been the most popular sources of renewable energy for residential andsemi-commercial applications. Solar energy sources alone cannot be used to charge anelectric vehicle (EV). Solar/Grid interconnected charging stations are used to chargeEV batteries to reduce the dependency on the grid and enable charging at convenientlocations such as a residential garage or a parking lot right next to an office or a shoppingmall.

The Z-source inverter (ZSI) topology achieves voltage boost and DC-AC power con-version in a single stage. In this thesis, the design and implementation of a modifiedZSI (MZSI) based charging topology for PV/EV/Grid interconnected application has beenpresented. The operation of the proposed topology was verified. The proposed topologyreduces the number of conversion stages to charge EVs from a Smart Grid/PV interface(high efficiency).

A 3.3 kW MZSI has been designed and simulated using PLECS. Detailed loss model-ing was done using PLECS. The peak efficiency of 94% was observed under irradiationand temperature changes. A scaled-down version of the proposed topology has beenimplemented for proof of concept.

In a single-phase 60 Hz inverter, the 120 Hz component has to be suppressed. Oneway is to size the capacitance in the system to absorb the 120 Hz component which mayresult in a bulky system. The design of Active Power Filters (APF) for the ZSI topologycan be tricky because of the shoot-through state. A new DC side active power filter hasbeen proposed for ZSI topology which suppresses the 120 Hz component completelythereby eliminating the need to use electrolytic capacitors in ZSI systems. The proposedAPF can reduce the capacitance by 100 times. Simulation studies have been presentedfor the proposed topology.

i

DEDICATION AND ACKNOWLEDGEMENTS

First, I would like to thank my supervisor, Dr. Sheldon S. Williamson, for giving me theopportunity to work with him in his laboratory. I express my sincere gratitude to Dr.Williamson for having the faith in me and constantly encouraging me to push hardertowards excellence.

I thank Dr. Najath Abdul Azeez, for being an amazing mentor and for all the inputsand encouragement throughout my research.

I thank Dr. Lalit Patnaik for his insightful feedback and critical comments whichhelped me to think harder about my work every day.

I would like to thank all my fellow labmates Deepak, Vamsi, David, Amandeep, Sang,Janamejaya, Ronanki, Navbir, Arun, Rishi, Arvind, Praneeth, Deepa, Hassan, Manjot,Shoma, Kai and Akash in the STEER group for the past three and a half years forsharing their knowledge but more importantly being a family everyday through our upsand downs.

I would also like to thank the PEER group members at Concordia University. I wasthere only for a year at the start of my doctoral studies but met some amazing people. Abig thank you to Dr. Abhijit Choudhury helped me through my initial days at ConcordiaUniversity, Montreal.

I thank Mr. Gautam Banerjea for showing faith in me and pointing me in the rightdirection during my undergraduate studies in India.

I thank Dr. Bimal B. Sen for his constant encouragement throughout my doctoralstudies.

I thank two of my best friends Aishwarya and Vani for sticking by me and giving meunconditional support and encouragement throughout my undergraduate, masters anddoctoral studies.

Last but most importantly, I thank my parents and sister for being patient withme and allowing me to pursue my dreams and my late paternal grandparents for theirunconditional love and encouragement.

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Dedicated to my parents and my sister Sanjukta.

iv

TABLE OF CONTENTS

Page

List of Tables viii

List of Figures ix

1 Introduction 3

1.1 Methods of Charging an Electric Vehicle . . . . . . . . . . . . . . . . . . . . 4

1.2 Photovoltaic Power Conversion Systems . . . . . . . . . . . . . . . . . . . . . 6

1.3 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.1 EV Charging Standards . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.2 Photovoltaic/Grid Interconnection Standards . . . . . . . . . . . . . 12

1.4 Existing Photovoltaic-AC Grid Integrated DC Charging Architecture . . . 12

1.5 Research Goal and Objectives of the Thesis . . . . . . . . . . . . . . . . . . . 16

1.6 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2 Background of a Z-source Inverter 19

2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.3 Maximum Shoot-Through Duty Ratio . . . . . . . . . . . . . . . . . . . . . . 26

2.4 Z-network Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.5 Z-network Capacitor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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TABLE OF CONTENTS

2.6 Small Signal Modeling of the ZSI . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.7 Controller Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.8 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.8.1 Operation under Variable Input . . . . . . . . . . . . . . . . . . . . . 31

2.8.2 Operation under Variation in the Z-network . . . . . . . . . . . . . . 35

2.9 Experimental Setup and Results . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.9.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.9.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.10 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3 A Single Phase Traditional Z source Inverter topology for Photovoltaic/Grid

Integrated DC Charger 47

3.1 Modified Z-source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.1.1 Maximum Shoot Through Duty Ratio, D0max . . . . . . . . . . . . . 49

3.1.2 Inductor L1 and L2 Design . . . . . . . . . . . . . . . . . . . . . . . . 49

3.1.3 Capacitor C1 and C2 Design . . . . . . . . . . . . . . . . . . . . . . . 49

3.1.4 Average Modeling of the Integrated Half-Bridge DC-DC Converter

Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.1.5 State Space Average Modeling of the Single Stage Inverter Charger 51

3.1.6 Energy Management Scheme for the Proposed Converter . . . . . . 55

3.2 Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . 57

3.3.1 Simulation Study for a MZSI Operation . . . . . . . . . . . . . . . . 57

3.3.2 Loss Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.3.3 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.3.4 Proof of Concept of the MZSI Topology . . . . . . . . . . . . . . . . . 67

3.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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TABLE OF CONTENTS

4 DC side Active Power Filter(APF) for Second Order Harmonic sup-

pression in Impedance Source Inverters 71

4.1 Origin of Second Order Harmonics in Solar Inverters . . . . . . . . . . . . . 72

4.2 Proposed DC Side Active Power Filter for ZSI . . . . . . . . . . . . . . . . . 75

4.2.1 Capacitor CS Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.2.2 Inductor LS Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3 Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.1 Determination of the Second Harmonic Current . . . . . . . . . . . 78

4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5 Conclusion and Future Work 83

5.0.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.0.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Bibliography 91

A PLECS 4.0.4 Simulation Circuits 103

vii

LIST OF TABLES

TABLE Page

1.1 SAE J1772:AC Charging Levels(North America) . . . . . . . . . . . . . . . . . . 12

1.2 SAE J1772:DC Charging Levels(North America) . . . . . . . . . . . . . . . . . . 12

2.1 Shoot-Through PWM Logic Generation in [1] . . . . . . . . . . . . . . . . . . . . 25

2.2 Shoot-through PWM logic generation in [2] . . . . . . . . . . . . . . . . . . . . . 25

2.3 PI Controller Values for simulation results . . . . . . . . . . . . . . . . . . . . . 30

2.4 PV module Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.5 ZSI Component Specifications for the Proposed System . . . . . . . . . . . . . 32

2.6 ZSI Prototype Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 39

2.7 ZSI Prototype Component Specifications . . . . . . . . . . . . . . . . . . . . . . 40

2.8 PI Controller Values for experimental results . . . . . . . . . . . . . . . . . . . 44

3.1 Isolated Split Primary HBC PWM Logic . . . . . . . . . . . . . . . . . . . . . . . 57

3.2 Modified ZSI based Charger System Simulation Specifications . . . . . . . . . 61

3.3 Component Models used for Loss Modeling of the Proposed System . . . . . . 61

3.4 ZSI Prototype Component Specifications . . . . . . . . . . . . . . . . . . . . . . 63

3.5 Modified ZSI based Charger System Prototype Electrical Specifications . . . . 67

3.6 Isolated Split Primary Half Bridge DC-DC System Electrical Specifications . 69

4.1 ZSI Simulation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.2 APF parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

viii

LIST OF FIGURES

FIGURE Page

1.1 Block diagram of a typical On-board Plug-in AC Charging Architecture . . . 4

1.2 Block diagram of a typical Off-board Plug-in DC charging Architecture . . . . 5

1.3 Block diagram of a typical Wireless Charging Architecture . . . . . . . . . . . 5

1.4 Block diagram of a Microinverter Architecture . . . . . . . . . . . . . . . . . . . 7

1.5 Block diagram of a String Architecture . . . . . . . . . . . . . . . . . . . . . . . 9

1.6 Block diagram of a Centralized Architecture . . . . . . . . . . . . . . . . . . . . 10

1.7 Block diagram of a typical DC Charging Architecture with an AC Link . . . . 13

1.8 Block diagram of a typical DC Charging Architecture with an DC Link . . . . 14

2.1 Schematic of a Z-source Inverter (ZSI) for photovoltaic/AC grid inter- con-

nected applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 Schematic of ZSI topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3 Shoot-through state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.5 Gain vs shoot-through duty ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.6 Peak modulation index vs shoot-through duty ratio . . . . . . . . . . . . . . . . 23

2.7 Switching Waveform for ZSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.8 Switching Waveform for ZSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.9 Block diagram of the controller for ZSI . . . . . . . . . . . . . . . . . . . . . . . . 29

ix

LIST OF FIGURES

2.10 Electrical Characteristics of BP 175B Solar under variable temperature . . . 31

2.11 Electrical Characteristics of BP Solar 175B under variable irradiations . . . . 32

2.12 Waveform for grid voltage (vg (scaled 10 times)), grid current (ILf ), capacitor

voltage (VC), DC Link Voltage (VPN) and shoot-through duty ratio(D0) for a

step change in inductor current (IL1), from 9.8 A to 4.9 A at 25C . . . . . . . 33

2.13 Waveform for grid Voltage (vg (scaled 10 times)), grid current (i g), capacitor

voltage (VC), DC link voltage (VPN) and shoot through duty ratio (D0) for a

step change in inductor current (iL1), from 9.952 A to 4.976 A at 45C . . . . 34

2.14 Simulation waveforms of capacitor voltages, peak DC link voltage and inductor

current for C1=5000 uF and C2=2500 uF . . . . . . . . . . . . . . . . . . . . . . 35

2.15 Simulation waveforms of capacitor voltages, peak DC link voltage and inductor

current for C1=2500 uF and C2=5000 uF . . . . . . . . . . . . . . . . . . . . . . 35

2.16 Change is DC link voltage ripple with irradiation changes for unequal capaci-

tances in the z-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.17 Change is DC link voltage ripple with irradiation changes for unequal capaci-

tances in the z-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.18 Variation in output AC current THD with irradiation changes for unequal

capacitances in the z-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.19 Variation in output AC current THD with temperature changes for unequal

capacitances in the z-network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.20 Experimental Configuration of the ZSI topology . . . . . . . . . . . . . . . . . . 39

2.21 LEM LA 55-P hall effect current sensor connection . . . . . . . . . . . . . . . . 40

2.22 LEM LA 55-P hall effect current sensor . . . . . . . . . . . . . . . . . . . . . . . 40

2.23 dSPACE rapid prototyping controller board . . . . . . . . . . . . . . . . . . . . . 41

2.24 Powerex BG2C gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.25 Experimental implementation of the PWM logic[ . . . . . . . . . . . . . . . . . 42

x

LIST OF FIGURES

2.26 Input inductor current iL (blue:100 mv/A), the capacitor voltage Vc (red), the

input voltage to the ZSI (pink: 40 V/div) and the the ZSI output current ig

(green:100 mV/A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.27 Input inductor current iL (blue:100 mv/A), the capacitor voltage Vc (red), the

input voltage to the ZSI (pink: 40 V/div) and the the ZSI output current ig

(green:100 mV/A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.28 Critical points of a Z- source Single Phase inverter layout . . . . . . . . . . . . 45

3.1 Detailed Schematic of Proposed MZSI . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2 Isolated Split primary half bridge DC-DC converter schematic . . . . . . . . . 51

3.3 Schemetic of one the Primary across CHB1 operating at 50% duty cycle . . . 51

3.4 Equivalent Model of the proposed Modified Z-source Inverter(MZSI) with

battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5 Block diagram of the Control Scheme Proposed Modified Z-source Inverter

Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.6 Simplified Block Diagram of the System . . . . . . . . . . . . . . . . . . . . . . . 55

3.7 Two MZSI connected in series connected across one high voltage battery . . . 56

3.8 Two MZSI connected in parallel for current sharing across one low battery

voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.9 Simulation Waveform for the PWM logic for the split primary half bridge

DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.10 Simulation waveform for the power balance between the photovoltaic input

power, the AC grid side and the battery power . . . . . . . . . . . . . . . . . . . 59

3.11 Simulation Waveform of the grid current, i g, DC link voltage, VPN , Capacitor

Voltage, VC1, and Battery current, ib for the power balance between the

Photovoltaic input power, the AC Grid side and the battery power for a step

change in irradiation from 1000W /m2 to 500W /m2 . . . . . . . . . . . . . . . . 60

xi

LIST OF FIGURES

3.12 Loss distribution chart for the MZSI topology for a fixed charging power

PB=3.3 kW at 25 C, under varying irradiation . . . . . . . . . . . . . . . . . . . 62

3.13 Efficiency curve for different ratios of AC Grid Power Pg to Photovoltaic Power

Ppv curve for a fixed charging power PB=3.3 kW at under varying photovoltaic

condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.14 Loss distribution for various battery voltages,VB, for a fixed charging power,PB=3.3

kW, at 45 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.15 Experimental Configuration of the ZSI topology . . . . . . . . . . . . . . . . . . 64

3.16 LEM LA 55-P hall effect current sensor connection . . . . . . . . . . . . . . . . 65

3.17 LEM LA 55-P hall effect current sensor . . . . . . . . . . . . . . . . . . . . . . . 65

3.18 dSPACE rapid prototyping controller board . . . . . . . . . . . . . . . . . . . . . 65

3.19 Powerex BG2C gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.20 Isolated Split primary half bridge DC-DC converter setup . . . . . . . . . . . . 66

3.21 PWM logic for the isolated HBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.22 Experimental setup waveforms for the Inductor current(top), charger output

current(middle) and the primary currents of the split charger(bottom) . . . . 68

3.23 Experimental waveform input current(blue) and output current(green) be-

tween the charger and the AC output of the MZSI . . . . . . . . . . . . . . . . . 69

4.1 Proposed DC side shunt active power filter for ZSI topology. . . . . . . . . . . . 76

4.2 Schematic of a ZSI topology with proposed DC side shunt active power filter. 76

4.3 Schematic of a QZSI topology with proposed DC side shunt active power filter. 76

4.4 Block Diagram of the control strategy of the APF. . . . . . . . . . . . . . . . . . 77

4.5 Schematic Diagram of the simulation circuit . . . . . . . . . . . . . . . . . . . . 79

4.6 Simulation waveform of a ZSI operating operating at steady state with

vin=286 V, iL=9.8 A, DC link voltage VPN=433 V and D0=0.1697 without

APF with a step change at t=1.75 secs . . . . . . . . . . . . . . . . . . . . . . . . 80

xii

LIST OF FIGURES

4.7 Simulation waveform of a ZSI operating operating at steady state with

vin=286 V, iL=9.8 A, DC link voltage VPN=433 V and D0=0.1697 with APF

with a step change at t=1.75 secs . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.1 Schematic of PV/Grid interconnected QZSI . . . . . . . . . . . . . . . . . . . . . 87

5.2 Schematic of a modified PV/Grid interconnected QZSI (MQZSI) . . . . . . . . 87

A.1 Circuits for ZSI PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

A.2 ZSI shoot-through state generation . . . . . . . . . . . . . . . . . . . . . . . . . . 104

A.3 ZSI shoot-through state generation . . . . . . . . . . . . . . . . . . . . . . . . . . 104

A.4 ZSI output current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

A.5 ZSI input current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

A.6 Battery current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

A.7 Capacitor voltage controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

A.8 Schematic of the single phase grid connected ZSI . . . . . . . . . . . . . . . . . 107

A.9 Schematic of the proposed MZSI topology . . . . . . . . . . . . . . . . . . . . . . 107

A.10 Schematic of Operational Amplifier based Implementation of Hysteresis Cur-

rent Control (HCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

xiii

NOMENCLATURE

Symbols DefinitionAC Alternating currentC Capacitance (Farads)

CSI Current source inverterD Duty cycleD0 Shoot-through duty cycleDC Direct currentEV Electric vehiclefSW Switching frequency (Hz)

HBC Half bridge converterHz Frequencyi pv Input PV currenti g Output AC currentL Inductance (Henry)M Modulation index

MZSI Modified Z-source inverterPV Photovoltaic

PWM Pulse width modulationTHD Total harmonic distortionVSI Voltage source invertervB Battery voltagevpv Input PV voltagevg Output AC voltage

VPN DC link voltageω Frequency in rad/sec

1

CH

AP

TE

R

1INTRODUCTION

Charging of electric vehicles currently heavily involves the use of the AC grid.

The various methods of charging such as wireless charging or plug-in charging

still cause pollution irrespective of how highly efficient the topology is. The

amount of fossil fuels that are consumed to generate the energy required to charge an

electric vehicle gives a clearer picture of the overall efficiency that is achieved while

charging an electric vehicle. To achieve a lower carbon footprint, one of the ways is

to integrate renewable energy sources into a charging infrastructure to reduce the

dependency on the AC grid.

Photovoltaic/grid interconnected systems have been used in the past for commercial

charging infrastructure [3][4]. These systems reduce the dependency of the charging

infrastructure on the AC grid. The use of solar and grid interconnected system is an

attractive solution for residential charging systems for EVs. For systems up to 10 kW

[5], single phase inverters can be used for residential applications. For interconnection

of the residential solar PV to the grid, various isolated and non-isolated topologies are

available with multiple stages [5]-[7]. Residential photovoltaic systems for EV charging

3

CHAPTER 1. INTRODUCTION

require features such as bidirectional power flow capability, isolation and voltage boost

capability to match the solar PV array voltage to the grid voltage requirements.

1.1 Methods of Charging an Electric Vehicle

Figure 1.1: Block diagram of a typical On-board Plug-in AC Charging Architecture

The methods of plug-in charging of electric vehicles can broadly be classified into

AC Charging and DC charging based on the nature of charge current. Both AC plug-in

charging and DC plug-in charging can be achieved directly from the AC grid using

multiple stages [8]. The block diagram shown in Figure 1.1 is of a typical AC charging

method onboard an EV which has a rectifier, a power factor correction stage and a DC to

DC battery charger stage which is connected to the battery onboard the electric vehicle

[9]-[11]. The DC-DC charger stage can either be an isolated or non-isolated topology.

During charging the EV is plugged into the AC grid by a connector through a port of the

EV.

The use of DC off-board charging eliminates the need for onboard converters on EVs.

4

1.1. METHODS OF CHARGING AN ELECTRIC VEHICLE

Figure 1.2: Block diagram of a typical Off-board Plug-in DC charging Architecture

Figure 1.3: Block diagram of a typical Wireless Charging Architecture

Figure 1.2 represents the block diagram of a typical off-board plug-in DC charging archi-

tecture. Based on the technology used, power electronics converters used for charging

applications can be classified into isolated and non-isolated type [12][13]. The use of isola-

tion transformers in power electronics converter topologies provides galvanic isolation to

the user end from the rest of the high voltage (HV) system. Providing galvanic isolation

is one of the requirements for designing an EV battery charger as a safety measure [14].

The galvanic isolation can be provided either on the AC grid side or on the charger

side.The size of the isolation transformer on the grid side is usually much larger than

5


the one on the charger side [15]. Due to the improvement in semiconductor technology,

high-frequency switching facilitates the use of smaller sized transformers for galvanic

isolation. The use of isolation, on the other hand, can result in the use of a large number

of components and increase in the complexity of the controllers of the converter. The cost

of such converter is higher and the reliability is reduced.

The use of non-isolated bidirectional DC-DC converters was proposed for fast charging

of Plug-in Hybrid electric vehicles (PHEVs) [12]. The other requirements are to be able

to charge various EV batteries having a wide range of voltage requirements. The use of

either the isolated or non-isolated converter topologies require a rectifier at the input

side and for integration for any other energy sources will require an additional power

converter.

1.2 Photovoltaic Power Conversion Systems

At the heart of the photovoltaic power conversion system is the photovoltaic inverter

which converts DC power to AC power. Photovoltaic inverters have two main categories:

1. Standalone Inverters: These inverters have a photovoltaic array as a source and

supply to AC loads directly at the output. The power supply to the load is completely

dependent on the photovoltaic power generated. Standalone inverters are not

capable of charging EV batteries without the assistance of the Grid or an electric

energy storage system.

2. Grid-Connected Inverters: These Inverters have photovoltaic panels as the DC

source and the AC grid as the inverter output load [16]. The inverter output voltage

is clamped to the AC grid voltage. This category of inverters is widely used for

charging of EVs.

6

1.2. PHOTOVOLTAIC POWER CONVERSION SYSTEMS

Grid-connected photovoltaic inverter topologies are broadly classified into various cate-

gories based on a number of factors [5]:

1. Based on PV arrays connected to the Inverter: In this category, solar inverters can

be classified into [17]:

a) Micro Inverters: A Micro Inverter consist of a small DC to AC grid matching

power conversion unit installed behind a solar panel [18][19].

Some of the main advantages of a microinverter are:

Figure 1.4: Block diagram of a Microinverter Architecture

i. Maximum power can be extracted from each solar panel(usually 100W to

400W) even under partial shading conditions.

7


ii. Low DC voltage (around 60V).

iii. Reliability is higher (guarantee of up to 25 years provided by manufactur-

ers).

Some of the disadvantages of a microinverter based solar system are:

i. Cost.

ii. Integration of energy storage units can be expensive.

When the photovoltaic has lower input DC voltage, some architectures inte-

grate a high boost DC-DC converter stage between the DC-DC converter and

the microinverter and the entire conversion stage is mounted behind the PV

panel. Such architecture is known as a "Micro-Converter". The most common

DC-DC converters used for micro converters are flyback and boost converter

[20].

b) String Inverters: String inverters are the most commonly used solar inverter

systems for residential applications [21]-[23]. They consist of a "string" of

panels connected to a single inverter. Such systems are then connected to the

AC grid (120 V/240 V/250 V, 60Hz). For safety reasons in North America, the

National Electrical Code (NEC) in article 690 restricts the maximum voltage

of the PV source to 600V.

Some of the advantages of a string inverter based solar system are:

i. Perfect for residential solar systems for power levels up to 10 kW.

ii. Higher power and voltage levels allow for a lower cost to integrate energy

storage systems.

iii. Higher flexibility while designing high power systems using cascaded

structures.

iv. lower cost per kW generated over its lifetime (10-12 years).

8


Figure 1.5: Block diagram of a String Architecture

Some of the disadvantages of a string inverter based solar system are:

i. High DC voltage levels can be a health hazard. Require isolation.

ii. Shorter life compared to a microinverter.

iii. PV string sizing is important.

iv. Lower efficiency during partially shaded condition since maximum power

point tracking (MPPT) is not available for each PV panel.

9


c) Central Inverters: Central Inverters are mostly used in industrial applications.

They are rated for above 100 kW in solar grid tied applications and can be

rated as high as 2500 kW [24].

Some of the advantages of a central inverter based solar system are:

Figure 1.6: Block diagram of a Centralized Architecture

i. High Power density.

ii. High efficiency.

iii. Installation is easier because of a single unit structure.

Some of the disadvantages of a central inverter based solar system are:

i. Bulky.

ii. Single point of system fault. Reliability can be an issue.

iii. Installation is easier because of a single unit structure.

2. Based on Topology: In this category, photovoltaic inverters can be broadly classified

in Current Source Inverters (CSI) and Voltage Source Inverters (VSI). CSI has

a constant output current irrespective of the load. It has a large input inductor

which allows it to operate without a dead time. The peak output AC voltage is

10


higher than the input DC link voltage. In energy storage applications, CSIs are

avoided due to the inability to store energy. VSI has a constant voltage output

irrespective of the load. During operation, no two switches of the same leg can

be switched on at the same time. This can result in dead short of the DC input

voltage source. Such situation can happen unwantedly if there is a radiated or

conducted electromagnetic interference (EMI) effect from some external source.

Such condition has to be avoided. It requires a "dead time" between two switches

of the same leg for safe operation. VSIs are normally used for energy storage

applications. The peak output AC voltage is lower than the input DC link voltage.

3. Power Level: For inverter applications up to 10 kW, single phase inverters are more

commonly used. These inverters use an H-bridge configuration consisting of four

switches. For power levels beyond 10 kW, three-phase inverters are more common.

Three phase inverters use three legs, six switch configuration for operation. For very

high power levels, multilevel inverters or multi-modular converters are preferred

because of the reduced voltage stresses on the switches [25][26].

4. Based on the presence of isolation: Based on isolation, Grid-connected photovoltaic

inverters can be classified into Isolated or Non Isolated topologies. Galvanic isola-

tion can be achieved through a low-frequency isolation transformer on the grid side

or a high-frequency transformer on the DC side. The isolation can be doubled up to

achieve a voltage boost on the secondary side. Non-Isolated photovoltaic inverters

are more compact, efficient and cost less as compared to isolated photovoltaic

inverters [5]-[7] [27].

11


Table 1.1: SAE J1772:AC Charging Levels(North America)

Charge Method Nominal Supply Voltage(V) Maximum Continuous Current(A)

AC Level I 120 V AC (1-ph) 16 A

AC Level II 208 V-240 V AC (1-ph) 80 A

Table 1.2: SAE J1772:DC Charging Levels(North America)

Charge Method EVSE DC Output Voltage(V) Maximum Continuous Current(A)

DC Level I 200 V-500 V (DC) 80A

DC Level II 200 V-500 V (DC) 200 A

DC Level III 200 V-500 V(DC) 400 A

1.3 Standards

1.3.1 EV Charging Standards

EV charging method and power levels should comply with the Society of Automobile

Engineers (SAE) J1772 standard. It clearly states the power levels for each level of

charging for both AC and DC charging.

1.3.2 Photovoltaic/Grid Interconnection Standards

For photovoltaic grid, interconnected inverters UL1741/IEEE1547/IEEE 519-2014 stan-

dards are followed for maintaining power quality.

1.4 Existing Photovoltaic-AC Grid Integrated DC

Charging Architecture

In literature, the most common architectures that are used for photovolatic grid connected

charging infrastructures have a common AC Link or a DC Link shown in Figure 1.7

12

1.4. EXISTING PHOTOVOLTAIC-AC GRID INTEGRATED DC CHARGINGARCHITECTURE

and Figure 1.8 respectively. A detailed comparison of the various architectures has been

presented in [28].

Figure 1.7: Block diagram of a typical DC Charging Architecture with an AC Link

The AC link structure provides isolation to the EV from the Grid as well as to the PV

from the grid through a high frequency transformer [29]. It consists of multiple power

conversion stages which can be costly and the reliabilty can be an issue.

The DC link architecture is a more common structure in which the PV is connected

to the grid through a DC/DC stage followed by an inverter stage. The EV is isolated

from the PV and grid [30]. In [31], a solar powered residential home with AC charging

of PHEVs was proposed. The topology has single phase photovoltaic/grid integrated

H-bridge inverter integrated with a bidirectional DC-DC converter for energy storage.

The PHEV to be charged is connected as an AC load on the grid side. The isolation

requirement was not taken into consideration in this topology.

In [32], the architecture used is similar to the one shown in Figure 1.8. A 10 kW

PV/grid connected charger topology was proposed for mitigating the intermittency of the

photovoltaic power system using the charger functionality. The PV/ grid connection was

13


Figure 1.8: Block diagram of a typical DC Charging Architecture with an DC Link

achieved through a MPPT based DC/DC converter. The 25 kW PV systems consisted

of two strings of PV arrays connected to individual DC/DC. The outputs of the DC/DC

converters are connected together forming a common DC bus voltage which is then

connected to the grid through a three-phase inverter. A 10 kW charger has been connected

to the DC link. The charger consists of four 2.5 kW soft switched bidirectional DC-DC

converter.

EV charging through a residential BESS through a PV/grid connected 2.2 kW system

has been proposed in [33]. The topology consists of a common DC link to which the

PV is connected through a DC/DC converter. The DC link serves as the input to the

single-phase inverter tying the system to the AC grid. The BESS is connected to the DC

link of the inverter through a bidirectional DC/DC buck-boost converter. The single-phase

inverter has multiple functions such as to operate as an active power filter and harmonics

mitigation along with reactive power compensation. Although the bidirectional capability

of the voltage source inverter has not been addressed. In this topology, for each mode of

power flow, there are at least two stages. Any EV connected is charged from the BESS.

14

1.4. EXISTING PHOTOVOLTAIC-AC GRID INTEGRATED DC CHARGINGARCHITECTURE

As can be seen, solar inverters have used multi-stage systems for grid integration of

solar photovoltaics. There has been a great interest to increase efficiency as well as the

reliability of single stage inverter systems. When such inverters are used in applications

such as a charging infrastructure, the multiple-stages can result in lower efficiencies

and power densities in different modes of operations. The need for high-efficiency solar

converter chargers has resulted in generating particular interest in single stage solar

inverters and more specifically in z-source inverter topology proposed in [2]. It has gained

tremendous interest in photovoltaic-grid connected applications [34]-[38]. It has been of

great interest in residential applications [39].

The operation of a ZSI is heavily dependent on the passive components. It presents

an opportunity to integrate energy storage units into such a system. In [40], the Z-source

DC-DC converter topology was used to charge an EV from the PV directly but for the

reverse power flow of the EV to the grid was achieved through a separate PWM rectifier

topology. The ZSI topology was modified to develop a DC charging infrastructure in [15]

as a centralized photovoltaic grid connect inverter/charger.

Some of the advantages of a Z-source inverter for PV/grid/EV connected charging

applications are:

1. It has the unique ability to behave as a buck and boost converter in a single stage.

2. With the presence of the "shoot through" state, the reliability improves under

accidental short-circuit conditions due to Electromagnetic Interference (EMI) from

the surrounding equipment.

3. Compact high-frequency ZSI systems can be designed by reducing the component

sizing.

4. The PV, EV and the AC grid operate at three different voltage levels. Two of them

are different DC voltages and one of them is AC voltage. This is an advantage that

15


ZSI topology offers without an additional stage.

1.5 Research Goal and Objectives of the Thesis

The main research goal of this thesis is to design and develop a proof of concept for a

modified Z-source inverter/charger for photovoltaic/AC grid/EV integrated operation.

The implementation of the entire charging system includes various aspects such as

protection circuits, grid integration, battery charging algorithms, mechanical aspects and

communication systems. This research work is limited to the design and implementation

of the topology. The objectives of the research project were:

1. To investigate the single-phase ZSI topology and develop design guide-

lines for the Z-network for the MZSI

The ZSI network uses two inductors, two capacitors, a diode and a single phase

H-bridge inverter module to achieve voltage boost and DC/AC power conversion

in a single stage. The capacitors used are usually electrolytic capacitors which

have tolerance bands up to 50% due to manufacturing defects or even aging factors.

Inductors, on the other hand, have tight tolerance bands up to 10%. The effect of

these variations has a different effect on some of the key parameters of the ZSI

such as the DC link voltage ripple and the ZSI output AC current. The DC link

voltage ripple should be such that the maximum voltage ratings of the H-bridge

of the ZSI is never exceeded. In single phase systems, the second order frequency

ripple can cause a system failure if not contained. The harmonic content in the AC

output current should be kept below 5% as per IEEE 1547 standard defining the

quality of power that is being fed into or taken out of the AC grid. The controller

should be able to perform even during component mismatch and operate within

the standards described by IEEE. One of the objectives of this thesis is to reduce

16

1.6. OUTLINE OF THE THESIS

the component size. In this thesis, the Z-network inductors have been designed for

high-frequency shoot through state and a DC side active power filter (APF) has

been proposed that is able to completely reduce the second order harmonics.

2. Investigate the operation of the MZSI topology for a modular inverter/

charger configuration

In Z-source inverters, the active duty cycle and the shoot-through duty ratio is

coupled and follow a necessary condition that the summation of the modulation

index and the shoot through duty cycle at any instant should not exceed unity.

Decoupling the two can be quite a challenge. In this research work, the MZSI

topology has been proposed for modular operation which gives the flexibility of

increasing the power handling capacity of the charger and operates the ZSI at

high modulation indices to ensure good power quality drawn from the grid during

charging and to avoid a single point of fault as well as charge batteries with a wide

range of battery voltages at high efficiencies.

3. Implementation of a Modified ZSI topology for DC charging topology A

proof of concept for the proposed system has been presented. dSPACE rapid pro-

totyping controller board was used to implement the controller and generate the

PWM logic for the ZSI. Implementing the control logic for the control of current

of the MZSI. The implementation of MZSI also includes the design of the split

primary DC-DC converter design and integration.

1.6 Outline of the Thesis

• Chapter 1 discusses the various methods of charging techniques for pure elec-

tric/ hybrid electric vehicles, various kinds of a photovoltaic power conversion

systems, the common standards that need to be followed and an overview of the

17


existing structures of the photovoltaic-grid connected charging architectures that

are available in the literature for DC charging of electric vehicles.

• Chapter 2 provides a detailed review of the ZSI topology with a detailed description

regarding the operation, component design, controller strategy and issues related

to a single phase ZSI layout has been discussed.

• Chapter 3 introduces a modified Z-source inverter (MZSI). A detailed modeling,

component design, loss modeling, simulation results and experimental results.

• Chapter 4 proposes a DC side active power filter (APF) for the suppression of

second-order harmonics in the ZSI topology. The challenges, the proposed topol-

ogy, component design, operation, simulation results have been presented in this

chapter.

• Chapter 5 summarises the main points of the thesis and proposes some points for

future work.

18

CH

AP

TE

R

2BACKGROUND OF A Z-SOURCE INVERTER

In this chapter, a review of the ZSI topology, operation, PWM techniques, passive compo-

nent design, control strategy and practical layout issues and possible solutions has been

presented along with the simulation and experimental results of a single phase Z-source

inverter.

19

CHAPTER 2. BACKGROUND OF A Z-SOURCE INVERTER

Figure 2.1: Schematic of a Z-source Inverter (ZSI) for photovoltaic/AC grid inter- con-nected applications

The traditional Z-source Inverter (ZSI) topology for photovoltaic/grid connected ap-

plication is as shown in Figure 2.1 [2]. It uses two identical inductors, L1 and L2, two

identical capacitors, C1 and C2, a power diode D and a conventional H-bridge topology to

achieve voltage boost and inversion in a single stage. The output of the inversion stage

is connected to an AC load through a filter inductor, L f . The ZSI is able to boost a low

input photovoltaic voltage, vpv, to a voltage level, VPN , such that the the ouput AC volt-

age at the H-bridge output matches in the load requirements. In this photovoltaic/grid

connected applications, the load is the AC grid.

2.1 Operation

The basic topology of a Z-source inverter supplying an AC load is shown in Figure 2.2.

The ZSI topology, shown in Figure 2.2, utilizes two modes of operation to achieve boost

and inversion in a single stage [2].

1. Shoot-through state: For a time duration, T0, a PWM is generated and inserted

in the non active states of the conventional bipolar or unipolar PWM generation

20

2.1. OPERATION

Figure 2.2: Schematic of ZSI topology [2]

Figure 2.3: Shoot-through state Figure 2.4: Active state

technique. As long as the volt-sec balance of the PWM signal remains the same for

each half of the switching cycle, the insertion of the shoot through states will not

create any distortion in the output waveform [2].

2. Active state: This is the active state similar to the active state of a conventional

PWM VSI inverter which can be implemented through Unipolar PWM or bipolar

PWM generation.

The behaviour of the Z network during the shoot-through state and active state is

shown in Figure 2.3 and Figure 2.4 respectively. In the shoot through state, the switches

of the same leg,i.e, SA and SB or SC and SD , or all four switches are "ON" at the same

time. The diode D is "OFF" and the capacitors C1 and C2 discharge through the inductors

21


L1 and L2 respectively and the voltages of the capacitors are impressed upon the respec-

tive inductors. The duration of this shoot through state is described by the duty cycle D0

and the switching frequency fSW . In the non-shoot through or active state, where the ZSI

operates as a VSI. Thus, maintaining a higher voltage at the input of the DC link, VPN [2].

From Figure 2.1, for a input power, PPV , the input current is [2]:

(2.1) iPV = PPV

vPV

The peak DC link voltage, ˆVPN , at the input of the H-bridge inverter is given by [2]:

(2.2) ˆVPN = 11−2D0

vpv

Figure 2.5 shows the ZSI gain curve for various shoot through duty ratio is given by the

equation:

(2.3)ˆVPN

vpv= 1

1−2D0

D0 is the shoot through duty ratio of the ZSI. where [2],

(2.4) D0 = T0

T

where,

(2.5) T = 1fSW

The time duration T0 has a duty ratio of D0 such that

(2.6) D0(t)+Mmax < 1

where,

(2.7) D = Mmax sinωt

22

2.1. OPERATION

Figure 2.5: Gain vs shoot-through dutyratio

Figure 2.6: Peak modulation index vsshoot-through duty ratio

where, D is the active duty cycle. Equation (2.6) is a necessary condition for PWM

generation for a ZSI. The variation of the modulation index with the increase in shoot-

through duty ratio is shown in Figure 2.6.

The two capacitor average voltages are expressed as [2],

(2.8) VC =VC1 =VC2 =1−D0

1−2D0vpv

The average voltage across the DC link is [2],

(2.9) VPN =VC

The power balance equation between the DC and AC side of the ZSI is expressed as,

(2.10) (1−D0) ˆVPN IPN = i grmsvgrms

where IPN and VPN are the peak DC link current and voltage. The output R.M.S voltage

of the ZSI is [2]:

(2.11) vgrms =Mvpvp

2 (1−2D0)

(2.12) vgPK =VCD

1−D0

where vgPK is the peak voltage of the AC grid, D is the active duty ratio of the ZSI

switches.

23


2.2 PWM Generation

The PWM technique for a ZSI is slightly different from a conventional VSI. There are

two methods for implementing the above two states in a PWM switching technique for

single phase ZSI proposed in [1] and [2].

The switching waveform proposed in [1] is shown in Figure 2.7. The shoot through states

Figure 2.7: Switching Waveform for ZSI proposed in [1]

are inserted on either side of the active PWM pulses.

24

2.2. PWM GENERATION

Table 2.1: Shoot-Through PWM Logic Generation in [1]

Condition State

Vtri < (M−D0) SA=HighVtri < −M SB=HighVtri > M SC=High

Vtri > (−M−D0) SD=High

Table 2.2: Shoot-through PWM logic generation in [2]

Parameters Value

Vtri > (1−D0) HighVtri < −(1−D0) High

else Low

The slope of the inductor current shown is divided into two parts as shown in sectors

2-4, thereby reducing the rate of change of current in the inductor, iL. Thereby, the rate

of inductor current changes in lower. Although there are multiple points of DC link

voltage VPN changes. The DC link voltage changes from ˆVPN to 0 at the end of sector

1, from 0 to ˆVPN at the end of sector 2, from ˆVPN to 0 at the end of sector 3 and again

from 0 to ˆVPN at the end of sector 4. This method of PWM generation can cause multiple

points of DC link voltage ringing. In this method, a DC offset is observed at the inverter

output current.

In the PWM technique proposed in [2], the shoot through PWM duty cycle (shaded)

is inserted symmetrically in the middle of the traditional zero state of PWM inverter

operation as shown in Figure 2.8. The shoot through duty cycle is compared with the

peak of the triangular carrier wave with the logic shown in Table 2.2. As shown in Figure

2.8, in this PWM technique the DC link voltage changes from, ˆVPN to 0 at the end of

sector 2 and from 0 to ˆVPN at the end of sector 3.

25


Figure 2.8: Switching waveform for ZSI proposed in [2]

2.3 Maximum Shoot-Through Duty Ratio

The maximum shoot through ratio for a given application is described by the following

equation:

(2.13) D0max =VCmax −vpvmin

2VCmax −vpvmin

where, VCmax is the maximum capacitor voltage for the application and vpv is the

minimum voltage of the PV array connected to the ZSI.

26

2.4. Z-NETWORK INDUCTOR DESIGN

2.4 Z-network Inductor Design

The inductors are designed for the shoot through state when the capacitor voltage VC is

impressed on the inductors for the duration of the shoot through duty cycle D0 [41][42],

(2.14) VC =VL

(2.15) L = L1 = L2 = VCmaxD0max

fsw∆iL

where, VCmax is the maximum voltage across the capacitor, D0max is the maximum

shoot-through duty ratio. For triangular inductor current waveform, the RMS current of

3.5 A seems reasonable based on the performance of the electtrolytic capacitor. Thus for

a ∆iL=12 A the calculated inductor value was 560 uH.

2.5 Z-network Capacitor Design

The capacitors for a single phase topology are designed to absorb the second order voltage

harmonic (120 Hz).

(2.16) C = C1 = C2 >= P2ωVCmin∆VC

The voltage rating of the capacitor should be atleast the peak voltage across the capacitor

VC. Electrolytic capacitors are usually used in single phase inverters to suppress second

order harmonics. For less than 5% 120 Hz ripple, the calculated capacitance for a

minimum voltage of 360 V is 2.5 mF. Considering a tolerance band of 50%, a nominal

value of 5 mF is reasonable.

27


2.6 Small Signal Modeling of the ZSI

Small signal modeling for the ZSI is derived as: The KVL equation for the non shoot-

through mode [43],

(2.17)diL

dt= vpv −VC − iL(r+R)+ i gR

L

The KCL equation for the non shoot-through mode [43],

(2.18)dVC

dt= iL − i g

C

The dynamic state equation for the ZSI during non shoot-through state [43],

˙iL

VC

=

− (R+r)

L − 1L

− 1C 0

iL

VC

+

RL

1L

−(1)C 0

i g

vpv

The KVL equation for the shoot-through mode [43],

(2.19)diL

dt= VC − iL(R+ r)

L

The KCL equation for the shoot-through mode [43],

(2.20)dVC

dt=− iL

C

The dynamic state equation for the ZSI during the shoot-through state [43],

˙iL

VC

=

−R+r

L1L

− 1C 0

iL

VC

+

0 0

0 0

i g

vpv

The average state space equation for the ZSI can be written as [43],

28

2.7. CONTROLLER STRATEGY

˙iL

VC

=

− (r+R)

L −1−2D0L

1−2D0C 0

iL

VC

+

(1−D0)RL

1−D0L

−1−D0C 0

i g

vpv

The transfer funtion of the input current to the output current can be written as [15],

(2.21)iL(s)

î g(s)= sRC(1−2D0)+ (1−2D0)(1−D0)

LCs2 + sC(r+R)+ (1−2D0)2

Where î g(s) is the peak ac side inverter output current. The transfer function to control

the capacitor voltage loop can be written as [38],

(2.22)Vc(s)d0(s)

= −sL(2iL − i g)+ i g(2R+ r)−2iL(r+R)+ (2VC −Vin)(1−2D0)LCs2 + sC(r+R)+ (1−2D0)2

2.7 Controller Strategy

The controller strategy for controlling the input current to the ZSI and the output current

from the ZSI is shown in Figure 2.9.

Figure 2.9: Block diagram of the controller for ZSI

For photovoltaic applications, the reference input current is generated by a maximum

power point tracking (MPPT) algorithm [44][45]. The reference current is tracked by the

29


actual current with a PI controller:

(2.23) GC(s)= Kp + K i

s

The input current loop generates the peak magnitude of the ZSI output AC reference

current. The Capacitor voltage, VC, control loop has been discussed in literature previ-

ously [38]. The voltage controller requires a feedforward control to speed up the steady

state response given by:

(2.24) FFV (s)= VC1re f −VIN

2VC1re f −VIN

The voltage controller loop has the slowest response followed by the input current loop

and then the output AC current loop.

Table 2.3: PI Controller Values for simulation results

Controller Loop P I

Input Current Loop 50e-3 15Voltage Loop 6.7e-4 5e-5

Output Current Loop 60e-3 0

2.8 Simulation Results

A ZSI has been simulated for a PV rating of 2.8 kW. PV module parameters of BP solar

175B has been used for simulation. The electrical characterictics of a BP Solar 175B has

been shown in Table 2.4.

Table 2.4: PV module Electrical Specifications

Parameters Value

Open Circuit Voltage,Voc 44.2 VShort Circuit Current, IOC 5.45

Voltage at maximum power,Vmpp 35.8 VCurrent at maximum power,Impp 4.9 A

30

2.8. SIMULATION RESULTS

2.8.1 Operation under Variable Input

The characteristics of BP solar 175B for variable temperatures is shown in Figure 2.10.

Figure 2.10: Electrical Characteristics of BP 175B Solar under variable temperature

As shown in Figure 2.10, with the increase in temperature from 25 C to 60 C, the

PV output voltage decreases from the 35.8 V to 29.5 V. The power output of the module

also decreases from 174 W to 149.6 W. The PV output current increases from 4.9 A to 5 A.

On the other hand with the decrease in temperature from 25 C to 0 C, the PV output

voltage at peak power increases from the 35.8 V to 40.34 V. The peak power output of the

module also increases from 174 W to 193 W. Although the PV output current is reduced

from 4.9 A to 4.8 A.

The characteristics of BP 175B for variable irradiation is shown in Figure 2.11. With

the decrease in irradiadion from 1 kW/ m2 to 200 W/m2, the peak power output of the

PV panel changes from 174 W to 32 W. Although the PV output voltage at peak output

power changes shows little variation from 35.8 V to 33.8 V.

For a string consisting of 8 BP solar 175B panels connected in series and 2 such

strings are connected in parallel to obtains a 2.8 kW PV arrangement.

31


Figure 2.11: Electrical Characteristics of BP 175B Solar under variable irradiations

Table 2.5: ZSI Component Specifications for the Proposed System

Parameters Value

Input Voltage, vpv 286.2 VInput Current, i in 9.8 A

Inductor Value, L1=L2 560 uHSwitching Frequency, fSW 25 kHz

Grid Voltage, vg 240V (RMS)Inverter Output Filter Inductor, L f 7.5 mH

For the above string configuration, the minimum voltage is 236 V. When the maximum

impedance network capacitance voltage VCmax is 500V, the maximum shoot through ratio

from equation (2.13) is 0.345. For an RMS current of 3.5 A based on the performance of

electrolytic capacitors, ∆iL for triangular waveform is 12 A. The calculated to be 560 uH.

The capacitor value is 5000 uF for a 120 Hz voltage ripple less than 5%.

Simulation studies for the PV system has been carried out and a step change in input

current from 9.8 A to 4.9 A has been shown in the Figure 2.12. The THD for the inverter

side output AC current is maintained at 2.8% and 0.99 power factor through closed loop

control. The capacitor voltage loop shown in Figure 2.9 maintains the voltage VC at 360

32


Inductor Current, iL

Grid Voltage, vg and Grid Current, ig

Capacitor Voltage, Vc

DC Link Voltage, VPN

Shoot -Through Duty Ratio, D0

iL (

A)

0

5

10

15

20vg (

V)

/ ig

(A)

-40

-20

0

20

40

Vc

(V)

330340350360370380390400

VPN

(V)

0

100

200

300

400

500

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

D0

0.120.140.160.180.200.220.24

Figure 2.12: Waveform for grid voltage (vg[scaled 10 times]), grid current (i g), capacitorvoltage (VC), DC link voltage (VPN) and shoot-through duty ratio (D0) for a step changein inductor current (iL1), from 9.8 A to 4.9 A at 25C

V. The shoot-through duty ratio is maintained at 0.1697 according to equation (2.5).

Temperature variations are usually slower than possible irradiation changes. In

Figure 2.13, a step response to the input current is shown at 45 C is shown maintaining

the capacitor voltage at 360 V. The shoot through duty cycle is maintained at 0.22 and

the power factor is maintained 0.99.

33


Inductor Current, iL

Grid Voltage, vg and Grid Current, ig

Capacitor Voltage, Vc


Shoot -Through Duty Ratio, D0

iL (

A)

0

5

10

15

20

vg (

V)

/ ig

(A)

-40

-20

0

20

40

Vc

(V)

330340350360370380390400

VPN

(V)

0

100

200

300

400

500

2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

D0

0.20

0.21

0.22

0.23

0.24

0.25

0.26

Figure 2.13: Waveform for grid voltage (vg [scaled 10 times]), grid current (i g), capacitorvoltage (VC), DC link voltage (VPN) and shoot through duty ratio (D0) for a step changein inductor current (iL1), from 9.952 A to 4.976 A at 45C

Although in simulation the inductor current reference has been shown undergoing a

step response, in practical situations the change in the reference current is in the order

of minutes or even hours. The controllers performance under such rapid change in input

current shows it should have satisfactory performance under slower varying conditions.

The ZSI should be able to operate between the minimum input voltage and the

34


minimum input current under varying temperature and irradiation changes respectively.

The condition defined by equation (2.6) also states that higher the shoot through duty

cycle, lower is the modulation index. Inverters are usually operated at higher modulation

index (D>0.6) to maintain a good quality of sinusoidal output current.

2.8.2 Operation under Variation in the Z-network

Figure 2.14: Simulation waveforms ofcapacitor voltages, peak DC link voltageand inductor current for C1=5000 uFand C2=2500 uF

Figure 2.15: Simulation waveforms ofcapacitor voltages, peak DC link voltageand inductor current for C1=2500 uFand C2=5000 uF

The ZSI is heavily dependent on the performance of the passive components in the

Z-network. The passive components used in the design of the system have a tolerance

band within which its values can vary. The ZSI uses two inductors and two capacitors.

In most study they are assumed to have equal values. The tolerances become even more

35


important in single phase ZSI for symmetrical operations. Inductors in general have

tight tolerance bands upto 10%. Such a small variation do not cause any major changes

in the operation of the ZSI apart from the change in the high frequency ripple content.

The designed value of the inductor in this thesis was 560 uH and with tolerance band

limit upto 10%.

On the other hand electrolytic capacitors used single phase systems can have toler-

ances upto 50% due to manufacturing defects, aging affect over time etc. Components

with tighter tolerance bands are more expensive. In this section the effect of varying

capacitance values on the DC link voltage ripple and the AC output current THD of the

ZSI has been discussed. Figure 2.14 and Figure 2.15 show simulation waveforms for a

system operating at an input voltage of 286.4 V and capacitor voltage VC1=360 V.

Figure 2.16: Change is DC link voltage ripple with irradiation changes for unequalcapacitances in the z-network

2.8.2.1 C1 > C2

As shown in Figure 2.14, VC1 and VC2 operating at the set voltage of 360 V but the 120

Hz content differ leading to unequal voltage stress between the two capacitors. The

inductor current in L1 is observed to be carrying a higher 120Hz ripple than L2. The

peak to peak ripple Dc link voltage ∆VPN= 11.5 V.

36


Figure 2.17: Change is DC link voltage ripple with temperature changes for unequalcapacitances in the z-network

Figure 2.18: Variation in output AC current THD with irradiation changes for unequalcapacitances in the z-network

2.8.2.2 C1 < C2

As shown in Figure 2.15, VC1 and VC2 operating at the set voltage of 360 V but the 120

Hz content differ leading to unequal voltage stress between the two capacitors. The

inductor current in L2 is observed to be carrying a higher 120 Hz ripple than L1. The

peak to peak ripple DC link voltage ∆VPN= 17 V.

As can be seen from the Figure 2.16 and Figure 2.17, when C1 > C2, DC link voltage

37


Figure 2.19: Variation in output AC current THD with temperature changes for unequalcapacitances in the z-network

ripple is higher than when C1 < C2 under the same irradiation conditions. From Figure

2.10 and Figure 2.11 , the change in irradiation causes a change in input current to the

ZSI with little variation in input voltage and change in temperature causes a change in

the input voltage with little change in current respectively. With temperature variations,

the DC link voltage ripple goes through a larger variation when C1 < C2.

Figure 2.18, the variation of output AC current THD under unequal capacitances

and equal capacitances have been shown. It was observed that the THD was highest

when C1 > C2 under varying irradiation condition. From Figure 2.19, with temperature

variations, the AC output current THD is highest when C1 > C2.

From the design parameters in this thesis, the DC link voltage ripple in maintained

below 5% in the tolerance bands of the electrolytic capacitors. The AC output current

THD is also maintained below 5% in accordance with IEEE 1547 standard.

38

2.9. EXPERIMENTAL SETUP AND RESULTS

2.9 Experimental Setup and Results

2.9.1 Experimental Setup

The experimental setup for the ZSI topology was implemented though a hardware-in-loop

setup with dspace 1103 rapid prototyping controller at the core of the controller. The

experimental setup for the Z source inverter topology is shown in Figure 2.17. The

electrical specifications used in this thesis is listed in Table 2.6 and the components used

is presented in Table 2.7.

Figure 2.20: Experimental Configuration of the ZSI topology

The specifications of the ZSI prototype is shown in Table 2.4.

Table 2.6: ZSI Prototype Electrical Specifications

Parameters Value

Input Voltage, Vin 38 VInput Current, I in 3.8 A

Inductor Value, L1=L2 560 uHSwitching Frequency, fSW 25 kHz

Inverter Output Filter Inductor, L f 2.5 mH

39


Table 2.7: ZSI Prototype Component Specifications

Component Specification

DC voltage source Magna Power LXI 5kWLoad Resistor, R 8Ω, 300 W

Diode, D STTH6010WZSI MOSFETs [SA, SB, SC and SD] APT28M120L

Capacitor, C1 and C2 ECE-T2VP182FA

DC source

The Magna Power LXI model was used as a DC source to the ZSI topology. The provided

a wide range of input voltage supply to test the ZSI.

Current sensors

Figure 2.21: LEM LA 55-P hall effectcurrent sensor connection

Figure 2.22: LEM LA 55-P hall effectcurrent sensor

The setup uses two LEM LA 55-P hall effect sensors to sense the input current iPV

and the AC output current i g. The current sensors can measure currents upto 50 A. The

current sensor output range is between ±5 V. The sensor connection schematic is shown

in Figure 2.21 and the LEM current sensor is shown in Figure 2.22.

dSPACE 1103 Rapid Prototyping Controller Board

The dSPACE controller board shown in Figure 2.23 is used to implement the controller

loop to generate the desired PWM technique to control the operation of the ZSI. The

40


Figure 2.23: dSPACE rapid prototyping controller board

dSPACE controller board can be fully programmable from the SIMULINK environment.

It has 20 16-bit analog to digital (A/D) channels and 8 digital to analog (D/A) channels.

The A/D channels can be used for reading the current sensor outputs. The A/D channel

have an input voltage range of ±10 V. In the simulink environment the voltage outputs

from the sensors are obtained through the A/D channels and multiplied by a gain to 100

to regenerate the actual analog current values.

Gate Drivers

Powerex BG2C gate drivers were used for driving the H-bridge inverter topology. These

are isolated gate drivers generating +15 V to -7 V gate-source voltages upto 60 kHz

signals to drive the inverter switches. the turn on and turn off time can be controlled by

changing the output gate resistors of the gate drivers. The gate driver board is shown in

Figure 2.24.

41


Figure 2.24: Powerex BG2C gate drivers

Figure 2.25: Experimental implementation of the PWM logic [2]

2.9.2 Results

The results for the ZSI prototype is presented in this section. The dSPACE controller

used to implement the PWM logic shown in Figure 2.5. The logic in Table 2.2 was

used to implement the shoot through state. This shoot through state is then added

to the conventional unipolar PWM logic generated for the VSI switches to obtain the

switching waveform shown by the waveforms SA, SB, SC and SD shown in Figure 2.5.

42


Figure 2.26: Input inductor current iL (blue:100 mv/A), the capacitor voltage Vc (red),the input voltage to the ZSI (pink: 40 V/div) and the the ZSI output current ig (green:100mV/A)

Figure 2.27: Input inductor current iL (blue:100 mv/A), the capacitor voltage Vc (red),the input voltage to the ZSI (pink: 40 V/div) and the the ZSI output current ig (green:100mV/A)

43


The experimental implementation of the PWM generation is shown in Figure 2.25.

Table 2.8: PI Controller Values for experimental results

Controller Loop P I

Input Current Loop 5e-3 1Output Current Loop 60e-3 0

The setup shown in Figure 2.17 is operated in closed loop with PI parameters shown

in Table 2.8. The converter is operated at two different input voltages emulating the

behavior of the topology working under different temperatures at a fixed load. The input

current has been maintained at the rated peak current of 3.82 A.

Figure 2.26 shows the experimental waveforms for the ZSI operating at an input

DC voltage of 38 V at a shoot through duty cycle of D0=0.2. The input current iL is

maintained at 3.8 A through closed loop control. A 8 ohm, 300 W resistor is connected at

the output of the inverter side. The capacitor voltages VC are maintained at 50V since

both the capacitors C1 and C2 and are connected in parallel in an average sense, the

average voltages across the inductors L1 and L2 are zero.

Figure 2.27 shows the results for the ZSI operating at an input DC voltage of 33 V

at a shoot through duty cycle of D0=0.255. The input current iL is maintained at 3.8 A

through closed loop control. The capacitor voltages VC are maintained around 50V.

One of the major challenges in the development of Z-source topologies is the layout

for its electrical circuit. The challenges increase with the increase of switching frequency

and power levels. The critical points in the circuit is shown in red in the Figure 2.25 [46].

These points have to be reduced as far as possible to reduce "ringing" problems which

appear at voltage overshoots on the voltage, VPN .

From Figure (2.5), the DC link current, IPN transitions from the region marked as

3 to the region marked as 4, IPN changes from 2iL to 0. From Figure (2.28), due to

the presence of possible parasitic inductances are present in the region 1, 2, 5 and 6

44


the current can form a LC resonant network between the parasitic inductances and

MOSFET drain-gate capacitance and cause voltage overshoots on the voltage VPN . Some

Figure 2.28: Critical points of a Z- source Single Phase inverter layout

of the design recommendations that can be taken while designing layouts are as folows:

1. Electrolytic capacitors are usually used in single phase inverters [47]. Electrolytic

capacitors take up large space which can cause layout issues. The lengths marked

by 1 and 2 in Figure (2.28) should be shortened as far as possible through proper

layouts to reduce parasitic inductances.

2. Film capacitors can also be used in conjunction with the electrolytic capacitors

to limit high frequency "ringing" at the DC input of the H-bridge inverter. The

capacitor can be sized as follows,

(2.25) iC = Cdvdt

(2.26) C >= 2iLD0

2∆ ˆVPN

3. H-bridge inverter modules can be used to reduce the lengths 5 and 6.

4. Design suitable higher gate resistances to dampen the ringing. Although increasing

the gate resistance can lead to higher switching losses.

45


5. Reduction of the lengths marked by 3, 4 and 7. The diode D should be a fast

recovery diode.

6. Selection of MOSFET internal resistance can help dampen the effect of the ringing

although it can increase the conduction losses in the topology.

7. Proper design of the PCB circuit layouts keeping in mind the points 1-7 mentioned

above. Use of short copper bus bars for connections can reduce ringing on the DC

side [46].

8. Use of snubber circuits can reduce ringing but increases design complexity and

layout requirements [48]-[50].

2.10 Conclusions

ZSI topology has gained a tremendous interest in photovoltaic grid connected applications

due to its single stage structure. It is an attractive solution for power converter topologies

requiring compact structures such as photovoltaic systems in residential applications.

For single phase residential applications, ZSI uses a conventional H-bridge converter

and passive components to match a lower input DC voltage the standard single phase

grid voltages.

Although ZSI provides high voltage gain for the input DC voltage, the active duty

cycle, D and the shoot-through duty ratio, D0 is coupled. For high boost operation, the

modulation index can be low which leads to poor outpur power quality. Decoupling the

two can lead to complicated controller design.

This chapter explains the basic operation of a ZSI and also the basic building blocks

for the practical implementation of a ZSI, PWM generation technique, control strategy

adopted and challenges for practical implementations.

46

CH

AP

TE

R

3A SINGLE PHASE TRADITIONAL Z SOURCE INVERTER

TOPOLOGY FOR PHOTOVOLTAIC/GRID INTEGRATED DC

CHARGER

This chapter presents modeling, design and operation of a modified Z-source inverter

(MZSI) integrated with a split primary isolated battery charger for DC charging applica-

tions. Simulation and experimental results have been presented for the proof of concept of

the operation of the proposed converter.

47

CHAPTER 3. A SINGLE PHASE TRADITIONAL Z SOURCE INVERTER TOPOLOGYFOR PHOTOVOLTAIC/GRID INTEGRATED DC CHARGER

Figure 3.1: Detailed Schematic of Proposed MZSI

3.1 Modified Z-source Inverter

Figure 3.1 shows a modified Z source inverter has been proposed having an integrated

charger. The two capacitors C1 and C2 from Figure 2.1 are split and each of them acts

as one of the legs of one of the two primaries of the split primary isolated half-bridge

converter. The MOSFET SR allows bidirectional operation of the MZSI when required.

The diode DPV blocks the reverse flow of current back into the PV. Rin is the internal

resistance of the input capacitor Cin. For a symmetrical operation of the MZSI, a split

primary isolated DC to DC converter has been proposed for the integration of the charger

side into the ZSI. The split primaries contain two half-bridge converters (HBC) primaries

isolated from a single full bridge secondary through a high-frequency transformer. The

HBC primaries and the secondaries are operated at 50% duty cycle in open loop. The

output current of the secondary is connected to an energy storage unit such as a lithium-

ion (Li-ion) battery. The energy storage unit clamps its own voltage, vB, across the input

48

3.1. MODIFIED Z-SOURCE INVERTER

of the HBC primaries, VC, such that,

(3.1) VC = 2vB

3.1.1 Maximum Shoot Through Duty Ratio, D0max

As a result of the energy storage unit being connected across the capacitors, the maximum

shoot through duty ratio, D0max is calculated based on the minimum input voltage,

vpvmin and the maximum battery voltage, VBmax connected across the capacitors and is

expressed as:

(3.2) D0max =2VBmax −vpvmin

4VBmax −vpvmin

SAE J1772 standard defines the standard battery voltages for DC charging between

200V-500V.

3.1.2 Inductor L1 and L2 Design

The inductors L1 and L2 are sized for high-frequency peak to peak current ripple assumed

between 15-25% of the inductor current during the shoot-through time interval D0T2 as

follow [39][41]:

(3.3) L1 = L2 = VCmaxD0max

2∆iLf

3.1.3 Capacitor C1 and C2 Design

The capacitors are sized to absorb the second order harmonic component in the capacitor

voltages as follow [39]:

(3.4) C1 = C2 = P2ω∆VCVC

where VC is the average voltage across the capacitors VC1 and VC2 and ∆VC is the

predetermined voltage ripple limit. ω is the second order harmonics expressed in rad/s.

49


In single phase Z source inverters, oversized electrolytic capacitors for second-order

harmonics suppression can result in a bulky system.

For the proposed topology, maximum capacitor voltage rating is equal to at least

twice the peak voltage of the energy storage device clamped across it. For triangular

inductor current waveform, an RMS current of 4 A is a reasonable assumption[51].

3.1.4 Average Modeling of the Integrated Half-Bridge DC-DC

Converter Charger

When an energy storage unit is connected to the secondary side of the charger then

each of the split primaries operates alternately and supplies half the required battery

current. Figure 3.2 shows the schematic of the topology. The voltage across the capacitors

is defined by the equation (3.1). The secondary side can be either an active rectifier or a

diode rectifier based on the power flow requirements. In this thesis, the secondary bridge

rectifier has been implemented using a diode bridge rectifier. For future developments,

the diode rectifier can be replaced by an active bridge to implement vehicle battery to

grid power flow (V2G). Figure 3.3 shows that when one of the primaries is connected to

the secondary for a duration of HBC2 secs. Each switch of one primary operates for HBC

4

secs. The detailed average modeling of the split primary DC-DC converter is explained

in [42][51].

Each of the two primaries can be represented using an RLE circuit connected parallel

to each of the capacitor, C1 and C2, as shown in the simplified equivalent model of Figure

3.4.

50


Figure 3.2: Isolated Split primary half bridge DC-DC converter schematic

Figure 3.3: Schemetic of one the Primary across CHB1 operating at 50% duty cycle

3.1.5 State Space Average Modeling of the Single Stage

Inverter Charger

The detailed state space average modeling was presented in [42]. The equivalent diagram

of the modeled MZSI is shown in the Fig. 3.4, During the non shoot-through state, the

KVL equation is given by:

(3.5) LdiL

dt= vpv − iLr+RHB + (2 i g + iB

2)RHB −VC

The KCL equation is:

(3.6) CdVC

dt= iL − i g − iB

4

51


Figure 3.4: Equivalent Model of the proposed Modified Z-source Inverter(MZSI) withbattery

During the shoot-through state, the KVL equation is:

(3.7) LdiL

dt=VC − iL(RHB + r)− iB

2RHB

The KCL equation is written as:

(3.8) CdVC

dt=−iL − iB

4

From equations (3.5)-(3.8), state space equations for the entire system can be written

as:

52


˙iL

VC

˙iB

=

−−(r+2RHB)L −1−2D0

L(1−2D0)

2L RHB

1−2D0C 0 − 1

4C

1−2D0LB

RHB1

2LB−RHB+RB

2LB

iL

VC

iB

+

2(1−D0)RHB

L

−1−D0C

− (1−D0)RHBLB

[

i g

]

+

(1−D0)

L

0

0

[vpv

]

+

0

0

− 1LB

[VB

](3.9)

Figure 3.4 shows the positive directions of the battery current, iB, and the grid side

AC current, i g.

Figure 3.5 shows the block diagram for the controller for the proposed MZSI topology.

It consists of three loops: the PV current i pv loop, grid current i g loop and the battery

current iB loop.

In literature, the ZSI capacitor voltage is controlled to generate the reference current

for the H-bridge inverter output current [52] or generate the shoot through duty ratio

D0 [38]. In this thesis, the reference current is generated by controlling the peak input

photovoltaic current [53]. If a stiff voltage VC is connected across either or both capacitors,

the shoot through duty ratio, D0, will depend on VC.

Since the battery current loop does not require fast dynamic changes battery loop

53


Figure 3.5: Block diagram of the Control Scheme Proposed Modified Z-source InverterCharger

control is the slowest response compared to the input current control. For the battery

loop control the transfer function is given by:

(3.10)IB(s)d0(s)

= −C[4RHB iL −2RHB id]s− [2iL − id]4LBCs2 +2C[RHB +2RB]s+0.25

A feedforward is added to the battery control loop,

(3.11) FFB = 2VB −vPV

4VB −vPV

where VB is the output voltage of the HBC and vPV is the tracked PV voltage. From

Figure 3.4 and equation (3.9), the transfer function for input current and the peak of the

reference AC output current is as follows:

(3.12)IL(s)

Îg(s)= 2CRHB(1−D0)s+ (1−D0)(1−2D0)

LCs2 +C(r+2RHB)s+ (1−2D0)2

The active duty cycle D is controlled by the output grid current control loop from the

following transfer function:

(3.13)Ig

D=

ˆVPN

Vtri

1L f s+ r

where Vtri is the peak of the triangular carrier wave. The output AC side current

controller should have the fastest response. The inverter mode is the worst case for

inverter/charge operations [54]. The controllers are tuned for inverter stage.

54


Figure 3.6: Simplified Block Diagram of the System

3.1.6 Energy Management Scheme for the Proposed Converter

Figure 3.6 shows a simplified block diagram of the proposed system. When a BESS is

integrated into a ZSI, the power equation can be written as [55]:

(3.14) vPV iPV = vb ib + i grmsvgrms

where ib and vb are the battery and voltage. The single phase AC grid power Pg balances

the power fluctuation of the photovoltaic source Ppv thus a constant charge power, PB, is

obtained at the ESS.

For EV battery charging using both the single phase AC grid and the photovoltaic

power, the direction of the AC grid current i g changes to negative while drawing power

from the grid.

The inverter side can be operated bidirectionally and the PV and the grid provides

power for the charger, maintaining the power balance.

(3.15) vPV iPV + i grmsvgrms = vb ib

As long as the voltage across the input capacitor Cin is maintained to at least

the minimum value of the PV voltage, the MZSI can be operated as a grid-connected

rectifier/charger in the absence of the PV [48]-[58].

55


Anti-islanding protection techniques for the ZSI topology have been addressed in the

literature previously in [59].

3.2 Challenges

Figure 3.7: Two MZSI connected in se-ries connected across one high voltagebattery

Figure 3.8: Two MZSI connected in par-allel for current sharing across one lowbattery voltage

The EV battery voltages vary between 200-500 V. The capacitor voltages VC1 and VC1

in the MZSI topology is such that:

(3.16) VC1 = 2VB

For a variation between 200-500 V, the capacitor voltage will be varying between 400-

1000 V. For the photovoltaic array parameters described in Table 2.5, the shoot through

duty ratio and modulation index varies inversely. At minimum PV voltage the maximum

shoot through duty ratio for a battery voltage of 500 V is 0.433. For two identical MZSI

operating in string configuration, the charger sides can be collected in series or parallel to

56

3.3. SIMULATION AND EXPERIMENTAL RESULTS

add up the output voltage or current sharing mode. Cascaded impedance source inverters

have gained tremendous interest for PV/grid connected applications [60] [61]. The size of

the ZSI can be further reduced at higher frequency operation [62].

In the series and parallel configuration shown in Figure 3.7 and (3.8) makes it

possible for the MZSI to operate in a thin band. The maximum shoot through duty ratio

is kept at 0.355 as long as the MZSI charger side operates in parallel below 250V and in

series above 250V battery voltage for a minimum voltage of 236 V. thereby maintaining

a minimum modulation index of 0.6.

3.3 Simulation and Experimental Results

3.3.1 Simulation Study for a MZSI Operation

Table 3.1: Isolated Split Primary HBC PWM Logic

Enable SAHB SAHB SAHB SAHB1 1 0 0 01 0 1 0 00 0 0 1 00 0 0 0 1

The simulation studies to demonstrate the behaviour of the proposed topology have

been carried out using PLECS 4 for a 3.3 kW charger for a string inverter configuration.

Simulation has been carried out for the system shown in Figure 3.1. The PWM logic for

the integrated split phase HBC is shown in Table 3.1.

The waveform for the logic in Table 3.1 is shown in Figure 3.9. Each of the HBC

MOSFETs operates for 25% of the HBC switching time period such that there is no

overlap. In practical implementations, a deadtime is introduced between the MOSFETs

long enough for the magnetizing current to die down in the primary.

57


Figure 3.9: Simulation Waveform for the PWM logic for the split primary half bridgeDC-DC converter

Figure 3.10 shows at simulation time t=1.75 s, the input PV power reduces from 2.8

kW to 2 kW, the grid power increases from 710 W to 1500 W to maintain the output

charger power to 3.3 kW and the corresponding grid current, DC link voltage, capacitor

voltage and the battery current is shown in Figure 3.11.

3.3.2 Loss Modeling

The loss modeling for the proposed system shown in Figure 3.2 has been carried out by

modeling the actual components in PLECS 4.0. The switching components used for the

modeling is shown in the Table 3.3,

58


Power Balance Curve

Time(s)1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

Pow

er(

W)

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

3000

3100

3200

3300

3400

Photovoltaic Power,Ppv

AC Grid Power,Pg

Battery Charge Power,PB

Figure 3.10: Simulation waveform for the power balance between the photovoltaic inputpower, the AC grid side and the battery power

For the loss modeling of the passive components, the internal resistance of the

inductors, L1, L2 and L f are r=100 mΩ and the ESR, RHB for the capacitors C1, C2 and

Cin are 138 mΩ.

Figure 3.12 shows the loss distribution between the ZSI (conduction and switching

losses of the MOSFETs and diode D), the HBC (conduction and switching losses of the

MOSFETs and secondary diodes) and other losses in due to the inductor, capacitors,

leakage losses in the high frequency transformer and battery series resistances in the

system for varying irradiations for a constant charging power PB=3.3 kW.

Figure 3.13 shows the peak efficiency is around 94% from the efficiency curve for

various ratios of AC Grid Power, Pg, to Photovoltaic Power, Ppv for a fixed charging power,

59


Grid Current, ig


Capacitor Voltage, VC

Battery Current, iB

ig (

A)

-10

-5

0

5

10

VPN

(V)

0

100

200

300

400

500VC (

V)

356

358

360

362

364

Time(secs)1.7 1.8 1.9 2.0 2.1 2.2 2.3

iB (

A)

18.15

18.20

18.25

18.30

18.35

18.40

18.45

Figure 3.11: Simulation Waveform of the grid current, i g, DC link voltage, VPN , CapacitorVoltage, VC1, and Battery current, ib for the power balance between the Photovoltaicinput power, the AC Grid side and the battery power for a step change in irradiationfrom 1000W /m2 to 500W /m2

PB=3.3 kW, for varying irradiation between 500W/m2 to 1000W/m2 and temperature

variations from 0 C to 60 C .The efficiency is the highest when the sharing between the

photovoltaic power Ppv and the grid power Pg is equal.

For a constant frequency of operation, the HBC MOSFET losses remain constant for

a fixed value VB and charging power, PB. Although in reality, this might not be the case.

The efficiency of the converter will change with the change in the battery voltage. Figure

3.12 shows the distribution of the losses between the ZSI losses, the HBC MOSFETs

and the losses due to the inductor, capacitors, leakage losses in the high-frequency

60


Table 3.2: Modified ZSI based Charger System Simulation Specifications

Parameters ValueInput Voltage, vpv 286 VInput Current, i pv 9.8 A

Inductor Value, L1=L2 560 uHZSI Switching Frequency, FSW 25 kHz

Grid Voltage (RMS), vg 240 VInverter Output Filter Inductor, L f 7.5 mH

PV Input Power, PPV 2.8 kWHBC Switching Frequency, fHBC 50 kHz

HBC Output Filter, LB 1 mHBattery charge power, PB 3.3 kW

Table 3.3: Component Models used for Loss Modeling of the Proposed System

Component Value


HBC MOSFETs [SAHB, SBHB, SCHB and SDHB] IXFN64N50PHBC Diodes, [S′

AHB, S′BHB, S′

CHB and S′DHB] STTH6010W

Capacitor, Cin, C1 and C2 ECE-T2VP182FA

transformer and battery series resistances in the system for various battery voltages.

For higher currents in the battery chargers, the conduction losses increase.

From Figure 3.14, at 45 C, the vpv drops to 258V and it can be observed that with

the increase in battery voltage the ZSI losses increase but the HBC losses and the losses

in the passive components reduce.

3.3.3 Experimental Setup

The experimental setup for the ZSI topology was implemented though a hardware-in-loop

setup with dspace 1103 rapid prototyping controller at the core of the controller. The

experimental setup for the Z source inverter topology is shown in Figure 3.15.

The list of components used in this experimental setup is shown in Table 3.4.

61


Figure 3.12: Loss distribution chart for the MZSI topology for a fixed charging powerPB=3.3 kW at 25 C, under varying irradiation

Figure 3.13: Efficiency curve for different ratios of AC Grid Power Pg to PhotovoltaicPower Ppv curve for a fixed charging power PB=3.3 kW at under varying photovoltaiccondition

DC Source

The Magna Power LXI model was used as a DC source to the ZSI topology. The provided

a wide range of input voltage supply to test the ZSI.

62


Figure 3.14: Loss distribution for various battery voltages,VB, for a fixed chargingpower,PB=3.3 kW, at 45 C

Table 3.4: ZSI Prototype Component Specifications

Component Specification

DC voltage source Magna Power LXI 5kWLoad Resistor, R 8Ω, 300 W


Capacitor, C1 and C2 ECE-T2VP182FA

Current Sensors

The setup uses two LEM LA 55-P hall effect sensors to sense the input current iPV and

the AC output current i g. The current sensors can measure currents upto 50 A. The

current sensor output range is between ±5 V. The schematic for the sensor connection is

shown in Figure 3.16 and the sensor is shown in Figure 3.17.

dSPACE 1103 Rapid Prototyping Controller Board

The dSPACE controller board is used to implement the controller loop to generate the

desired PWM technique to control the operation of the ZSI. The dSPACE controller board

can be fully programmable from the SIMULINK environment. It has 20 16-bit analog

to digital (A/D) channels and 8 digital to analog (D/A) channels. The A/D channels can

63


FIGURE 3.15. Experimental Configuration of the ZSI topology

be used for reading the current sensor outputs. The A/D channel have an input voltage

range of ±10 V. In the Simulink environment the voltage outputs from the sensors are

obtained through the A/D channels and multiplied by a gain to 100 to regenerate the

actual analog current values.

64


Figure 3.16: LEM LA 55-P hall effectcurrent sensor connection

Figure 3.17: LEM LA 55-P hall effectcurrent sensor

Figure 3.18: dSPACE rapid prototyping controller board

Gate Drivers

Powerex BG2C gate drivers were used for driving the H-bridge inverter topology. These

are isolated gate drivers generating +15 V to -7 V gate-source voltages up to 60 kHz

signals to drive the inverter switches. the turn on and turn off time can be controlled by

changing the output gate resistors of the gate drivers.

Isolated Split Primary Half-Bridge DC-DC Converter

For designing the split primary and the single secondary, the following methodology has

been adopted:

(3.17) N = E2AC∆BfHBC

65


Figure 3.19: Powerex BG2C gate drivers

Figure 3.20: Isolated Split primary half bridge DC-DC converter setup

where, AC is the crosssectional area of the core, ∆B is the swing in flux density during

the half period THBC2 , fHBC is the switching frequency for the converter and E is the

half-period average value of the induced voltage across the winding. Each primary

is operating alternately. From Figure 3.1, each primary voltage is impressed on the

secondary.

66


Figure 3.21: PWM logic for the isolated HBC

3.3.4 Proof of Concept of the MZSI Topology

In this paper as proof of concept, a scaled down 145 W experimental setup was built

using MATLAB/Simulink and dSPACE 1103.The electrical specifications for the setup

are shown in Table 3.5.

Table 3.5: Modified ZSI based Charger System Prototype Electrical Specifications

Parameters Value

Input Voltage, Vin 38 VInput Current, I in 3.82 A

Inductor Value, L1 & L2 560 uHPeak DC Link Voltage, VPN 63.33 V

Modulation Index, M 0.75Shoot Through Duty Ratio, D0MAX 0.2

Switching Frequency, FSW 25 kHzGrid Voltage, Vg 34 V(RMS)

Inverter Output Filter Inductor, L f 2.5 mHHBC switching frequency, fHBC 50 kHz

Figure 3.21 shows the PWM scheme for the HBC. Each of the split primary operate for

half the HBC switching period. Each MOSFET SAHB, SBHB, SCHB and SDHB operates

67


Figure 3.22: Experimental setup waveforms for the Inductor current(top), charger outputcurrent(middle) and the primary currents of the split charger(bottom)

exclusively for one quarter of the entire HBC switching period. Equation (3.22) can be

written in terms of the current sharing between the AC load (grid) and the battery as:

(3.18) iPV = 1−D0

2(1−2D0)ib +

Mp2 (1−2D0)

i g

where M is the modulation index and D0 is the shoot through duty ratio. For D0=0.2,

(3.19) iPV = 23

ib +p

32

i g

From equation (3.19), at D0=0.2, for an input current iPV =3.82 A and fixed HBC output

current ib=2 A, the ZSI AC output current i g is calculated to be 2.87 A.

Figure 3.22 shows the the inductor current iL1, the battery current iB and the split

primary current iCHB1 and iCHB2 and the total primary current. Each of the primary

68


Figure 3.23: Experimental waveform input current(blue) and output current(green)between the charger and the AC output of the MZSI

operate alternately. The total primary current is a high frequency alternating current of

fHBC=50 kHz.

From Figure 3.22 and Figure 3.23, the charger ouput current is maintained at 2 A

using a Chroma Programmable AC/DC Electronics Load(Model 6304). The PV input

current is maintained at 3.82 A using a Magna-power LXITM solar emulator. The output

grid current is observed to be 2.66 A.

Table 3.6: Isolated Split Primary Half Bridge DC-DC System Electrical Specifications

Parameters Value

Input Voltage, VC 50.667 VOutput Voltage , VB 25.335 V

Switching Frequency, Fsw(HB 50 kHzFilter inductor, LB 500 uH

The lower values of the output current is a result of the losses in the circuit. The

practical PI values for the AC side current control was KP=0.03 and the battery loop was

KPB=.0003 and K IB=.09 and the input PV current loop were KPin=0.005 and K I in=2.

69


3.4 Conclusions

A modified ZSI topology has been proposed in this chapter is an attractive solution

for photovoltaic/grid-connected charging systems. It consists of a single stage photo-

voltaic/grid connection and an integrated charger for energy storage. This topology can

be applied to the centralized configuration for charging in semi-commercial locations

such as a parking lot of a shopping mall. For residential applications, this idea can be

extended to string inverters with the charger side of the string inverter configurations

connected in series or parallel for current sharing. The chapter proposes MZI module for

cascaded architecture for PV/grid-connected charging application.

70

CH

AP

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4DC SIDE ACTIVE POWER FILTER(APF) FOR SECOND

ORDER HARMONIC SUPPRESSION IN IMPEDANCE

SOURCE INVERTERS

From Chapter 3 and chapter 4, it has been observed that the operation of a single phase

ZSI is heavily dependent on the electrolytic capacitors. Electrolytic capacitors can be

bulky and unreliable. In this chapter a DC side active power filter has been proposed and

presented which operates independent of the operation of the ZSI and eliminates the need

for electrolytic capacitors.

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CHAPTER 4. DC SIDE ACTIVE POWER FILTER(APF) FOR SECOND ORDERHARMONIC SUPPRESSION IN IMPEDANCE SOURCE INVERTERS

4.1 Origin of Second Order Harmonics in Solar

Inverters

In a single phase voltage source inverter system with unity power factor operation, the

inverter output load current and voltage can be expressed as,

(4.1) i g = Im sin(ωt)

(4.2) vg =Vm sin(ωt)

The output load power of the single phase inverter,

(4.3) Pg = vg ∗ i g = VmIm

2− VmIm

2cos(2ωt)

The second term in the above equation is the ripple term.

The filter inductor at the output of the inverter has an energy storage capability of,

(4.4) EL = 12

Li2g

Therefore,the energy stored in the output filter inductor,

(4.5) EL = 12

LI2m sin2(ωt)

The corresponding power is expressed as

(4.6) PL = 12

LωI2m sin(2ωt)

Assuming a lossless system, for a power flow from the photovoltaic to the AC load, power

at the DC link as seen by the impedance network is the sum of the load power, Pg,and

the inductor stored power, PL expressed as,

(4.7) PPN = Pg +PL

72

4.1. ORIGIN OF SECOND ORDER HARMONICS IN SOLAR INVERTERS

(4.8) PPN = VmIm

2− VmIm

2cos(2ωt)+ 1

2LωI2

m sin(2ωt)

The DC link power is a summation of the constant power, Pc and the ripple power Pr.

The constant power,

(4.9) Pc = VmIm

2

The ripple power,

(4.10) Pr =−VmIm

2cos(2ωt)+ 1

2LωI2

m sin(2ωt)

From (4.10), the ripple power can be expressed in the form of,

(4.11) Pr = Asin(2ωt+α)

where for unity power factor operation,

(4.12) Pr = 12

√(VmIm)2 + (LωI2

m)2 sin(2ωt+α)

where,

(4.13) α= tan−1(−Vm

LωIm)

where the peak ripple power from equation (4.12) as seen from the DC link is,

(4.14) Prpk =12

√(VmIm)2 + (LωI2

m)2

The peak ripple energy as shown from the DC link is,

(4.15) Erpk =Im

2ω

√(Vm)2 + (ωLIm)2

For a single-phase voltage source inverter (VSI), PPN is the input power drawn from

the PV also oscillates with the AC power at 120Hz. Photovoltaic systems are expected

to have a lifetime of 20-25 years. In single phase systems, the 2nd order harmonics

cause fluctuation in the system causing the photovoltaic array voltages and currents to

73


oscillate and thus decreasing its lifetime and efficiency. On the other hand, the second

order harmonics cause low-frequency oscillations on the DC link voltage at the inverter

input resulting in increased voltage stresses on the inverter switches. To suppress such

2nd order harmonic ripples various methods have been proposed in literature such as the

use of DC side active power filters (APF) [63]-[67] and control techniques [68]. Increasing

the capacitor size is one of the ways to suppress 2nd order harmonic ripples but the

presence of large electrolytic capacitors in any system can have the following effects:

1) The system volume becomes large.

2) Reduces the lifetime of the system.

3) Presence of higher ESL compared to a film capacitor introduces unwanted resonance

in the system.

4) Layouts can be an issue due to the presence of bulky capacitors.

The 2nd harmonic ripples if not controlled can cause the degradation of the lifetime of

electrolytic capacitors that are used in such high power systems in testing atmospheric

conditions. In systems such as photovoltaic inverters, these electrolytic capacitors can

raise serious reliability concerns.

In literature, there are both shunt and series APF have been reported [69]. A compar-

ative study between them showed that the series and shunt active filters more effectively

eliminate the current harmonics on the AC side and the voltage harmonics in the DC

side respectively. In a DC side APF the voltage across the capacitor of the APF, VS, is not

limited to a value below the DC link voltage VPN .

The energy stored in the APF capacitor CS [70],

(4.16)12

Cs(VS0 +12∆VS)2 − 1

2Cs(VS0 −

12∆VS)2 = CSVS0∆VS

74

4.2. PROPOSED DC SIDE ACTIVE POWER FILTER FOR ZSI

This energy stored is the same as expressed by equation (4.15). The sizing of the

DC side APF capacitor CS is inversely proportional to the voltage expected across it.

From equation (4.16), the energy stored in the capacitor CS depends on the capacitance

value and the voltage applied across VS. In systems such as Z source inverters where the

operation depends on the behavior of the passive components, any unwanted parasitic in-

ductances can form a resonance circuit inside the topology and cause voltage oscillations

at the input of the H bridge inverter switches [46].

For single phase Z source inverters, various methods have been proposed to reduce

the second order harmonics through PWM techniques [47][71], controllers [53] [72] and

active power filters (APF) [73][74]. Component sizing of ZSIs or QZSIs to suppress second

order harmonics can result in large component size [47][75]. An AC side active power

filter was proposed in [76] for a QZSI. Operation of an APF at the AC output side of a

ZSI or QZSI can be challenging to design and the APF capacitor voltage is restricted to

less that of the DC link.

The DC link power PPN in single-phase inverters is expressed by the equation (4.8).

The 2nd harmonic component term Pr gets stored in the various components of the

impedance network. It is essential that the 2nd harmonic suppression using APF is done

between the impedance network and the H bridge inverter or on the inverter output side.

4.2 Proposed DC Side Active Power Filter for ZSI

In most DC side APFs reported in the literature, the APF inductor has been designed to

operate in the discontinuous mode to reduce losses in the inductor and to make the APF

capacitor the main passive component to temporarily store the second order harmonic

energy storage before injecting it back into the system [77][78] .

A DC side Active Power Filter (APF) for reduction of second-order harmonics for

QZSI topology was first proposed in [79]. The topology under study is a bidirectional

75


Figure 4.1: Proposed DC side shunt active power filter for ZSI topology.

Figure 4.2: Schematic of a ZSI topology with proposed DC side shunt active power filter.

Figure 4.3: Schematic of a QZSI topology with proposed DC side shunt active power filter.

buck-boost converter shown in Figure 4.1. The average voltage of the APF capacitor VS

is higher than the peak DC link voltage of the z source converter. The ripple voltage of

the APF ∆VS can also be large to reduce the size of the capacitor.

For a Z-source inverter, if the DC link current exceeds the input current, the diode D

76

4.2. PROPOSED DC SIDE ACTIVE POWER FILTER FOR ZSI

Figure 4.4: Block Diagram of the control strategy of the APF.

switches off causing the source to get disconnected from the load during an active state.

Which causes a DC link voltage to dip and distortions in the output current.

Therefore, conventional APFs operating in discontinuous mode cannot be used in ZSI.

In discontinuous mode, the peak current is the APF is twice the average current which

can drive the ZSI into the unwanted shoot through states which results in dips in the

DC link voltage, VPN .

4.2.1 Capacitor CS Design

The capacitor CS is designed according to equation (4.15) and (4.16). The minimum

voltage across the capacitor Cs should be,

(4.17) Vsmin > Vin

(1−2D0)(1−D)

where D is the duty cycle of the buck-boost converter and D0 is the shoot through duty

ratio and Vin is the input DC voltage of the DC source to the ZSI. This equation ensures

that the average APF capacitor voltage is always maintained above the DC link voltage,

VPN .

77


From (4.16), the peak to peak ripple voltage of the capacitor should be such that,

(4.18) VS(pk−pk)ripple < 2D∗100%

where D is the duty cycle of S2 of the APF. The RMS current rating of the capacitor [77],

(4.19) IS(RMS) =Prp2 Vc

4.2.2 Inductor LS Design

The inductor for the APF is designed for a continuous mode of operation. While storing

the second harmonic energy, it behaves like a boost converter with the voltage of the APF

capacitor at a higher voltage than the DC link. The inductor value can be calculated as,

(4.20) L ≥ VS −VPN

2IL fs(1−D)

4.3 Controller Design

A dual loop controller has been adopted to maintain the output voltage of the capacitor

and control the input current of the APF. Figure 4.4 shows the controller block diagram.

The reference voltage of the APF capacitor, CS, is decided by the equation (4.17). The

voltage loop generates the average APF current. The 120 Hz current component is added

to the average current component to generate the reference current for the current

control loop.

4.3.1 Determination of the Second Harmonic Current

The 120Hz component in a single phase H-bridge inverters can estimate easily from

the DC link current. In Z -source inverters, the presence of the impedance network and

the shoot-through condition can make the estimation of the 120Hz component quite

challenging. A second-order notch filter can be used to extract the 120Hz component from

78


the DC link current (between the impedance network) and the H-bridge inverter configu-

ration shown in Figure 4.2 and Figure 4.3. The notch filter can be expressed as follow [80],

(4.21) KR(s)= 2ζhωss2 +2ζhωs+ (hω)2 ∗Kh

Where the damping factor ζ =0.01, ’h’ is the harmonic multiple of the fundamental

frequency, h=2, and Kh is the gain at that frequency. This transfer function acts as a

bandpass filter.

For the voltage control of the APF capacitor, a PI controller has been used. The output

of the voltage control loop generates the average current of the APF. The inner current

controller can be implemented using Hysteresis Current Control (HCC) or through PI

controller shown in APPENDIX A.

The controller design for the active power filter can be implemented using various

advanced controllers such as Model Predictive Control (MPC) [81].

4.4 Simulation Results

The simulation studies have been carried out using PLECS 4. Simulation results have

been shown for electrical parameters shown in Table 4.1.

Figure 4.5: Schematic Diagram of the simulation circuit

79


Table 4.1: ZSI Simulation Specifications

Parameters Value

Input Voltage, vpv 286 VInput Current, i in 9.8 A

Inductor Value, L1=L2 560 uHCapacitance Value, C1=C2 5000 uFPeak DC Link Voltage, VPN 433 V

Modulation Index, M 0.8Shoot Through Duty Ratio, D0MAX 0.1697

Switching Frequency, FSW 25 kHzInverter Output Voltage,vg 240 V(RMS)

Inverter Output Filter Inductor, L f 7500 uH

Figure 4.6: Simulation waveform of a ZSI operating operating at steady state withvin=286 V, iL=9.8 A, DC link voltage VPN=433 V and D0=0.1697 without APF with astep change at t=1.75 secs

The results of the simulation studies for the system in Figure 4.5 with electrical

parameters shown in Table 4.1 has been shown in Figure 4.6. At the rated power of 2.8

kW, inductor current has considerable second order harmonic ripple along with high-

frequency ripple. The peak to peak inductor current ripple is 4.8 A. The presence of the

80


Figure 4.7: Simulation waveform of a ZSI operating operating at steady state withvin=286 V, iL=9.8 A, DC link voltage VPN=433 V and D0=0.1697 with APF with a stepchange at t=1.75 secs

Table 4.2: APF parameters

Parameters Value

Capacitor Voltage, CS 600VCapacitance Value, CS 400 uF

Inductor Value, LS 250 uH

second harmonics causes the DC link voltage to oscillate around the peak value causing

stresses on the switches. The second harmonic peak-peak voltage ripple is observed to be

5.4 V. The waveforms show the inverter output current, the inductor current, the DC link

voltage and the input volt-ampere (VA) to the ZSI. Without the APF, the input power

to the ZSI is seen oscillating about its mean power, which can cause the life of the DC

source to degrade. To achieve a DC link voltage ripple of 1%, from equation (2.16), the

capacitance C1 and C2 is calculated to be 5000 uF.

Simulation results for the ZSI system with APF is shown in Figure 4.7. The inductor

current, iL, ripple is completely reduced. Only the high-frequency ripple remain. The

81


DC link voltage has been regulated to its natural peak voltage VPN . As seen from the

waveform, the second harmonics input power ripple is completely removed. As a result,

the required inverter switch voltage ratings, the VA rating of the inverter and the

capacitance required is reduced considerably. As a result, the capacitance is designed

only for the high-frequency shoot-through state: [50],

(4.22) C = 2iLD0max

rV VC fSW

where T0max is the duration of the peak shoot through from equation (2.13). iL is the

average inductor current, B is the peak gain of the ZSI and rV is the allowed high-

frequency ripple voltage. For D0max of 0.345, peak DC link voltage, VPN=764 V, and

I in=9.8 A, the calculated value of capacitors is 35uF. A filter capacitor value of 50

uF, 600V is a reasonable choice for the ZSI impedance network capacitors. Thus the

capacitance is reduced by 100 times from 5000 uF to 50 uF.

4.5 Conclusions

This chapter proposes a DC side active power filter (APF) which operates independently

of the operation of the ZSI topology. It is able to eliminate the need for bulky electrolytic

capacitors. the capacitance is reduced by 100 times from 5000 uF to 50 uF. With the

elimination of bulky electrolytic capacitors, compact ZSI topologies can be designed

using more reliable film capacitors. One of the main advantages of this topology is that

the APF capacitor voltage, VS can be controlled and maintained above the DC link

voltage, VPN . This provides the flexibility of reducing the size of the APF capacitance,

CS by increasing the APF capacitor voltage, VS. Photovoltaic/grid connected cascaded

charging topologies proposed in this thesis can be designed in very compact structures

for residential applications where space in a constraint.

82

CH

AP

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5CONCLUSION AND FUTURE WORK

Photovoltaic/Grid connected EV chargers are attractive solutions for residential charging

infrastructures. ZSI topology module provides an attractive solution for such applications.

ZSI topologies are very good candidates for string inverters configurations in solar/grid

interconnected inverter systems.

The modulation index of a ZSI is coupled with the shoot through duty ratio it operates

at. During high voltage boost operation requirements, i.e, at high shoot-through duty

ratios, the modulation indices are poor which can lead to poor output power quality and

higher losses if operated over a long period of time. The proposed 3.3 kW MZSI charger

topology operates between minimum modulation index of 0.6 to 0.9 for battery voltages

200-500 V for PV voltages varying between 236-286 V. The PV voltage is based on of

string configuration of 8 series connected PV panels having a total power rating of 2.8

kW. When two such strings are connected to individual ZSIs, the resultant photovoltaic

systems are capable of producing 5.6 kW. When each of the ZSI is modified to a MZSI,

then each MZSI is designed to supply 3.3 kW to the battery connected to the charger.

The charger size of the MZSIs if connected in series or parallel as per requirement can

83

CHAPTER 5. CONCLUSION AND FUTURE WORK

supply up to 6.6 kW. The peak efficiency of each MZSI supplying 3.3 kW power to the

charger was observed to be around 94% for equal power sharing between the grid and

the PV for a battery voltage of 360 V under varying conditions for PV.

For the proposed charging system, when battery voltages vary between 200V-500

V, the capacitor voltages vary between twice the minimum battery voltage to twice the

fully charged battery voltage. For high battery voltages, the MZSI will be operating

at low modulation indices unless the shoot through duty cycle D0 is decoupled from

the active duty cycle D. Decoupling of D0 and D can result in complicated control

systems design requirements for a centralized configuration. For the proposed topology,

the converter operates between D0min to Dmax for vpvmax to vpvmin respectively. The

cascaded configuration of the proposed system has the following advantages:

1. Single point of fault is avoided.

2. ZSI has a compact structure due to the reduced number of stages.

3. Galvanic isolation is available between the charger side and the PV and Grid.

4. Provides an opportunity to step up the charging power levels by adding such

converters.

5. Any battery voltage levels can be charged by changing the charger side of the

converter between voltage sharing or current sharing.

6. Due to the dependency on the size of passive components, higher frequency MZSI

can be designed using wide-band-gap (WBG) devices.

5.0.1 Contributions

1. A 3.3 kW MZSI was designed and efficiency analysis was carried out using PLECS

Under variable irradiation and temperature changes it was found out that the

84

MZSI maintains a efficiency of around 94%. From the efficiency curves, it was

observed that the efficiency is maximum when there is equal sharing of power

between the AC grid and the PV. This topology has been proposed as a module

for a cascaded architecture for charging of EVs. For charging of EVs battery pack

voltages of 200-500 V, two MZSI charger side can be connected in series or parallel

to match the charger output voltage requirements resulting in a 6.6 kW charger.

The inverter side, as a result, operates at a minimum modulation index of 0.6 or

higher maintaining power quality.

2. Transfer functions for the controller design has been presented with guidelines for

implementing advanced controllers. The controllers should be designed such that

the grid current control loop should have the fastest response followed by the input

current loop. The battery current control loop should be the slowest. As seen from

the simulation results for the controller parameters the battery current ripple is

maintained under 1% and the grid current THD is maintained less than 5% as

required by the IEEE 1547 standard even under varying photovoltaic conditions.

3. Implementation of a MZSI for the proof of concept has been developed. The proof

of concept has been developed and shown for inverter operation. Power flow from

the grid into the charger has not been shown in this thesis but in literature, the

rectifier operation of the ZSI has been covered extensively and the proposed MZSI

can be validated. The switching logic for the integrated split primary half-bridge

DC/DC converter has been shown. The inverter output current is maintained under

5% as required by IEEE 1547.

4. To reduce the size of the system, a DC side active power filter has been proposed

which eliminates the need for bulky electrolytic capacitors. It operates indepen-

dently of the operation of the ZSI. It reduces the capacitance required from 5000uF

to 50 uF for a 2.8 kW ZSI. This facilitates the use of film capacitors which can help

85


in extending the life of the converter. The size of the inductors has been designed

for the high-frequency shoot-through state. By optimizing and further design itera-

tions, this topology can be made even more compact at a higher operating switching

frequency.

5.0.2 Future Work

1. Vehicle to Grid (V2G) operation of the MZSI charger. If the secondary side of the

HBC charger is controlled then the battery can be discharged through the charger

into the AC side of the power converter. The controls of the ZSI is able to inherently

control the power factor.

2. Experimental implementation of the Active Power Filter and Efficiency analysis

of the ZSI with and without the APF. The modeling, control, efficiency calculation

and the performance of the APF can be evaluated. One of the main advantages of

this topology is that it operates independent of the ZSI topology, Different control

schemes can be used to check for an optimized performance.

3. Design and implementation of a modified Quasi-Z-source converter for a cascaded

configuration.

Quasi-Z-source inverter was first proposed in [82]. have some advantages over

traditional ZSIs such as inherent constant input current, lower voltage ratings

of one of the capacitors and lower EMIs. Photovoltaic/Grid connected QZSI with

BESS integrated systems have drawn tremendous interest [83]. Figure (5.1) shows

the schematic of a PV/Grid connected QZSI. QZSI topology can be modified by

integrating a half bridge converter as shown in figure (5.2): The proposed QMZSI

is very similar to the topology proposed using the traditional ZSI proposed in this

system. The capacitors CHB1UP and CHB1LOW are the split capacitors from the

86

Figure 5.1: Schematic of PV/Grid interconnected QZSI

Figure 5.2: Schematic of a modified PV/Grid interconnected QZSI (MQZSI)

original QZSI topology capacitor. The form one of the legs of the integrated HBC

topology. One of the advantages of this MQZSI is the avoidance of the split primary

high-frequency transformer in the proposed MZSI. It is also providing isolation to

the battery side from the PV and the grid. The experimental implementation of the

87


MQZSI is going to be a very interesting work. This work can be further extended to

a string configuration shown in figure (5.3): Component sizing, modeling, efficiency

analysis for different modes can be done as a part of the future work.

88

PUBLICATIONS

Transactions

1. S. A. Singh, G. Carli, N. A. Azeez and S. S. Williamson, "Modeling, Design, Con-

trol, and Implementation of a Modified Z-Source Integrated PV/Grid/EV DC

Charger/Inverter," in IEEE Transactions on Industrial Electronics, vol. 65, no.

6, pp. 5213-5220, June 2018. doi: 10.1109/TIE.2017.2784396.

2. D. Ronanki, S. A. Singh and S. S. Williamson, "Comprehensive Topological Overview

of Rolling Stock Architectures and Recent Trends in Electric Railway Traction

Systems," in IEEE Transactions on Transportation Electrification, vol. 3, no. 3, pp.

724-738, Sept. 2017. doi: 10.1109/TTE.2017.2703583.

Conference

1. S. A. Singh, G. Carli, N. A. Azeez, A. Ramy and S. S. Williamson, "Modeling and

power flow control of a single phase photovoltaic/grid interconnected modified Z-

source topology based inverter/charger for electric vehicle charging infrastructure,"

IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society,

Florence, 2016, pp. 7190-7196. doi: 10.1109/IECON.2016.7793537

2. S. A. Singh, G. Carli, N. A. Azeez and S. S. Williamson, "A modified Z-source con-

verter based single phase PV/grid inter-connected DC charging converter for future

89


transportation electrification," 2016 IEEE Energy Conversion Congress and Expo-

sition (ECCE), Milwaukee, WI, 2016, pp. 1-6. doi: 10.1109/ECCE.2016.7854708.

3. S. A. Singh, N. A. Azeez and S. S. Williamson, "Capacitance reduction in a single

phase Quasi Z-Source Inverter using a hysteresis current controlled active power

filter," 2016 IEEE 25th International Symposium on Industrial Electronics (ISIE),

Santa Clara, CA, 2016, pp. 805-810. doi: 10.1109/ISIE.2016.7744993.

4. S. A. Singh, N. A. Azeez and S. S. Williamson, "A new single-stage high-efficiency

photovoltaic(PV)/grid-interconnected dc charging system for transportation electri-

fication," IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics

Society, Yokohama, 2015, pp. 005374-005380. doi: 10.1109/IECON.2015.7392948.

90

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102

AP

PE

ND

IX

APLECS 4.0.4 SIMULATION CIRCUITS

ZSI PWM Generation

Figure A.1: Circuits for ZSI PWM generation

103

APPENDIX A. PLECS 4.0.4 SIMULATION CIRCUITS

ZSI shoot-through state generation

Figure A.2: ZSI shoot-through state generation

HBC PWM generation

Figure A.3: ZSI shoot-through state generation

104

ZSI output current controller

Figure A.4: ZSI output current controller

ZSI input current controller

Figure A.5: ZSI input current controller

105


Battery current controller

Figure A.6: Battery current controller

Capacitor voltage controller

Figure A.7: Capacitor voltage controller

106

Schematic of the ZSI

Figure A.8: Schematic of the single phase grid connected ZSI

Schematic of the MZSI

Figure A.9: Schematic of the proposed MZSI topology

107


Schematic of the controller for the proposed DC side

APF

Figure A.10: Schematic of Operational Amplifier based Implementation of HysteresisCurrent Control (HCC)

108

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