Pentium® 4 Processor Block Diagram€¦ · Pentium® 4 Processor Block Diagram FP RF FMul FAdd MMX...

PentiumPentium ®® 4 Processor 4 Processor Block DiagramBlock Diagram

FMulFMulFAddFAddMMXMMXSSESSE

FP moveFP moveFP storeFP store

ace L2 Cache and ControlL2 Cache and Control

-- Cac

-- TLBTLB

StoreStoreAGUAGULoadLoadAGUAGU

ALUALU

ALUALUT

BTBBTB

uCodeuCodeROMROM

-- TLBTLB

L2 Cache and ControlL2 Cache and Control

Fall 2000

NetburstNetburst TMTM MicroMicro --architecture architecture Pipeline Pipeline vsvs P6P6

11 22 33 44 55 66 77 88 99 1010

FetchFetch FetchFetch DecodeDecode DecodeDecode DecodeDecode RenameRename ROB RdROB Rd RdyRdy/Sch/Sch DispatchDispatch ExecExec

Basic P6 PipelineBasic P6 Pipeline

Hyper pipelined Technology enables industry leading performance and clock rate

Hyper pipelined Technology enables industry Hyper pipelined Technology enables industry leading performance and clock rateleading performance and clock rate

Basic PentiumBasic Pentium ®® 4 Processor Pipeline4 Processor Pipeline

11 22 33 44 55 66 77 88 99 1010 1111 1212TC TC Nxt Nxt IPIP TC FetchTC Fetch DriveDrive AllocAlloc RenameRename QueQue SchSch SchSch SchSch

1313 1414DispDisp DispDisp

1515 1616 1717 1818 1919 2020RFRF ExEx FlgsFlgs Br CkBr Ck DriveDriveRF RF

Intro at Intro at ≥≥≥≥≥≥≥≥ 1.4GHz1.4GHz

.18.18µµ

Intro at Intro at 733MHz733MHz

.18.18µµ

Fall 2000Hyper pipelined TechnologyHyper pipelined Technology

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

33 44 55 66 77 88 99 1010 1111 1212TC FetchTC Fetch DriveDrive AllocAlloc RenameRename QueQue SchSch SchSch SchSch

1515 1616 1717 1818 1919 2020RFRF ExEx FlgsFlgs Br CkBr Ck DriveDriveRF RF

TC Nxt IP: Trace cache next instruction pointerPointer from the BTB, indicating location of

next instruction.

22TC TC Nxt Nxt IPIP

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

22 33 44 55 66 77 88 99 1010 1111 1212TC FetchTC Fetch DriveDrive AllocAlloc RenameRename QueQue SchSch SchSch SchSch

1515 1616 1717 1818 1919 2020RFRF ExEx FlgsFlgs Br CkBr Ck DriveDriveRF RF TC TC Nxt Nxt IPIP

TC Fetch: Trace cache fetchRead the decoded instructions (uOPs) out of the Execution Trace Cache

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Drive: Wire delayDrive the uOPs to the allocator

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Alloc: AllocateAllocate resources required for execution. Theresources include Load buffers, Store buffers, etc..

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Rename: Register renamingRename the logical registers (EAX) to the physicalregister space (128 are implemented).

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Que: Write into the uOP QueueuOPs are placed into the queues, where they

are held until there is room in the schedulers

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Sch: ScheduleWrite into the schedulers and compute dependencies. Watch for dependency to resolve.

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Disp: DispatchSend the uOPs to the appropriate execution

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

RF: Register FileRead the register file. These are the source(s)

for the pending operation (ALU or other).

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Ex: ExecuteExecute the uOPs on the appropriate execution

FopFop

FmsFms

AGUAGU

ALUALUALUALU

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Flgs: FlagsCompute flags (zero, negative, etc..). These

are typically the input to a branch instruction.

ALUALUALUALU

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Br Ck: Branch CheckThe branch operation compares the result of the

actual branch direction with the prediction.

ALUALUALUALU

FopFop

FmsFms

-- Cac

-- TLBTLB

AGUAGU

ALUALUALUALU

BTBBTB

ROMROM

-- TLBTLB

Drive: Wire delayDrive the result of the branch check to the front

end of the machine.

Fall 2000

The Execution Trace CacheThe Execution Trace Cache

-- Cac

-- TLBTLB

FMulFMulFAddFAddMMXMMXSSESSE

FP moveFP moveFP storeFP store

StoreStoreAGUAGULoadLoadAGUAGU

ALUALU

BTBBTB

uCodeuCodeROMROM

-- TLBTLB

BTBBTB

Fall 2000Execution Trace CacheExecution Trace Cache

�� Advanced L1 instruction cacheAdvanced L1 instruction cache––Caches Caches ““ decodeddecoded ”” IAIA--32 instructions (uops)32 instructions (uops)

�� Removes decoder pipeline latencyRemoves decoder pipeline latency

�� Capacity is ~12K Capacity is ~12K uOps uOps

�� Integrates branches into single lineIntegrates branches into single line––Follows predicted path of program executionFollows predicted path of program execution

Execution Trace Cache feeds fast engineExecution Trace Cache feeds fast engineExecution Trace Cache feeds fast engine

Fall 2000

1 1 cmpcmp2 br 2 br --> T1 > T1

... (unused code)... (unused code)

T1:T1: 3 sub3 sub4 br 4 br --> T2> T2....... (unused code)... (unused code)

T2:T2: 5 5 movmov6 sub6 sub7 br 7 br --> T3> T3

... (unused code)... (unused code)

T3:T3: 8 add8 add9 sub9 sub

10 10 mulmul11 11 cmpcmp12 br 12 br --> T4> T4

Execution Trace CacheExecution Trace Cache

Trace Cache DeliveryTrace Cache Delivery

10 mul 11 cmp 12 br T4

7 br T3 8 T3:add 9 sub

4 br T2 5 mov 6 sub

1 cmp 2 br T1 3 T1: sub

Pentium® 4 Processor Block Diagram€¦ · Pentium® 4 Processor Block Diagram FP RF FMul FAdd MMX...

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